Chip packaging structure and electronic equipment

Abstract

The utility model provides a chip packaging structure and electronic equipment. The chip packaging structure comprises at least one chip, a carrier plate, a heat conduction insulating layer and a packaging shell. The bottom surface of the chip is installed on the carrier plate, and the heat conduction insulating layer and the chip are packaged in the packaging shell. The packaging shell comprises a heat dissipation piece and a plastic packaging piece, in the first direction, the carrier plate, the chip, the heat conduction insulating layer and the heat dissipation piece are sequentially arranged in a stacked mode, at least part of the top face of the chip, the heat conduction insulating layer and the heat dissipation piece make contact in sequence, and the surface, deviating from at least one chip, of the heat dissipation piece in the first direction is exposed relative to the outer surface of the plastic packaging piece; wherein the first direction is parallel to the thickness direction of the chip packaging structure, and the top surface and the bottom surface of the chip are arranged back to back in the first direction. The heat dissipation capability of the chip packaging structure can be improved, and stable work of the chip is facilitated.

Description

Technical Field

[0001] The present application relates to the field of electrical components, and in particular to a chip packaging structure and electronic equipment. Background Art

[0002] Chip packaging is to encapsulate the chip in a packaging shell and lead the chip electrodes out of the packaging shell so that the packaged chip packaging structure and other structures can be electrically connected. On the one hand, by encapsulating the chip in a packaging shell, a stable working environment can be provided for the chip to prevent external moisture, dust, etc. from contacting the chip circuit and corroding and interfering with it, causing the electrical performance to deteriorate, thereby interfering with the operation of the chip or even the electronic equipment. On the other hand, by encapsulating the chip, the packaged chip can also be made as a stable whole, which is convenient for batch transportation and modular installation.

[0003] A general chip packaging structure includes a chip, a carrier board and a packaging shell. Among them, the bottom surface of the chip is mounted on the carrier board by curing a curing material (such as glue), and the plastic packaging shell formed by curing the plastic packaging material encapsulates the chip and the carrier board to form a chip packaging structure. Here, it can be understood that the plastic packaging shell formed after the plastic packaging material is cured serves as the entire packaging shell of the chip packaging structure.

[0004] However, as the performance of current chips gradually becomes stronger, their power consumption is also gradually increasing. The increasing heat generation makes the temperature of the chip rise. High temperature will cause the electrons of the components inside the chip to increase, and the transmission speed of the circuit signal will decrease, resulting in a decrease in the working speed and computing efficiency of the chip, affecting the performance of the chip. At the same time, high temperature also has a great impact on the life of the chip and the carrier board. Faced with chips with increasing thermal power, the aforementioned chip packaging structure exposes the problem of poor heat dissipation performance.

[0005] First, the heat dissipation effect of the chip packaging structure is not good. When dissipating heat, the chip packaging structure mainly exchanges heat with the outside air through the plastic packaging shell formed by the solidification of the plastic packaging material to complete the heat dissipation process. However, due to the large thermal resistance of the plastic packaging material, the heat exchange efficiency between the chip packaging structure and the air is low, resulting in the chip packaging structure being unable to dissipate heat well, which in turn causes the chip inside the chip packaging structure to be unable to dissipate heat in time, resulting in its temperature being too high.

[0006] Secondly, the thermal conductivity inside the chip packaging structure is not good. On the one hand, the heat generated by the chip is difficult to transfer to the outer surface of the plastic shell, resulting in a large temperature difference between the chip and the outer surface of the plastic shell, and it is difficult for the chip to dissipate heat. On the other hand, in order to balance power consumption and performance, some chips in electronic devices currently adopt a large and small core (i.e., large chip and small chip) architecture. In high-load scenarios, the high-power large core is responsible for the main work. At this time, the large core has a higher temperature, while the small core has a lower temperature due to its lower power, resulting in a large temperature difference between the two. In addition, the gap between the chips is filled with cured plastic packaging materials, which have poor thermal conductivity, so the large core accumulates more heat and cannot be dissipated. The large temperature difference between the large and small cores will greatly affect the chip life and performance.

[0007] It can be seen from the above that the existing chip packaging structure has poor heat dissipation performance, which is not conducive to the stable operation of the chip. Utility Model Content

[0008] The embodiments of the present application provide a chip packaging structure and an electronic device, which solve the problem that the chip packaging structure in the prior art has poor heat dissipation performance and is not conducive to stable operation of the chip.

[0009] The present application provides a chip packaging structure, including at least one chip, a carrier, a heat-conducting insulating layer and a packaging shell. The bottom surface of the at least one chip is mounted on the carrier, and the heat-conducting insulating layer and the at least one chip are packaged in the packaging shell.

[0010] The packaging shell includes a heat sink and a plastic package. In a first direction, a carrier, at least one chip, a thermally conductive insulating layer and a heat sink are stacked in sequence, and at least a portion of the top surface of at least one chip, the thermally conductive insulating layer and the heat sink are in contact with each other in sequence. The surface of the heat sink facing away from the at least one chip in the first direction is exposed relative to the outer surface of the plastic package. The first direction is parallel to the thickness direction of the chip packaging structure, and the top surface and bottom surface of the at least one chip are facing each other in the first direction.

[0011] This may be understood as follows: in a first direction, the chip, the thermally conductive insulating layer and the heat sink are stacked and contacted in sequence, thereby forming a heat dissipation channel inside the chip packaging structure: the chip acts as a heat-generating device, and the heat generated by it is transferred to the heat sink through the thermally conductive insulating layer, and the heat sink with better heat dissipation capacity exchanges heat with the air, completing the entire heat dissipation process.

[0012] Compared with the method in which the heat generated by the chip in the fully plastic-encapsulated structure is transferred to the outer surface of the plastic-encapsulated shell and the heat is dissipated by heat exchange between the plastic-encapsulated shell and the air, the heat dissipation method of the chip packaging structure provided by the embodiment of the present application is obviously more efficient. This makes the temperature lower when the chip generates the same amount of heat, and the heat that can be tolerated is greater when the chip temperature is the same. It is conducive to adapting chips with stronger performance and higher power consumption, and better ensuring their stable operation and releasing their performance.

[0013] At the same time, the packaging shell composed of the heat sink and the plastic sealing member still encapsulates the chip inside, so that the chip's heat dissipation performance is enhanced while still ensuring the chip's stability and safety.

[0014] In summary, the chip packaging structure provided in the embodiment of the present application has good heat dissipation performance, which is conducive to the stable operation of the chip.

[0015] In some embodiments, the heat sink includes a first heat sink, and in a first direction, at least a portion of the top surface of at least one chip, the thermally conductive insulating layer, and the heat sink are in contact in sequence, and a surface of the first heat sink facing away from the at least one chip in the first direction is exposed relative to an outer surface of the plastic package. By configuring the heat sink to include the first heat sink, on the one hand, the difficulty of chip packaging is reduced, and on the other hand, the cost of the heat sink is relatively low, which is beneficial to the cost control of the entire chip packaging structure.

[0016] In some embodiments, the heat sink also includes a plurality of second heat sinks, each of which is in a stepped structure and includes a first part and a second part, one end of the first part is connected to the outer edge of the first heat sink, and the other end is connected to one end of the second part; the first part is encapsulated in a plastic package, and the surface of the second part away from the thermally conductive insulating layer constitutes at least part of the outer side of the packaging shell. On the one hand, by providing a second heat sink, part of each side of the chip packaging structure is also used as a heat dissipation surface for heat dissipation, further improving the heat dissipation performance of the heat sink. On the other hand, by setting the second heat sink as a stepped structure, the outer peripheral edge of the top of the chip packaging structure is still filled with the plastic package, thereby ensuring the impact resistance of the chip packaging structure.

[0017] In some embodiments, a plurality of second heat sinks are connected in sequence on a plane perpendicular to the first direction to form an annular frame structure. Here, it can be understood that each side surface of the chip packaging structure is configured as a heat dissipation surface, further increasing the heat dissipation area of ​​the chip packaging structure, thereby improving the heat dissipation capacity of the chip packaging structure.

[0018] In some embodiments, the heat sink further comprises a plurality of connection pins arranged at intervals on a plane perpendicular to the first direction, one end of each of the plurality of connection pins is connected to the first heat sink and relatively fixed, and each of the connection pins extends along the first direction. The outer peripheral edge of the carrier is provided with: a plurality of protrusions protruding outward and arranged corresponding to the plurality of connection pins, each of the plurality of protrusions is provided with a snap-fitting hole, and the other end of each of the plurality of connection pins is snap-fitted to the snap-fitting hole on the corresponding protrusion to fix the heat sink to the carrier.

[0019] Here, it can be understood that: by providing multiple connecting pins on the heat sink, multiple protrusions on the outer edge of the carrier, and multiple clamping holes corresponding to the multiple connecting pins on the protrusions, during installation, it is only necessary to clamp each connecting pin of the heat sink with the corresponding clamping hole to complete the installation. This design can ensure that the installation is relatively simple on the one hand, and on the other hand, it can ensure that the connection is relatively stable, thereby improving the service life of the chip packaging structure as a whole.

[0020] In some embodiments, the connecting foot has an elastic clamping section, which is configured as a hollow elastic structure, which is inserted into the clamping hole and elastically abuts against the hole wall of the clamping hole. By providing the elastic clamping section, the situation where the matching structure is not precise enough due to the processing tolerance during the processing can be effectively reduced, and the connection reliability is provided while facilitating assembly.

[0021] In some embodiments, when the heat sink further includes a plurality of second heat sinks, each of which is in a stepped structure and includes a first portion and a second portion, one end of each of the plurality of connecting pins is connected to the other end of the second portion and relatively fixed, so that one end of each connecting pin is connected to the first heat sink through the corresponding second heat sink. The connecting pin is connected to the first heat sink through the second heat sink, so that the required length angle of the connecting pin is reduced, thereby simplifying the structure of the heat sink.

[0022] In some embodiments, on a plane perpendicular to the first direction, the projection of the first heat sink completely covers the projection of at least one chip, thereby further increasing the surface area of ​​the first heat sink and enhancing the heat dissipation effect of the first heat sink.

[0023] In some embodiments, the material of the thermally conductive insulating layer is a curable thermally conductive insulating material.

[0024] In some embodiments, the heat sink is connected to the thermally conductive insulating layer by curing. During processing, the heat sink only needs to be placed on the thermally conductive insulating layer, and the heat sink can be fixed by curing the thermally conductive insulating layer. The processing is simple, the required working hours are short, and the cost is low.

[0025] In some embodiments, the thermally conductive insulating layer covers the entire top surface of at least one chip, ensuring that the top surface of the chip can be in contact with the thermally conductive insulating layer as a whole, so that it can dissipate heat evenly as a whole, avoiding the situation where part of the chip has no path to dissipate heat because it is not in contact with the thermally conductive insulating layer.

[0026] In some embodiments, the thermally conductive insulating layer also covers at least one side surface of at least one chip. By increasing the contact area between the chip and the thermally conductive insulating layer, the efficiency of heat exchange between the chip and the thermally conductive insulating layer is further improved.

[0027] In some embodiments, the thermally conductive insulating layer also covers all side surfaces of at least one chip, thereby maximizing the contact area between the chip and the thermally conductive insulating layer.

[0028] In some embodiments, at least one chip is a plurality of chips spaced apart on a plane perpendicular to the first direction, and the thermally conductive insulating layer is also filled in the gap between any two adjacent chips in the plurality of chips, and is in contact with two opposite sides of any two adjacent chips. Thus, in a multi-chip scenario, a large core (i.e., a large chip) with a larger heat output can transfer part of the heat to a small core (i.e., a small chip) with a smaller heat output. On the one hand, the temperatures of the multiple chips tend to be consistent, avoiding chip damage caused by excessive temperature differences. On the other hand, the temperature of the large core can also be lowered, and local overheating will not occur due to the inability to transfer heat.

[0029] In some embodiments, the top surface of at least one chip has at least one first electrical connector, and the chip packaging structure also includes at least one second electrical connector corresponding to the at least one first electrical connector, the at least one second electrical connector is located on the lower surface of the plastic package and / or the thermally conductive insulating layer, and the at least one second electrical connector is exposed relative to the outer surface of the plastic package, and each of the at least one first electrical connector is electrically connected to the corresponding second electrical connector through a lead. In this way, the chip is electrically connected to the second electrical connector, and the second electrical connector is used as an external interface to facilitate the electrical connection of the chip packaging structure with other parts of the electronic device. The usability and versatility of the chip packaging structure as a module are enhanced.

[0030] In some embodiments, the heat sink is an integrated structure, and the heat sink is made of metal. At least a portion of the carrier is configured as a heat-conducting structure, and the surface of the heat-conducting structure facing away from at least one chip is exposed relative to the outer surface of the plastic package. By configuring the heat sink as an integrated structure, the number of parts can be simplified, the processing steps can be reduced, and the cost can be reduced. By configuring the heat sink as a metal material, it can be easy to process and the heat dissipation effect is better. Configuring at least a portion of the carrier as a heat-conducting structure can be understood here as at least a portion of the surface of the carrier away from the chip is also used as a heat dissipation surface, so that the heat generated by the chip can be dissipated through the carrier, thereby maximizing the heat dissipation capacity of the chip packaging structure.

[0031] The present application also provides an electronic device, including the chip packaging structure in any of the above embodiments, so that the electronic device can run more stably and have better performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1a A schematic top view of a chip packaging structure;

[0033] Figure 1b for Figure 1a Schematic cross-sectional view along the AA direction;

[0034] Figure 1c for Figure 1a A schematic top view after removing the packaging shell;

[0035] Figure 1d A bottom view schematic diagram of a chip packaging structure;

[0036] Figure 2 It is a structural schematic diagram of another chip packaging structure;

[0037] Figure 3 A schematic top view of a first implementation of a chip packaging structure according to an embodiment of the present application;

[0038] Figure 4a for Figure 3 Schematic cross-sectional view in the middle BB direction;

[0039] Figure 4b for Figure 4a Enlarged view of part C;

[0040] Figure 4c for Figure 4a Enlarged view of section H;

[0041] Figure 5 for Figure 3 A schematic top view after removing the packaging shell and the thermally conductive insulating layer;

[0042] Figure 6A bottom view schematically showing a first implementation mode of a chip packaging structure according to an embodiment of the present application;

[0043] Figure 7 This is a schematic diagram of the processing flow of the chip packaging structure according to an embodiment of the present application;

[0044] Figure 8 This is a structural schematic diagram of a second implementation of the chip packaging structure of an embodiment of the present application;

[0045] Fig. 9 A schematic top view of a third implementation of a chip packaging structure according to an embodiment of the present application;

[0046] Fig.10a for Fig. 9 Cross-sectional view in the middle DD direction;

[0047] Fig.10b for Fig. 9 Cross-sectional view in the EE direction;

[0048] Fig.11 for Fig. 9 A schematic top view after removing the packaging shell and the thermally conductive insulating layer;

[0049] Fig.12 A bottom view schematically showing a third implementation mode of the chip packaging structure according to an embodiment of the present application;

[0050] Fig.13a This is a schematic diagram of the structure of the chip packaging structure before and after the connection pins are deformed according to an embodiment of the present application;

[0051] Fig.13b This is a schematic diagram of the assembly of the connection pins of the chip packaging structure according to an embodiment of the present application;

[0052] Fig.14 A schematic diagram of the processing flow of the third implementation mode of the chip packaging structure of the embodiment of the present application;

[0053] Fig.15 A schematic top view of a fourth implementation of a chip packaging structure according to an embodiment of the present application;

[0054] Fig.16a for Fig.15 Schematic cross-sectional view in the FF direction;

[0055] Fig.16b for Fig.15 Schematic cross-sectional view in the GG direction;

[0056] Fig.17 for Fig.15 A schematic top view after removing the packaging shell and the thermally conductive insulating layer;

[0057] Fig.18A bottom view schematically showing a fourth implementation mode of the chip packaging structure according to an embodiment of the present application;

[0058] Fig.19 It is a side view schematic diagram of a fourth implementation of the chip packaging structure of an embodiment of the present application.

[0059] Description of reference numerals:

[0060] Existing technology:

[0061] 100', chip packaging structure;

[0062] 1', chip; 11', large core; 12', small core;

[0063] 2', carrier board; 3', plastic casing.

[0064] This application:

[0065] 100. Chip packaging structure;

[0066] 1. Chip; 101. Top surface; 102. Bottom surface; 103. Side surface; 11. Large core; 12. Small core;

[0067] 2. carrier board; 21. protrusion; 211. snap-fit ​​hole; 22. adhesive layer;

[0068] 3. Encapsulation shell; 31. Heat sink; 311. First heat sink; 312. Second heat sink; 312A. First part; 312B. Second part; 313. Connecting pin; 313A. Elastic clamping section; 32. Plastic package;

[0069] 4. Thermally conductive insulation layer;

[0070] 51. first electrical connection member; 52. second electrical connection member; 53. lead wire;

[0071] z, first direction. DETAILED DESCRIPTION

[0072] The following specific embodiments illustrate the implementation of the present application, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Although the description of the present application will be introduced in conjunction with some embodiments, this does not mean that the features of this application are limited to the implementation. On the contrary, the purpose of introducing the application in conjunction with the implementation is to cover other options or modifications that may be extended based on the claims of the present application. In order to provide a deep understanding of the present application, the following description will include many specific details. The present application can also be implemented without using these details. In addition, in order to avoid confusion or blurring the focus of the present application, some specific details will be omitted in the description. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0073] It should be noted that in this specification, similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0074] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "top", "bottom", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0075] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0076] In the description of the present application, it should be understood that "electrical connection" in the present application can be understood as physical contact and electrical conduction between components; it can also be understood as a form in which different components in a circuit structure are connected through physical lines such as printed circuit board (PCB) copper foil or wires that can transmit electrical signals.

[0077] In the description of the present application, it should be noted that the mutual perpendicularity in the present application is not absolute perpendicularity, and the approximate perpendicularity due to processing errors and assembly errors (for example, the angle between the two structural features is 89.9°) is also within the scope of mutual perpendicularity in the present application. The mutual parallelism in the present application is also not absolute parallelism, and the approximate parallelism due to processing errors and assembly errors (for example, the angle between the two structural features is 0.1°) is also within the scope of mutual parallelism in the present application. The axisymmetry in the present application is not absolute axisymmetry, and the approximate axisymmetry due to processing errors and assembly errors (for example, part of the structure is offset by a certain distance or angle relative to the axis of symmetry) is also within the scope of axisymmetry in the present application. This application does not make specific limitations on this.

[0078] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0079] First, some chip packaging structures are described with reference to the accompanying drawings.

[0080] See also Figure 1a-1d , Figure 1a A schematic top view of a chip packaging structure; Figure 1b for Figure 1a Schematic cross-sectional view along the AA direction; Figure 1c for Figure 1a A schematic top view after removing the packaging shell; Figure 1d It is a bottom view schematic diagram of a chip packaging structure.

[0081] like Figure 1a-1d As shown, the chip packaging structure 100' comprises a chip 1', a carrier 2' and a plastic package shell 3'. The bottom surface of the chip 1' is mounted on the carrier 2' by curing a curing material (such as glue), and the plastic package shell 3' formed by curing the plastic package material encapsulates the chip inside to form the chip packaging structure 100'. (It can be understood here that the plastic package shell 3' formed after the plastic package material is cured serves as the entire packaging shell of the chip packaging structure 100'.)

[0082] At this time, the heat generated by the chip 1' is transferred to the plastic housing 3' and heat exchanged with the air through the plastic housing 3', thereby completing the entire heat dissipation process. Since the plastic housing 3' has weak heat conduction and heat dissipation capabilities, the heat dissipation capability of the chip packaging structure 100' is poor.

[0083] like Figure 1b The chip packaging structure shown in the figure takes a certain temperature as an example. According to the thermodynamic formula, we have:

[0084] P=(T j -T x ) / θ

[0085] Where P is the heat dissipation power of the chip packaging structure, P b Specifically refers to the heat dissipation power of the bottom surface of the chip packaging structure, P c Specifically refers to the heat dissipation power of the top surface of the chip packaging structure, P a Specifically refers to the total heat dissipation power of the chip packaging structure, the unit is W. T j is the chip temperature, T x is the ambient temperature (i.e., the temperature outside the chip package structure), the unit of temperature is °C, θ is the thermal resistance coefficient from chip to air under various conditions, θ jb Specifically refers to the thermal resistance coefficient of the chip to the bottom of the chip package structure, θ jc Specifically refers to the thermal resistance coefficient from chip to the top surface of the chip package structure.

[0086] Taking epoxy resin as the common plastic encapsulation material, and the carrier 2' being configured as a heat dissipation structure and made of copper as an example, only the heat dissipation of the top and bottom surfaces of the chip encapsulation structure is considered, and the temperature T j Set to 125℃, ambient temperature T x Set the temperature to 119°C and calculate the heat dissipation power of the chip packaging structure 100'. At this time, the thermal resistance parameter from the chip to the air is:

[0087] θ jb =1.2℃ / W、θ jc =12℃ / W

[0088] It can be calculated that the heat dissipation power P of the bottom surface of the chip packaging structure is b For: P b =(125℃-119℃) / 1.2℃ / W=5W

[0089] Heat dissipation power P of the bottom surface of the chip packaging structure c for:

[0090] P c =(125℃-119℃) / 12℃ / W=0.5W

[0091] At this time, the total heat dissipation power of the chip packaging structure is P a for:

[0092] P a =P b+ P c =5.5W

[0093] According to the above calculation, the maximum heat dissipation power of the chip package structure 100 ′ is 5.5 W. It can be seen that the heat dissipation capacity of the chip package structure 100 ′ is relatively poor.

[0094] In addition, when there are multiple chips, other problems may occur. The following will describe the problems of the multi-chip structure in conjunction with the accompanying drawings.

[0095] See also Figure 2 , Figure 2 A schematic diagram of the structure of another chip packaging structure.

[0096] like Figure 2 As shown, the chip packaging structure may specifically include a plurality of chips. Among them, the plurality of chips are divided into two specifications of chips, a chip with a larger volume and a higher power is called a large core 11' (i.e., a large chip), and another chip with a smaller volume and a lower power is called a small core 12' (i.e., a small chip). When working, the large core 11' usually has a higher temperature due to its large heat generation, while the small core 12' has a smaller heat generation and a lower temperature. At this time, there is no reliable heat transfer path between the large and small cores 12', resulting in a large temperature difference between the two. In this case, first, the internal temperature of the chip packaging structure 100' is uneven, which will affect the overall service life of the chip packaging structure 100' in long-term use; second, the large core 11' lacks a heat dissipation path, and the heat generated by it cannot be dissipated. In use, it is easy to cause the large core 11' to pass quickly and a large amount of heat cannot be dissipated (or it can be simply referred to as the large core 11' heat accumulation), which further leads to the large core 11's unstable operation, short service life, and inability to exert its full performance.

[0097] In summary, the chip packaging structure provided in the prior art has poor heat dissipation performance, which is not conducive to stable operation of the chip.

[0098] Therefore, the present application provides a chip packaging structure with good heat dissipation effect, which is conducive to the stable operation of the chip.

[0099] The present application also provides an electronic device, which uses the chip packaging structure in the present application. The electronic device can run more stably and have better performance. The electronic device in the embodiment of the present application is a device with data processing function, which may include but is not limited to a cellular phone, a smart phone, a laptop computer, a smart watch, a smart wristband, etc., and the present application does not limit it here.

[0100] See also Figure 3-Figure 6 , Figure 3 A schematic top view of a first implementation of a chip packaging structure according to an embodiment of the present application; Figure 4a for Figure 3 Schematic cross-sectional view in the middle BB direction; Figure 4b for Figure 4a Enlarged view of part C; Figure 4c for Figure 4a Enlarged view of section H; Figure 5 for Figure 3 A schematic top view after removing the packaging shell and the thermally conductive insulating layer; Figure 6 This is a bottom view of a first implementation of a chip packaging structure according to an embodiment of the present application. It should be noted that the chip packaging structure can be understood as a structure obtained by packaging a chip.

[0101] like Figure 3-Figure 6 As shown, the chip packaging structure 100 includes at least one chip 1, a carrier board 2, a thermally conductive insulating layer 4 and a packaging shell 3. Those skilled in the art can understand that the at least one chip 1 mentioned here can specifically refer to one chip or a chipset composed of multiple chips, and the present application does not limit this.

[0102] For example, Figure 4a As shown, in one embodiment, at least one chip 1 can be a chip 1, so as to obtain higher single-core performance or simplify the structure to save costs. In another alternative embodiment, at least one chip 1 can be multiple chips of the same size (or can be understood as multiple large core structures or multiple small core structures) so that the electronic device can obtain better multi-threaded performance. In another alternative embodiment, at least one chip can be multiple chips of different sizes (or can be understood as large and small core structures), and this structure will be described in detail below.

[0103] It should be noted that the multiple large core structures mentioned here can be understood as a structure between a single core structure and a large and small core structure, and the principle is consistent with the combination of a single core structure and a large and small core structure. Therefore, for the sake of simplicity, the following will take the single large core structure and the large and small core structure as examples, and will not elaborate on the multiple large core solution.

[0104] Furthermore, in the present application, the type of chip 1 is not limited. For example, in some embodiments, the chip 1 may be a silicon substrate chip, which is prepared by integrating transistors, resistors, capacitors and other microelectronic components on a silicon substrate. This type of chip is widely used.

[0105] The cost is low, which is convenient for large-scale production and processing, and can also save the cost of electronic equipment. In other embodiments, the chip can be a sapphire substrate chip, or a silicon carbide substrate chip or a diamond substrate chip to improve its structural strength or durability. This application is not limited here.

[0106] It should be noted that the chip 1 can be a single bare chip or a stacked bare chip, or a functional module composed of stacked chips. Bare chips usually exist in the form of large wafers or single-frequency chips, and become components of semiconductor components, integrated circuits or more complex circuits after packaging. Stacked bare chips refer to chips formed by stacking multiple bare chips together.

[0107] like Figures 4a to 4c As shown, the chip 1 has a top surface 101 and a bottom surface 102 that are arranged opposite to each other in a first direction z, and a side surface 103 connected between the top surface 101 and the bottom surface 102. The top surface 101 described here can also be called the front side, the active side, which is the side with electric potential that integrates microelectronic components such as transistors, resistors, capacitors, etc. in the chip 1. It can be understood that the chip 1 contains components or circuits that require power to realize their functions, and the components or circuits located inside the chip 1 can be electrically connected to the outside through pins or pads. In one example, the chip 1 has pins or pads welded on the active surface of the chip 1 before leaving the factory. The pins or pads have a conductive function, and the electrical connection between the chip 1 and the external device is realized through the pins or pads. The bottom surface 102 of the chip 1 opposite to the top surface 101 in the first direction z is called the back side. The bottom surface 102 can also be called the back side. The side surfaces 103 are the surfaces between the top surface 101 and the bottom surface 102 , or can be understood as the surfaces of the outer surface of the chip 1 except the top surface 101 and the bottom surface 102 .

[0108] It should be noted that the first direction z mentioned here can be understood as the thickness direction of the chip 1 , and can also be understood as the thickness direction of the chip packaging structure 100 .

[0109] like Figures 4a to 4c As shown, the bottom surface 102 of the chip 1 is mounted on the carrier 2, and the thermally conductive insulating layer 4 and the chip 1 are packaged in the packaging shell 3. Figure 4c As shown, combined with Figure 4a It is understood that in one embodiment, the top surface 101 of the chip has at least one first electrical connector 51, and the chip packaging structure 100 also includes at least one second electrical connector 52 arranged corresponding to the at least one first electrical connector 51, the second electrical connector 52 is located on the lower surface of the plastic package 32 and / or the thermal insulation layer 4, and is exposed outside the chip packaging structure 100, and each first electrical connector 51 is electrically connected to the corresponding second electrical connector 52 through a lead 53.

[0110] Here, it can be understood that the top surface 101 of the chip 1 is provided with a first electrical connector 51, and the second electrical connector 52 is led out on the outer surface of the chip packaging structure 100, and the first electrical connector 51 and the second electrical connector 52 are electrically connected through the lead 53. And the second electrical connector 52 is arranged to be exposed relative to the chip packaging structure 100, so that when the chip 1 needs to be connected to an external electronic device, it is only necessary to electrically connect the external electronic device to the exposed second electrical connector 52 to achieve the electrical connection between the external electronic device and the chip 1. Thereby, it is convenient to electrically connect the chip packaging structure 100 with other electronic devices of the electronic device. Enhance the usability and versatility of the chip packaging structure 100 as a module.

[0111] Exemplarily, the chip packaging structure is connected to other electronic components of the electronic device through a second electrical connector. The other electronic components of the electronic device may include but are not limited to circuit boards (main board or sub-board), speakers and various sensors, etc., and the present application does not impose any restrictions thereon.

[0112] It should be noted that if Figure 4a and Figure 4c As shown, the specific structures of the first electrical connector 51, the second electrical connector 52 and the lead 53 are not limited.

[0113] For example, Figure 4a and Figure 4c As shown, in one embodiment, the first electrical connector 51 may be specifically a pad or a pin (also referred to as a lead). The second electrical connector 52 may be a lead or a pad, which is used for an external interface terminal. The lead 53 may be a metal wire, specifically a gold wire (Au), an aluminum wire (Al), or an aluminum silicon wire (Si-Al), or a wire, or an FPC, etc., as long as the first electrical connector 51 and the second electrical connector 52 can be electrically connected, and the present application does not limit this. The pad mentioned above may be a metal pad, such as an aluminum pad, etc.

[0114] Those skilled in the art will appreciate that the specific number of the first electrical connector 51 , the second electrical connector 52 and the lead 53 is also not limited and may be one or more, and those skilled in the art may flexibly adjust according to design requirements.

[0115] The above is a structural description of the chip included in the embodiment of the present application. The carrier board will be described below in conjunction with the accompanying drawings.

[0116] like Figure 3-Figure 6As shown, the main function of the carrier board 2 described in the embodiment of the present application is to serve as a carrier of the chip 1 and as a basic structure of the chip packaging structure 100 to facilitate processing, such as installing the chip 1 and the packaging shell 3. The carrier board 2 may also have other functions. For example, in one embodiment, the chip 1 may also be grounded through the carrier board 2. This application does not limit this.

[0117] It will be appreciated by those skilled in the art that the specific material of the carrier 2 described herein is not limited. In one embodiment, the material of the carrier 2 may be a metal with good thermal conductivity to facilitate large-scale production and ensure low cost. In another alternative embodiment, the carrier may also be made of a more complex material such as a copper-nickel-tin alloy to further improve the strength and thermal conductivity of the carrier. This application does not make any limitation here.

[0118] The above is an explanation of the function and material of the carrier board. In order to maximize the use of the surface of the chip packaging structure as a heat dissipation surface, at least a portion of the carrier board 2 can be configured as a heat conducting structure.

[0119] like Figure 6 As shown, combined with Figure 4a It is understood that, in one embodiment, at least a portion (partial or entire) of the carrier 2 is configured as a heat-conducting structure (e.g., a metal sheet or a metal plate), and the surface of the heat-conducting structure facing away from the chip 1 is exposed relative to the outer surface of the plastic package 32. It can be understood here that at least a portion of the surface of the carrier 2 away from the chip 1 is also used as a heat dissipation surface, so that the heat generated by the chip 1 can be dissipated through the carrier 2, thereby maximizing the heat dissipation capacity of the chip packaging structure 100.

[0120] It should be noted that the specific connection method between the chip 1 and the carrier board 2 is also not limited.

[0121] like Figure 4b As shown, combined with Figure 4a It is understood that in one embodiment, the chip 1 can be bonded and fixed to the carrier 2 by the bonding layer 22. This not only ensures the stability of the fixation of the chip 1 and the carrier 2, but also ensures that the processing difficulty is low. In another alternative embodiment, the chip 1 and the carrier 2 can also be fixed by curing material, which is not limited in this application.

[0122] It should be noted that the specific structure of the adhesive layer described here is not limited.

[0123] In one embodiment, the adhesive layer 22 can be a conductive and thermally conductive material, such as graphene glue, etc., to cooperate with the above-mentioned setting of the carrier 2 as a thermally conductive structure, so that the chip 1 can also dissipate heat through the thermally conductive structure of the carrier 2 to obtain a better heat dissipation effect, and the chip 1 can be grounded through the carrier 2. In another alternative embodiment, the adhesive layer 22 can also be formed by coating glue and curing it, or by using double-sided tape, etc., which is not limited in this application.

[0124] The above is an introduction to the basic components of the chip packaging structure 100 according to the embodiment of the present application. The following will introduce the specific scheme of the present application.

[0125] like Figure 3-Figure 6 As shown, the package shell 3 includes a heat sink 31 and a plastic package 32, and the heat sink 31 is connected to the plastic package 32 and fixed relative to the plastic package 32. In the first direction z, the carrier 2, the chip 1, the thermal insulation layer 4 and the heat sink 31 are stacked in sequence, and at least a portion of the top surface 101 of the chip 1, the thermal insulation layer 4 and the heat sink 31 are in contact in sequence. And the surface of the heat sink 31 facing away from the chip 1 in the first direction z is exposed relative to the outer surface of the plastic package 32.

[0126] Here it can be understood that: in the first direction z, the chip 1, the thermal insulation layer 4 and the heat sink 31 are stacked and contacted in sequence, thereby forming a heat dissipation channel inside the chip packaging structure 100: the chip 1 acts as a heating device, and the heat generated by it is transferred to the heat sink 31 through the thermal insulation layer 4, and the heat sink 31 with better heat dissipation capacity exchanges heat with the air, completing the entire heat dissipation process.

[0127] As can be seen from the above, the chip packaging structure provided in the embodiment of the present application greatly improves the heat dissipation performance: compared with the heat dissipation method in which the chip in the full plastic packaging structure generates heat, the heat is transferred to the plastic packaging shell, and the plastic packaging shell exchanges heat with the air, the heat dissipation method in which the chip 1 provided in the embodiment of the present application generates heat, the heat is transferred to the heat sink 31 by the thermal insulation layer 4, and the heat sink 31 exchanges heat with the air is obviously more efficient. This can make the temperature lower when the chip generates the same amount of heat, and the heat that can be tolerated is greater when the chip temperature is the same. It is conducive to adapting chips with stronger performance and higher power consumption, and better releasing their performance.

[0128] At the same time, the packaging shell 3 composed of the heat sink 31 and the plastic package 32 can still completely encapsulate the chip, so that the chip packaging structure 100 can enhance the heat dissipation performance while still ensuring the stability and safety of the chip packaging structure 100.

[0129] In summary, the chip packaging structure provided in the embodiment of the present application has good heat dissipation performance, which is conducive to the stable operation of the chip.

[0130] In order to better illustrate the effects of the embodiments of the present application, quantitative calculations are performed below in combination with exemplary data.

[0131] like Figure 4a The chip packaging structure shown in the figure has the following formula according to thermodynamics:

[0132] P=(T j -T x ) / θ

[0133] Taking the case where the heat sink 31 and the carrier 2 are both made of copper as an example (other calculation conditions are the same as the exemplary calculation of the prior art in the previous text), the heat dissipation power of the chip packaging structure 100 is calculated. At this time, the thermal resistance parameter of the chip packaging structure is:

[0134] θ jb =1.2K / W,θ jc =1.2K / W

[0135] It can be calculated that the heat dissipation power P of the bottom surface of the chip packaging structure is b for:

[0136] P b =(125℃-119℃) / 1.2℃ / W=5W

[0137] Heat dissipation power P of the bottom surface of the chip packaging structure c for:

[0138] P c =(125℃-119℃) / 1.2℃ / W=5W

[0139] At this time, the total heat dissipation power of the chip packaging structure is P a for:

[0140] P a =P b+ P c =10W

[0141] Substituting the calculation into the above, the overall heat dissipation power of the chip package structure 100 is 10W, which shows that the heat dissipation effect of the chip package structure 100 is significantly improved. Compared with the chip package structure in the prior art, if the device junction temperature is kept the same, the heat dissipation of the device can be increased to 10W.

[0142] The above is an explanation of the basic concept and principle of the chip packaging structure proposed in this application. The possible specific structures of each component will be described in detail below in conjunction with the accompanying drawings.

[0143] First, the thermally conductive insulating layer will be described with reference to the accompanying drawings.

[0144] Those skilled in the art will appreciate that the specific coverage area of ​​the thermally conductive insulating layer is not limited.

[0145] like Figure 4a As shown, in one embodiment, the thermally conductive insulating layer 4 covers the entire top surface 101 of the chip 1. It is ensured that the top surface 101 of the chip 1 can be in contact with the thermally conductive insulating layer 4 as a whole, so that it can dissipate heat evenly as a whole, avoiding the situation where part of the chip 1 has no path for heat dissipation because it is not in contact with the thermally conductive insulating layer 4. It can be understood by those skilled in the art that in other alternative embodiments, the thermally conductive insulating layer 4 can also cover a partial area of ​​the top surface 101 of the chip 1, and the present application does not limit this.

[0146] Furthermore, in one embodiment, in order to further improve the thermal conductivity, the thermally conductive insulating layer 4 may also cover at least one side surface 103 of the chip 1. It may be understood here that at least one side surface 103 of the chip 1 is also in contact with the thermally conductive insulating layer 4, and the efficiency of heat exchange between the chip 1 and the thermally conductive insulating layer 4 is further improved by increasing the contact area between the chip 1 and the thermally conductive insulating layer 4.

[0147] In one embodiment, in order to maximize the heat conduction efficiency, the thermally conductive insulating layer 4 may also cover all side surfaces 103 of the chip 1. It may be understood here that all side surfaces 103 of the chip 1 are in contact with the thermally conductive insulating layer 4, thereby maximizing the contact area between the chip 1 and the thermally conductive insulating layer 4 and improving the efficiency of heat exchange between the chip 1 and the thermally conductive insulating layer 4.

[0148] It should be noted that the thermally conductive insulating layer 4 may only cover part of the side surface 103 of the chip 1 , or may not cover the side surface 103 of the chip 1 , and this application does not impose any limitation on this.

[0149] The above embodiments all treat the chip 1 as a whole, and enhance the thermal conductivity of the chip 1 by increasing the contact area between the chip 1 and the thermally conductive insulating layer 4. When there are multiple chips 1, the temperature between the chips 1 can also be balanced by filling the gaps between the chips 1 with the thermally conductive insulating layer 4.

[0150] It should be noted that the specific material of the thermally conductive insulating layer 4 is also not limited.

[0151] like Figure 4a As shown, in one embodiment, the material of the thermally conductive insulating layer 4 is a curable thermally conductive insulating material, such as a curable thermally conductive insulating silicone or a curable thermally conductive insulating gel. In another alternative embodiment, the material of the thermally conductive insulating layer 4 is a non-curable thermally conductive insulating material, such as thermally conductive silicone grease and thermally conductive oil. To obtain a thermally conductive insulating layer with better fluidity, so that it can contact the chip surface more fully, thereby improving the efficiency of heat exchange between the thermally conductive insulating layer 4 and the chip 1. This application is not limited here.

[0152] The above is a description of the specific material of the thermally conductive insulating layer 4 . It should be noted that the specific material of the plastic package 32 is also not limited.

[0153] like Figure 4a As shown, in one embodiment, the material of the plastic package 32 can be epoxy resin (Epoxy Resin), so as to obtain a plastic package with high mechanical strength, excellent heat resistance and chemical stability, and the cost of epoxy resin is low, which is conducive to reducing the cost of the chip packaging structure. In another alternative embodiment, the material of the plastic package 32 can also be polyester resin (Polyester Resin), crystal glue (Silicone) and organic silicone (Organic Silicone) to improve the service life and electrical insulation of the plastic package. This application is not limited here.

[0154] The above is a description of the specific structure of the plastic package 32 . The specific structure and material of the heat sink 31 will be described below with reference to the accompanying drawings.

[0155] like Figure 3 and Figure 4a As shown, those skilled in the art can understand that the specific material of the heat sink 31 is not limited.

[0156] For example, the heat sink 31 can be made of a metal material with good heat dissipation performance (such as copper, aluminum, and silver). On the one hand, metal materials usually have good heat dissipation performance and can exchange heat with air at a high efficiency. On the other hand, metal materials are usually easy to process and form, which is convenient for large-scale production.

[0157] In another alternative embodiment, the heat sink 31 may also be a non-metallic material with good heat dissipation performance (such as thermally conductive ceramics and polymers, etc.) to improve the overall insulation performance of the packaging shell, making its properties more stable and its service life longer.

[0158] like Figure 3 and Figure 4a As shown, in one embodiment, the heat sink 31 includes a first heat sink 311, and in the first direction z, at least a portion of the top surface 101 of the chip 1, the thermally conductive insulating layer 4 and the heat sink 31 are in contact in sequence, and the surface of the first heat sink 311 facing away from the chip 1 in the first direction z is exposed relative to the outer surface of the plastic package 32. The so-called exposure relative to the outer surface of the plastic package 32 can be understood as the first heat sink 311 constituting a portion of the outer surface of the chip packaging structure 100, so that it can directly exchange heat with the air.

[0159] By configuring the heat sink 31 to include a first heat sink 311 , on the one hand, the overall processing difficulty of the chip packaging structure 100 is reduced; on the other hand, the cost of the heat sink 31 is relatively low, which is beneficial to the cost control of the entire chip packaging structure 100 .

[0160] Further, such as Figure 4a As shown, in one embodiment, on a plane perpendicular to the first direction z, the projection of the first heat sink 311 completely covers the projection of the chip 1. This further increases the surface area of ​​the first heat sink 311 and enhances the heat dissipation effect of the first heat sink 311.

[0161] It should be noted that the fixing method of the heat sink 31 is not limited.

[0162] like Figure 4a As shown, in one embodiment, when the thermally conductive insulating layer 4 is formed of the aforementioned curable thermally conductive insulating material, the heat sink 31 can be cured and connected through the curable thermally conductive insulating layer 4, so that the chip packaging structure is easy to process and low in cost.

[0163] To better illustrate the low processing difficulty of the chip packaging structure of the embodiment of the present application, please refer to Figure 7 , Figure 7 This is a schematic diagram of the processing flow of the chip packaging structure according to an embodiment of the present application.

[0164] like Figure 7 As shown, combined with Figure 4aIt is understood that when the thermally conductive insulating layer 4 is formed by the aforementioned curable thermally conductive insulating material, the heat sink 31 can be connected by curing the curable thermally conductive insulating layer 4. At this time, the chip packaging structure packaging process in the embodiment of the present application is: first, the large wafer is thinned and its thickness is reduced by grinding. Then the large wafer is cut to obtain a single chip 1, and then the chip 1 is assembled with a carrier preform (the carrier 2 and the second electrical connector 52 are obtained after the frame of the outer periphery of the carrier preform is cut), and the chip 1 is electrically connected to the pins on the carrier preform (i.e., the second electrical connector 52). Then fill or coat the thermally conductive insulating material above the chip 1, and place the first heat sink 311 on the thermally conductive insulating material. After the thermally conductive insulating material is cured, a thermally conductive insulating layer 4 is formed, and the thermally conductive insulating layer 4 is fixedly connected to the first heat sink 311 by curing the thermally conductive insulating material. Then, the gaps between the parts are filled with plastic packaging materials, and the thermally conductive insulating layer 4 and the chip 1 are packaged to form a plastic packaging part 32. Finally, after electroplating, printing and other processes, the carrier preform is cut to form the final carrier 2. Compared with the chip packaging structure processing flow in the prior art, only the steps of filling or coating the thermally conductive insulating material and placing the first heat sink 311 are added. During processing, it is only necessary to place the heat sink 31 on the thermally conductive insulating material, and the heat sink 31 can be fixed by curing the thermally conductive insulating material. There is no need to add the previous and next processes, which is easy to process and will not increase the cost of the chip packaging structure too much.

[0165] In another alternative embodiment, in order to make the connection more stable, the heat sink 31 may be fixed in other ways, such as by providing connecting pins on the heat sink, etc. This solution will be described in detail below.

[0166] The above is a specific description of the basic embodiment of the present application. Several other alternative implementation methods of the present application will be described below.

[0167] See also Figure 8 , Figure 8 This is a structural schematic diagram of a second implementation of the chip packaging structure of an embodiment of the present application.

[0168] like Figure 8 As shown, as mentioned above, in another alternative embodiment, at least one chip can also be a plurality of chips 1 of different sizes. Because at least one chip includes a larger chip (also called a large core 11, usually with higher power consumption and stronger performance) and several smaller chips (also called small cores 12, usually with lower power consumption and weaker performance), it is also called a large and small core structure. A large core 11 and several small cores 12 are arranged at intervals on a plane perpendicular to the first direction z. A large core 11 and several small cores 12 can be electrically connected to each other, for example, the first electrical connectors on the top surfaces of each chip are electrically connected through leads.

[0169] Such a structure enables electronic devices to be operated by different numbers or types of chips under different working conditions. For example, high-load tasks are processed by a single large core 11, thereby providing the best performance and lowest latency. Low-load tasks are processed by multiple small cores 12, thereby improving energy consumption performance. In this way, energy consumption and performance are combined, so that the chip can work with appropriate power consumption in different scenarios and provide sufficient computing power when needed, thereby combining the performance and battery life of electronic devices, greatly improving the user experience.

[0170] like Figure 8 As shown, at least one chip 1 is a large core 11 and a plurality of small cores 12 arranged at intervals on a plane perpendicular to the first direction z, and the thermally conductive insulating layer 4 is also filled in the gap between any two adjacent chips 1 among the plurality of chips 1, and is in contact with two opposite side surfaces 103 of any two adjacent chips 1. It can be understood here that by filling the thermally conductive insulating layer 4 into the gap between the chips 1, heat exchange can also occur between the chips 1 with higher efficiency.

[0171] This design allows the large core 11 with a larger heat output to transfer part of the heat to the small core 12 with a smaller heat output in a multi-chip scenario. On the one hand, this allows the temperatures of multiple chips to be consistent, reduces the temperature difference between the chips, and avoids chip damage caused by excessive temperature differences. On the other hand, it can also lower the temperature of the large core 11, and prevent local overheating due to the inability to dissipate heat.

[0172] The above is an example of an embodiment of a chip packaging structure in a multi-core scenario. As mentioned above, in another alternative implementation, the heat sink can also be fixed by connecting pins.

[0173] See also Figure 9-12 , Fig. 9 A schematic top view of a third implementation of a chip packaging structure according to an embodiment of the present application; Fig.10a for Fig. 9 Cross-sectional view in the middle DD direction; Fig.10b for Fig. 9 Cross-sectional view in the EE direction; Fig.11 for Fig. 9 A schematic top view after removing the packaging shell and the thermally conductive insulating layer; Fig.12 It is a bottom view schematic diagram of a third implementation mode of the chip packaging structure of an embodiment of the present application.

[0174] like Figure 9-12As shown, the heat sink 31 may also include a plurality of connection pins 313 arranged at intervals on a plane perpendicular to the first direction z, one end of each connection pin 313 is connected to and relatively fixed with the first heat sink 311, and each connection pin 313 extends along the first direction z. The outer peripheral edge of the carrier 2 is provided with: a plurality of protrusions 21 protruding outward and arranged corresponding to the plurality of connection pins 313, each of the plurality of protrusions 21 is provided with a snap-fitting hole 211, and the other end of each of the plurality of connection pins 313 is snap-fitted to the snap-fitting hole 211 on the corresponding protrusion 21, so as to fix the heat sink 31 with the carrier 2.

[0175] Here, it can be understood that: a plurality of connecting pins 313 are provided on the heat sink 31, a plurality of protrusions 21 are provided on the outer edge of the carrier 2, and a plurality of snap-in holes 211 are provided on the protrusions 21, which correspond to the plurality of connecting pins 313 one by one. During installation, it is only necessary to snap-in each connecting pin 313 of the heat sink 31 with the corresponding snap-in hole 211 to complete the installation. On the one hand, such a design can ensure that the installation is relatively simple, and on the other hand, it can ensure that the connection is relatively stable, thereby improving the service life of the chip packaging structure as a whole. At this time, the heat sink 31 is mainly fixed by the cooperation between the connecting pin 313 and the snap-in hole 211 on the protrusion 21, so there is no requirement on whether the thermally conductive insulating layer is a curable material, and the scope of application is wider.

[0176] It should be noted that the specific structure of the protrusion 21 is not limited. In one embodiment, the protrusion 21 and the carrier 2 are an integral structure. In another alternative embodiment, the protrusion 21 and the carrier 2 are a split structure fixed to each other, which is not limited in this application.

[0177] It should be noted that the specific structure of the connecting pin 313 is not limited.

[0178] Furthermore, in order to ensure the fixing effect after installation, improvements can be made to the connecting pins.

[0179] See also Figure 13a-13b , Fig.13a This is a schematic diagram of the structure of the chip packaging structure before and after the connection pins are deformed according to an embodiment of the present application; Fig.13b It is a schematic diagram of the assembly of the connection pins of the chip packaging structure according to the embodiment of the present application.

[0180] like Figure 13a-13bAs shown, in one embodiment, the connecting foot 313 also has an elastic clamping section 313A. The elastic clamping section 313A is set as a hollow elastic structure (or can be understood as a fisheye structure), the elastic structure is penetrated through the clamping hole 211, and elastically abuts against the hole wall of the clamping hole 211. Or it can be understood that: the width of the elastic clamping section 313A when not under force is greater than the width of the clamping hole 211. During installation, force is applied in the width direction of the elastic clamping section 313A and it is compressed in the width direction and then placed into the clamping hole 211. After the elastic clamping section 313A enters the clamping hole 211, it can elastically abut against the clamping hole 211. Such a design can effectively reduce the situation where the matching structure is not precise enough due to processing tolerances during the processing process, and provides connection reliability while facilitating assembly.

[0181] To illustrate that the method of fixing the heat sink by connecting the pin 313 is also simple to process, refer to Fig.14 , Fig.14 This is a schematic diagram of the processing flow of the third implementation mode of the chip packaging structure of the embodiment of the present application.

[0182] like Fig.14 As shown, combined with Figure 9-13b It is understood that the heat sink 31 is fixed to the carrier 2 through the connecting pin 313. Compared with the process in the prior art, only the steps of filling the heat conductive insulating material, placing the first heat sink 311 and inserting the connecting pin 313 into the clamping hole 211 are added (the other steps have been described above and will not be repeated here). During processing, the heat sink 31 only needs to be inserted into the clamping hole to complete the fixing of the heat sink 31. Similarly, the processing difficulty of the chip packaging structure is not increased too much.

[0183] The above is an explanation of the first heat sink structure and possible fixing methods thereof. In order to further increase the heat dissipation area of ​​the packaging shell of the chip packaging structure, the heat sink may further include a plurality of second heat sinks.

[0184] See also Figure 15-19 , Fig.15 A schematic top view of a fourth implementation of a chip packaging structure according to an embodiment of the present application; Fig.16a for Fig.15 Schematic cross-sectional view in the FF direction; Fig.16b for Fig.15 Schematic cross-sectional view in the GG direction; Fig.17 for Fig.15 A schematic top view after removing the packaging shell and the thermally conductive insulating layer; Fig.18 A bottom view schematically showing a fourth implementation mode of the chip packaging structure according to an embodiment of the present application; Fig.19 It is a side view schematic diagram of a fourth implementation of the chip packaging structure of an embodiment of the present application.

[0185] like Figure 15-19 As shown, in one embodiment, the heat sink 31 further includes a plurality of second heat sinks 312, each of the plurality of second heat sinks 312 is in a stepped structure and includes a first portion 312A and a second portion 312B, one end of the first portion 312A is connected to the outer edge of the first heat sink 311, and the other end is connected to one end of the second portion 312B. The first portion 312A is encapsulated in the plastic package 32, and the surface of the second portion 312B away from the heat-conducting insulating layer 4 constitutes at least part of the outer side surface of the packaging shell 3. On the one hand, by providing the second heat sink 312, part of each side surface of the chip packaging structure 100 is also used as a heat dissipation surface for heat dissipation, further improving the heat dissipation performance of the heat sink 31. On the other hand, by providing the second heat sink 312 as a stepped structure, the outer peripheral edge of the top of the chip packaging structure 100 is still filled with the plastic package 32, thereby ensuring the impact resistance of the chip packaging structure 100.

[0186] like Figure 15-19 As shown, further, in one embodiment, a plurality of second heat sinks 312 are sequentially connected on a plane perpendicular to the first direction z to form an annular frame structure. It can be understood here that: a portion of each side surface of the chip packaging structure 100 is set as a heat dissipation surface, which further increases the heat dissipation area of ​​the chip packaging structure 100, thereby improving the heat dissipation capacity of the chip packaging structure 100.

[0187] It should be noted that the specific fixing method of the heat sink including the second heat sink is not limited. In one embodiment, the above description can be adopted to connect by curing the curable thermal insulation layer. In another embodiment, the heat sink can be fixed to the carrier board by connecting pins.

[0188] Take the method of setting the connection pin as an example. Figure 15-19 As shown, when the heat sink 31 also includes a plurality of second heat sinks 312, each second heat sink 312 is in a stepped structure and includes a first portion 312A and a second portion 312B, one end of each of the plurality of connecting pins 313 is connected to the other end of the second portion 312B and relatively fixed, so that one end of each connecting pin 313 is connected to the first heat sink 311 through the corresponding second heat sink 312, thereby simplifying the structure of the heat sink 31.

[0189] It should be noted that the connection method between the components of the heat sink 31 is also not limited.

[0190] In one embodiment, the heat sink 31 is an integral structure formed in one piece, which is helpful to reduce the number of parts and reduce the difficulty of processing. In another alternative embodiment, the components of the heat sink 31 can also be a split structure fixedly connected to each other. This application does not limit this.

[0191] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A chip packaging structure, characterized in that: The chip packaging structure comprises at least one chip, a carrier, a heat-conducting insulating layer and a packaging shell, wherein the bottom surface of the at least one chip is mounted on the carrier, and the heat-conducting insulating layer and the at least one chip are packaged in the packaging shell; The packaging shell includes a heat sink and a plastic package. In a first direction, the carrier, the at least one chip, the thermally conductive insulating layer and the heat sink are stacked in sequence, and at least a portion of the top surface of the at least one chip, the thermally conductive insulating layer and the heat sink are in contact with each other in sequence, and a surface of the heat sink facing away from the at least one chip in the first direction is exposed relative to an outer surface of the plastic package; wherein the first direction is parallel to a thickness direction of the chip packaging structure, and the top surface and the bottom surface of the at least one chip are facing each other in the first direction.

2. The chip packaging structure according to claim 1, characterized in that: The heat sink includes a first heat sink. In the first direction, at least a portion of the top surface of the at least one chip, the thermally conductive insulating layer and the heat sink are in contact in sequence. The surface of the first heat sink facing away from the at least one chip in the first direction is exposed relative to the outer surface of the plastic package.

3. The chip packaging structure according to claim 2, characterized in that: The heat sink also includes a plurality of second heat sinks, each of the plurality of second heat sinks is in a stepped structure and includes a first portion and a second portion, one end of the first portion is connected to the outer edge of the first heat sink, and the other end is connected to one end of the second portion; The first portion is encapsulated in the plastic package, and the surface of the second portion away from the heat-conducting insulating layer constitutes at least a portion of the outer side surface of the packaging shell.

4. The chip packaging structure according to claim 3, characterized in that: The plurality of second heat sinks are connected in sequence on a plane perpendicular to the first direction to form an annular frame structure.

5. The chip packaging structure according to any one of claims 2 to 4, characterized in that: The heat sink also includes a plurality of connection pins arranged at intervals on a plane perpendicular to the first direction, one end of each of the plurality of connection pins is connected to the first heat sink and relatively fixed, and each of the connection pins extends along the first direction; The outer peripheral edge of the carrier is provided with: a plurality of protrusions protruding outward and arranged corresponding to the plurality of connecting pins, each of the plurality of protrusions is provided with a snap-in hole, and the other end of each of the plurality of connecting pins is snap-fitted into the snap-in hole on the corresponding protrusion to fix the heat sink to the carrier.

6. The chip packaging structure according to claim 5, characterized in that: The connecting foot has an elastic clamping section, and the elastic clamping section is configured as a hollow elastic structure. The elastic structure is penetrated through the clamping hole and elastically abuts against the hole wall of the clamping hole.

7. The chip packaging structure according to claim 6, characterized in that: When the heat sink also includes multiple second heat sinks, each of the second heat sinks has a stepped structure and includes a first part and a second part, one end of each of the multiple connecting pins is connected to the other end of the second part and is relatively fixed, so that one end of each of the connecting pins is connected to the first heat sink through the corresponding second heat sink.

8. The chip packaging structure according to any one of claims 2 to 4, characterized in that: On a plane perpendicular to the first direction, a projection of the first heat sink completely covers a projection of the at least one chip.

9. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The material of the thermally conductive insulating layer is a curable thermally conductive insulating material.

10. The chip packaging structure according to claim 9, characterized in that: The heat sink is connected to the thermally conductive insulating layer by curing.

11. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The thermally conductive insulating layer covers the entire top surface of the at least one chip.

12. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The thermally conductive insulating layer also covers at least one side surface of the at least one chip.

13. The chip packaging structure according to claim 12, characterized in that: The thermally conductive insulating layer also covers all side surfaces of the at least one chip.

14. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The at least one chip is a plurality of chips spaced apart on a plane perpendicular to the first direction, and the thermally conductive insulating layer is also filled in a gap between any two adjacent chips among the plurality of chips and contacts two opposite side surfaces of the any two adjacent chips.

15. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The top surface of the at least one chip has at least one first electrical connector, and the chip packaging structure also includes at least one second electrical connector arranged corresponding to the at least one first electrical connector, the at least one second electrical connector is located on the lower surface of the plastic package and / or the thermally conductive insulation layer, and the at least one second electrical connector is exposed relative to the outer surface of the plastic package, and each of the at least one first electrical connector is electrically connected to the corresponding second electrical connector through a lead.

16. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The heat sink is an integrated structure, and the material of the heat sink is metal; At least a portion of the carrier is configured as a heat-conducting structure, and a surface of the heat-conducting structure facing away from the at least one chip is exposed relative to an outer surface of the plastic package.

17. An electronic device, characterized in that: Comprising the chip packaging structure as described in any one of claims 1-16.

Images