Chip function detection circuit and chip function detection device

Abstract

The utility model relates to the technical field of electronics, in particular to a chip function detection circuit and a chip function detection device. The function detection circuit comprises a control chip, a voltage decoy chip, a power supply chip and a power detection chip. The voltage decoy chip is used for sending a charging request signal to the fast charging protocol chip to be tested; the to-be-tested fast charging protocol chip is used for sending a charging control signal to the power supply chip according to the charging request signal; the power supply chip is used for outputting a corresponding charging power signal according to the charging control signal; the power detection chip is used for receiving the charging power signal, detecting an actual charging power value of the charging power signal and sending the detected actual charging power value to the control chip; and the control chip is used for outputting a function detection result. According to the chip function detection circuit provided by the invention, the function of the burnt fast-charging protocol chip to be detected can be automatically detected, and the detection efficiency and the detection precision are improved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a chip function detection circuit and a chip function detection device. Background Art

[0002] In the related art, after the fast charging protocol chip is burned, the accuracy of the burning result is usually verified. The common verification method is to use the check value and / or hash value to ensure the consistency of the data by comparing the check value and / or hash value in the source program and the target chip. If the verification is consistent, the burned fast charging protocol chip is attached to the PCB (Printed Circuit Board) motherboard of the product. However, it is found in actual production that the verification of chip burning results in the related art cannot completely screen out the fast charging protocol chips with abnormal burning, resulting in some fast charging protocol chips with abnormal burning being attached to the motherboard, which requires a lot of cost to check and rework, affecting production efficiency. Utility Model Content

[0003] The present application provides a chip function detection circuit and a chip function detection device to solve the technical problem of inaccurate detection of chip burning results in the related art.

[0004] In a first aspect, the present application provides a chip function detection circuit for performing function detection on a fast charging protocol chip to be tested after being burned, wherein the function detection circuit comprises: a control chip, a voltage deception chip, a power supply chip and a power detection chip;

[0005] The communication pin of the control chip is connected to the communication pin of the voltage deception chip; the fast charging protocol communication pin of the voltage deception chip is used to connect to the fast charging protocol communication pin of the fast charging protocol chip to be tested;

[0006] The voltage control pin of the power chip is used to connect to the voltage control pin of the fast charging protocol chip to be tested; the charging signal pin of the power chip is connected to the charging signal pin of the power detection chip;

[0007] The communication pin of the power detection chip is also connected to the communication pin of the control chip;

[0008] Among them, the control chip is used to send a function detection signal to the voltage deception chip; the voltage deception chip is used to send a charging request signal to the fast charging protocol chip to be tested according to the function detection signal, and the charging request signal includes a target charging power value during charging;

[0009] The fast charging protocol chip to be tested is used to send a charging control signal to the power chip according to the charging request signal; the power chip is used to output a corresponding charging power signal according to the charging control signal;

[0010] The power detection chip is used to receive the charging power signal, detect the actual charging power value of the charging power signal, and send the detected actual charging power value to the control chip;

[0011] The control chip is used to determine whether the actual charging power value matches the target charging power value, and output the function detection result of the fast charging protocol chip to be tested according to the matching result.

[0012] In one possible design, the burning pin of the control chip is used to connect to the burning pin of the fast charging protocol chip to be tested;

[0013] The control chip is also used to transmit the file to be burned to the fast charging protocol chip to be tested through the burning pin.

[0014] In a possible design, it also includes a first power supply circuit and a second power supply circuit;

[0015] The input end of the first power supply circuit is used to connect to a power supply, and the output end of the first power supply circuit is used to connect to a power supply pin of the fast charging protocol chip to be tested;

[0016] The input end of the second power supply circuit is used to connect to a power supply, and the output end of the second power supply circuit is connected to a power supply pin of the power chip;

[0017] The control chip further includes a first power supply control pin and a second power supply control pin, the first power supply control pin is connected to the control end of the first power supply circuit, and the second power supply control pin is connected to the control end of the second power supply circuit;

[0018] The control chip is also used to output corresponding control signals to the first power supply circuit and the second power supply circuit respectively; the control signal is used to control the first power supply circuit and the second power supply circuit to be turned on or off, thereby controlling the fast charging protocol chip to be tested and the power supply chip to be powered on or off.

[0019] In a possible design, the first power supply circuit includes a first transistor, a first resistor, a second resistor, a first capacitor, and a second capacitor;

[0020] The first pole of the first transistor is the input end of the first power supply circuit, and the input end of the first power supply circuit is used to connect to the power supply; the second pole of the first transistor is the output end of the first power supply circuit; the first pole of the first transistor is also grounded through the first capacitor, and the second pole of the first transistor is grounded through the second capacitor; the first end of the first resistor is connected to the first pole of the first transistor, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is the control end of the first power supply circuit; the control pole of the first transistor is connected to the second end of the first resistor;

[0021] The second power supply circuit includes a second transistor, a third resistor, a fourth resistor, a third capacitor and a fourth capacitor;

[0022] The first pole of the second transistor is the input end of the second power supply circuit, and the input end of the second power supply circuit is used to connect to the power supply; the second pole of the second transistor is the output end of the second power supply circuit; the first pole of the second transistor is also grounded through the third capacitor, and the second pole of the second transistor is grounded through the fourth capacitor; the first end of the third resistor is connected to the first pole of the second transistor, the second end of the third resistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor is the control end of the second power supply circuit; the control pole of the second transistor is connected to the second end of the third resistor.

[0023] In a possible design, a voltage conversion circuit is further included, wherein the voltage conversion circuit includes a fifth capacitor, a sixth capacitor and a voltage conversion chip;

[0024] The input end of the voltage conversion chip is the input end of the voltage conversion circuit, and the input end of the voltage conversion circuit is used to connect the power supply; the output end of the voltage conversion chip is the output end of the voltage conversion circuit, and the output end of the voltage conversion circuit is used to connect to one or more of the power supply end of the control chip, the power supply end of the voltage deception chip, the power supply end of the power detection chip, and the input end of the first power supply circuit to output the converted voltage signal;

[0025] The input end of the voltage conversion chip is grounded through the fifth capacitor, and the output end of the voltage conversion chip is grounded through the sixth capacitor.

[0026] In one possible design, it further includes a first pull-up circuit and a second pull-up circuit;

[0027] The first pull-up circuit includes a fifth resistor and a sixth resistor; the control chip includes a first programming pin and a second programming pin, the first end of the fifth resistor is used to connect to the power supply, and the second end of the fifth resistor is connected to the first programming pin; the first end of the sixth resistor is also used to connect to the power supply, and the second end of the sixth resistor is connected to the second programming pin;

[0028] The second pull-up circuit includes a seventh resistor and an eighth resistor; the control chip includes a first communication pin and a second communication pin, the first end of the seventh resistor is used to connect to the power supply, and the second end of the seventh resistor is connected to the first communication pin; the first end of the eighth resistor is also used to connect to the power supply, and the second end of the eighth resistor is connected to the second communication pin.

[0029] In a possible design, a reset circuit is further included, wherein the reset circuit includes a ninth resistor and a seventh capacitor;

[0030] The first end of the ninth resistor is used to connect to the power supply, the second end of the ninth resistor is connected to the first end of the seventh capacitor, and the second end of the seventh capacitor is grounded;

[0031] The control chip comprises a reset pin, and the second end of the ninth resistor is connected to the reset pin; the reset circuit is used for outputting a reset signal to the reset pin.

[0032] In a possible design, it also includes a clock chip, an eighth capacitor and a ninth capacitor;

[0033] The control chip comprises a first clock pin and a second clock pin; the first output pin of the clock chip is connected to the first clock pin of the control chip, and the second output pin of the clock chip is connected to the second clock pin of the control chip;

[0034] The first output pin of the clock chip is also grounded through the eighth capacitor, and the second output pin of the clock chip is also grounded through the ninth capacitor.

[0035] In one possible design, a filtering circuit is also included.

[0036] The input end of the filter circuit is connected to the charging signal pin of the power detection chip, and the output end of the filter circuit is grounded; the filter circuit includes at least one capacitor.

[0037] In a second aspect, the present application also provides a chip function detection device, comprising any of the chip function detection circuits described above.

[0038] In a possible design, the chip function detection device further includes a display, and the display is connected to the control chip;

[0039] The display is used to display the function detection result of the fast charging protocol chip to be tested output by the control chip.

[0040] According to the chip function detection circuit provided in the first aspect above, the function of the fast charging protocol chip to be tested after burning can be automatically detected to determine whether the function of the fast charging protocol chip to be tested after burning is normal, thereby improving the detection efficiency and detection accuracy.

[0041] The beneficial effects provided in the above-mentioned second aspect and various possible designs of the above-mentioned second aspect can refer to the beneficial effects brought about by the above-mentioned first aspect and various possible implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of the overall structure of a chip function detection circuit provided in an embodiment of the present application;

[0043] Figure 2 A schematic diagram of the structure of the fast charging protocol chip to be tested provided in an embodiment of the present application;

[0044] Figure 3 A schematic diagram of the structure of a control chip provided in an embodiment of the present application;

[0045] Figure 4 A schematic diagram of the structure of a voltage deception chip provided in an embodiment of the present application;

[0046] Figure 5 A schematic diagram of the structure of a power chip provided in an embodiment of the present application;

[0047] Figure 6 A schematic diagram of the structure of a power detection chip provided in an embodiment of the present application;

[0048] Figure 7 A schematic diagram of the voltage conversion circuit structure provided in an embodiment of the present application;

[0049] Figure 8 A schematic diagram of the structure of a first power supply circuit provided in an embodiment of the present application;

[0050] Fig. 9 A schematic diagram of the structure of a second power supply circuit provided in an embodiment of the present application;

[0051] Fig.10 A schematic diagram of the first pull-up circuit structure provided in an embodiment of the present application;

[0052] Fig.11 A schematic diagram of the structure of a second pull-up circuit provided in an embodiment of the present application;

[0053] Fig.12 A schematic diagram of the reset circuit structure provided in an embodiment of the present application;

[0054] Fig.13 This is a schematic diagram of the structure of a chip function detection device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0056] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0057] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0058] In the related art, after the fast charging protocol chip is burned, the consistency of the check value and / or hash value in the source program and the target chip is compared to determine whether the burning function is abnormal. If the check value and / or hash value in the source program and the target chip are consistent, it is determined that the fast charging protocol chip is burned normally and enters the next patch process. Then, after the chip is attached to the motherboard, it is powered on to test the actual function of the chip. However, in actual production, it is found that some chips that have passed the consistency test of the check value and / or hash value will still have functional abnormalities after actual power-on. It can be seen that the chip function detection method in the related art is less accurate. At this point, since the chip has been installed on the motherboard, a lot of cost is required for rework, which seriously affects production efficiency and even causes damage to the chip or motherboard during the rework process.

[0059] In order to overcome the deficiencies in the above-mentioned related technologies, the present application provides a chip function detection circuit for performing function detection on the fast charging protocol chip to be tested after burning. The function detection circuit integrates a control chip, a voltage deception chip, a power supply chip and a power detection chip, and simulates the normal working process of the fast charging protocol chip to realize the detection of the function of the fast charging protocol chip, so that the detection result is more accurate.

[0060] The transistor in the present application is a three-terminal transistor, and its three terminals are a control electrode, a first electrode, and a second electrode. The transistor can be a bipolar transistor or a field effect transistor, etc. For example, when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode can be the collector or emitter of the bipolar transistor, and the corresponding second electrode can be the emitter or collector of the bipolar transistor; when the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor, the first electrode can be the drain or source of the field effect transistor, and the corresponding second electrode can be the source or drain of the field effect transistor.

[0061] Figure 1 For the overall structure diagram of the chip function detection circuit provided in the embodiment of the present application, please refer to Figure 1 As shown, the function detection circuit includes: a control chip 20, a voltage deception chip 10, a power chip 30 and a power detection chip 50.

[0062] Among them, the communication pin of the control chip 20 is connected to the communication pin of the voltage deception chip 10; the fast charging protocol communication pin of the voltage deception chip 10 is used to connect to the fast charging protocol communication pin of the fast charging protocol chip 50 to be tested. The voltage control pin of the power chip 30 is connected to the voltage control pin of the fast charging protocol chip 50 to be tested; the charging signal pin of the power chip 30 is connected to the charging signal pin of the power detection chip 40. The communication pin of the power detection chip 40 is also connected to the communication pin of the control chip 20.

[0063] After power-on, first, the control chip 20 is used to send a function detection signal to the voltage deception chip 10; the voltage deception chip 10 is used to simulate an electronic device or a load. After receiving the function detection signal sent by the control chip 20, the voltage deception chip 10 sends a charging request signal to the fast charging protocol chip 50 to be tested. The charging request signal includes the target charging power value during charging. After receiving the charging request signal, the fast charging protocol chip 50 to be tested sends a charging control signal to the power chip 30, and the charging control signal is used to control the power chip 30 to output the above-mentioned target charging power. This process controls the voltage deception chip 10 by the control chip 20 to simulate the charging process of an electronic device in an actual charging scenario.

[0064] Then, after receiving the charging control signal, the power chip 30 outputs a corresponding charging power signal to the power detection chip 40, which may be an actual charging signal; the power detection chip 40 is used to receive the charging power signal, detect the actual charging power value of the charging power signal, and send the detected actual charging power value to the control chip 20. This process simulates the process in which the fast charging protocol chip outputs a corresponding charging signal according to the charging protocol after communication during the actual working process through the power chip 30 and the power detection chip 40.

[0065] Finally, the control chip 20 is used to determine whether the actual charging power value matches the target charging power value, and outputs the function detection result of the fast charging protocol chip 50 to be tested according to the matching result. It can be understood that if the requested target charging power value is the same as or close to the actual charging power value actually output, it can be determined that the function of the fast charging protocol chip 50 to be tested is normal, that is, the functions of charging protocol communication and charging intelligent control can be realized in the fast charging circuit, otherwise it is determined that the function of the fast charging protocol chip 50 to be tested is abnormal.

[0066] For example, the control chip 20 may include a comparator circuit, which compares the target charging power value and the actual charging power value of the actual output by the comparator circuit to see whether they are the same, or if the difference between the two is within a set threshold range, it can be determined that the function of the fast charging protocol chip 50 to be tested is normal.

[0067] In some embodiments, in order to reduce the movement of the fast charging protocol chip 50 to be tested and the electrical connection of the pins, while improving production efficiency, the burning and functional testing of the fast charging protocol chip 50 to be tested can be integrated into an overall circuit.

[0068] Specifically, the burning pin of the control chip 20 can be connected to the burning pin of the fast charging protocol chip 50 to be tested; the control chip 20 is also used to transmit the file to be burned to the fast charging protocol chip 50 to be tested through the burning pin to complete the burning process of the fast charging protocol chip 50 to be tested. After the burning is completed, the control chip 20 sends a function detection signal to the voltage deception chip 10 to start the chip function test process.

[0069] In this way, after the unburned fast charging protocol chip is placed in the predetermined position, and each pin of the chip is electrically connected to the corresponding pin in the detection circuit, the automatic burning and function detection process can be controlled by the control chip 20, without the need to transfer the chip in the middle, thereby improving the chip burning and function testing process.

[0070] It is understandable that in order to achieve the purpose of burning and functional testing of the above-mentioned fast charging protocol chip, the above-mentioned control chip 20, voltage deception chip 10, power chip 30 and power detection chip 40 can use chips of different models and types, as long as the corresponding functions of the above-mentioned chips can be realized. When the chips communicate with each other, the specific pin connection relationship is not limited, as long as the above-mentioned information transmission can be realized.

[0071] In some embodiments, the power detection chip 40 can specifically be a voltage detection chip, which detects the voltage value output by the power chip 30 and the control chip 20 to determine whether the voltage value in the target charging power is consistent with the actually detected voltage value, and outputs the functional detection result of the fast charging protocol chip 50 to be tested based on the determination result.

[0072] The structure, pin connection relationship and function of the detection circuit of the present application are further described below in combination with several specific chip structures.

[0073] Figure 2 This is a schematic diagram of the structure of the fast charging protocol chip to be tested provided in the embodiment of the present application. Figure 3 A schematic diagram of the structure of the control chip provided in the embodiment of the present application, Figure 4 This is a schematic diagram of the structure of the voltage deception chip provided in the embodiment of the present application. Figure 5 A schematic diagram of the structure of a power chip provided in an embodiment of the present application, Figure 6 This is a schematic diagram of the structure of the power detection chip provided in the embodiment of the present application. Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 As shown, in order for those skilled in the art to more clearly understand the connection between the various chips, the pins with the same name marked in the figure in this application indicate that the two are connected to each other.

[0074] In some embodiments, please refer to Figure 4 As shown, the fast charging protocol communication pins of the voltage spoofing chip 10 include four pins, namely SLT_CC1, SLT_CC2, SLT_DP1 and SLT_DM1. Among them, SLT_CC1 and SLT_CC2 are Type-C communication pins, and SLT_DP1 and SLT_DM1 are communication pins adapted to the universal serial bus, such as the pins adapted to USB (Universal Serial Bus) communication. Please refer to Figure 2 As shown, the fast charging protocol chip 50 to be tested also has four fast charging protocol communication pins of the same type. The SLT_CC1 pin, SLT_CC2 pin, SLT_DP1 pin and SLT_DM1 pin on the voltage deceiving chip 10 are respectively electrically connected to the four pins of the same type on the fast charging protocol chip 50 to be tested, thereby realizing the communication connection between the voltage deceiving chip 10 and the fast charging protocol chip 50 to be tested, and charging protocol communication can be performed.

[0075] In some embodiments, please refer to Figure 5 As shown, the voltage control pins on the power chip 30 include three pins, namely VOLT_SCL, VOLT_SDA and VOLT_FB. The three pins are respectively used to transmit different charging control signals, which can also be understood as voltage regulation signals. Since voltage regulation can be implemented in a variety of adjustment methods, in order to adapt to the fast charging protocol chip 50 to be tested with different adjustment types, a variety of types of voltage control pins are set on the power chip 30 in the present application. Among them, the VOLT_SCL pin is used to transmit the clock control signal, the VOLT_SDA pin is used to transmit serial data, and the VOLT_FB pin is used to transmit the voltage feedback type signal. The VOLT_SCL pin, VOLT_SDA pin and VOLT_FB pin of the power chip 30 are respectively connected to the three pins of the same type of the fast charging protocol chip 50 to be tested, so as to realize the adjustment of the charging power signal output by the power chip 30.

[0076] Please refer to Figure 2 and Figure 3 As shown, the control chip 20 includes two burning pins, namely a first burning pin BURN_SCL and a second burning pin BURN_SDA. The two burning pins are respectively communicated with the two burning pins on the fast charging protocol chip 50 to be tested to realize the transmission of the burning file.

[0077] Please refer to Figure 5 and Figure 6As shown, the power chip 30 includes a charging signal pin VBUS_MON, which can also be understood as an electric energy output pin for outputting a charging power signal. The charging power signal can also be understood as a charging signal, which includes information such as a charging voltage and a charging current. The charging signal pin VBUS_MON of the power chip 30 is connected to the charging signal pin on the power detection chip 40. It can be understood that the power detection chip 40 is used to simulate electronic equipment and can receive the charging power signal output by the power chip 30.

[0078] Please refer to Figure 3 , Figure 4 and Figure 6 As shown, the control chip 20 includes two communication pins, namely a first communication pin SLT_SDA and a second communication pin SLT_SCL. The first communication pin SLT_SDA and the second communication pin SLT_SCL are respectively connected to the two communication pins on the voltage deception chip 10 for communication between the control chip 20 and the voltage deception chip 10; and the first communication pin SLT_SDA and the second communication pin SLT_SCL are also respectively connected to the two communication pins on the power detection chip 40 for communication between the control chip 20 and the power detection chip 40.

[0079] In some embodiments, in order to enable the power supply to provide an adaptive power supply voltage to each chip, the present application further provides a voltage conversion circuit. Figure 7 For a schematic diagram of the voltage conversion circuit structure provided in the embodiment of the present application, please refer to Figure 7 As shown, the voltage conversion circuit 70 includes a fifth capacitor C5, a sixth capacitor C6 and a voltage conversion chip U7. The input end of the voltage conversion chip U7 is the input end of the voltage conversion circuit 70, and the input end of the voltage conversion circuit 70 is used to connect the power supply, for example, the power supply in this embodiment is 12V; the output end of the voltage conversion chip U7 is the output end VCC of the voltage conversion circuit 70, and the output end of the voltage conversion circuit is used to connect to the power supply end of the control chip 20, the power supply end of the voltage deception chip 10, and the power supply end of the power detection chip 40 to output the converted voltage signal. For example, the voltage conversion circuit 70 can convert the power supply (12V) into a 5V voltage signal and output it from the output end VCC, that is, all voltage signals connected to the output end VCC in the circuit are 5V.

[0080] In some embodiments, the chip function detection circuit also includes a first power supply circuit and a second power supply circuit. The input end of the first power supply circuit is used to connect the output end VCC of the power supply or the voltage conversion circuit 70, and the output end of the first power supply circuit is used to connect the power supply pin of the fast charging protocol chip 50 to be tested. The input end of the second power supply circuit is used to connect the output end VCC of the power supply or the voltage conversion circuit 70, and the output end of the second power supply circuit is connected to the power supply pin of the power chip 30.

[0081] Please refer to Figure 3 As shown, the control chip 20 also includes a first power supply control pin POWER1 and a second power supply control pin POWER2. The first power supply control pin POWER1 is connected to the control end of the first power supply circuit, and the second power supply control pin POWER2 is connected to the control end of the second power supply circuit. The control chip 20 is also used to output corresponding control signals to the first power supply circuit and the second power supply circuit respectively; the control signal is used to control the first power supply circuit and the second power supply circuit to be turned on or off, thereby controlling the fast charging protocol chip 50 to be tested and the power chip 30 to be powered on or off.

[0082] Figure 8 For a schematic diagram of the structure of the first power supply circuit provided in the embodiment of the present application, please refer to Figure 8 As shown, the first power supply circuit 80 includes a first transistor Q1, a first resistor R1, a second resistor R2, a first capacitor C1 and a second capacitor C2. The first pole of the first transistor Q1 is the input end of the first power supply circuit 80, and the input end of the first power supply circuit 80 is used to connect the output end VCC of the voltage conversion circuit 70; the second pole of the first transistor Q1 is the output end VDD of the first power supply circuit 80; the first pole of the first transistor Q1 is also grounded through the first capacitor C1, and the second pole of the first transistor Q1 is grounded through the second capacitor C2; the first end of the first resistor R1 is connected to the first pole of the first transistor Q1, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is the control end of the first power supply circuit 80, and is connected to the first power supply control pin POWER1; the control pole of the first transistor Q1 is connected to the second end of the first resistor R1. The output end VDD of the first power supply circuit 80 is connected to the power supply pin of the fast charging protocol chip 50 to be tested.

[0083] Fig. 9 For a schematic diagram of the structure of the second power supply circuit provided in the embodiment of the present application, please refer to Fig. 9As shown, the second power supply circuit 90 includes a second transistor Q2, a third resistor R3, a fourth resistor R4, a third capacitor C3 and a fourth capacitor C4. The first pole of the second transistor Q2 is the input end of the second power supply circuit 90, and the input end of the second power supply circuit 90 is used to connect the power supply; the second pole of the second transistor Q2 is the output end VDD1 of the second power supply circuit 90; the first pole of the second transistor Q2 is also grounded through the third capacitor C3, and the second pole of the second transistor Q3 is grounded through the fourth capacitor C4; the first end of the third resistor R3 is connected to the first pole of the second transistor Q2, the second end of the third resistor R3 is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is the control end of the second power supply circuit 90, and is connected to the second power supply control pin POWER2; the control pole of the second transistor Q2 is connected to the second end of the third resistor R3. The output end VDD1 of the second power supply circuit 90 is connected to the power supply pin of the power chip 30.

[0084] During operation, the control chip 20 outputs corresponding control signals through the first power supply control pin POWER1 and the second power supply control pin POWER2, ​​which can lower the voltage at the first power supply control pin POWER1 or the second power supply control pin POWER2 to control the first transistor Q1 and the second transistor Q2 to be turned on or off, thereby controlling the fast charging protocol chip 50 to be tested and the power chip 30 to be powered on or off.

[0085] In some embodiments, the chip function detection circuit further includes a first pull-up circuit and a second pull-up circuit. The first pull-up circuit and the second pull-up circuit are used to provide a pull-up signal to the pin corresponding to the control chip 20, so that the pin corresponding to the control chip 20 is turned on and works, and ensures that the control chip 20 works in a stable state.

[0086] Fig.10 For a schematic diagram of the first pull-up circuit structure provided in the embodiment of the present application, please refer to Fig.10 As shown, the first pull-up circuit 201 includes a fifth resistor R5 and a sixth resistor R6; the first end of the fifth resistor R5 is used to connect to the output end VCC of the voltage conversion circuit 70, and the second end of the fifth resistor R5 is connected to the first burning pin BURN_SCL; the first end of the sixth resistor R6 is also used to connect to the output end VCC of the voltage conversion circuit 70, and the second end of the sixth resistor R6 is connected to the second burning pin BURN_SDA.

[0087] Fig.11 For a schematic diagram of the second pull-up circuit structure provided in the embodiment of the present application, please refer to Fig.11As shown, the second pull-up circuit 202 includes a seventh resistor R7 and an eighth resistor R8, the first end of the seventh resistor R7 is used to connect to the output end VCC of the voltage conversion circuit 70, and the second end of the seventh resistor R7 is connected to the first communication pin SLT_SDA; the first end of the eighth resistor R8 is also used to connect to the output end VCC of the voltage conversion circuit 70, and the second end of the eighth resistor R8 is connected to the second communication pin SLT_SCL.

[0088] In some embodiments, the chip function detection circuit also includes a reset circuit. Fig.12 For a schematic diagram of the reset circuit structure provided in the embodiment of the present application, please refer to Fig.12 As shown, the reset circuit 203 includes a ninth resistor R9 and a seventh capacitor C7; the first end of the ninth resistor R9 is used to connect to the output end VCC of the voltage conversion circuit 70, the second end of the ninth resistor R9 is connected to the first end of the seventh capacitor C7, and the second end of the seventh capacitor C7 is grounded. The control chip 20 includes a reset pin NRST, the second end of the ninth resistor R9 is connected to the reset pin NRST, and the reset circuit 203 is used to output a reset signal to the reset pin NRST, and the reset signal is used to control the delayed start of the chip function detection circuit.

[0089] In some embodiments, the chip function detection circuit further includes a clock circuit 204, and the clock circuit 204 is used to provide a clock signal to the control chip 20. Figure 3 As shown, the clock circuit includes a clock chip U13, an eighth capacitor C8 and a ninth capacitor C9; the control chip 20 includes a first clock pin 5 and a second clock pin 6; the first output pin 3 of the clock chip U13 is connected to the first clock pin 5 of the control chip 20, and the second output pin 1 of the clock chip U13 is connected to the second clock pin 6 of the control chip 20; the first output pin 3 of the clock chip U13 is also grounded through the eighth capacitor C8, and the second output pin of the clock chip U13 is also grounded through the ninth capacitor C9.

[0090] In some embodiments, the function detection circuit further includes a filter circuit 205, the input end of the filter circuit 205 is connected to the charging signal pin of the power detection chip, and the output end of the filter circuit 205 is grounded; the filter circuit 205 includes at least one capacitor. For example, specifically, the filter circuit 205 includes a tenth capacitor C10 and an eleventh capacitor C11, and the tenth capacitor C10 and the eleventh capacitor C11 are arranged in parallel.

[0091] In some embodiments, the control chip 20 can select a common MCU (Microcontroller Unit), for example, a commonly used MCU model STM32 on the market can be selected. Based on the basic functions and functional pins of the STM32 chip, the above-mentioned test process can be implemented.

[0092] It can be understood that the voltage spoofing chip 10 is essentially a fast charging protocol chip used in electronic devices. Therefore, it can select the fast charging protocol chip commonly used in the market for electronic devices (such as mobile phones). For example, the commonly used fast charging protocol chip model SC2021 on the market can be selected. Based on the basic functions and functional pins of the SC2021 chip, the above-mentioned testing process can be realized.

[0093] It can be understood that the power chip 30 is essentially a buck-boost chip, which is mainly used for boosting and bucking. Therefore, it can select commonly used chips with boosting and bucking circuits. For example, the common power chip model SC8721 on the market can be selected. The basic functions and functional pins of the SC8721 chip can realize the above-mentioned test process.

[0094] It can be understood that the power detection chip 50 is essentially a fast charging protocol chip, which can use the common power detection chip model SC2001 on the market. The basic functions and functional pins of the SC2001 chip can realize the above-mentioned test process.

[0095] An embodiment of the present application also provides a chip function detection device, which includes the chip function detection circuit as described above.

[0096] Fig.13 For a schematic diagram of the chip function detection device provided in the embodiment of the present application, please refer to Fig.13 As shown, in some embodiments, the chip function detection device also includes a display 131, and the display 131 is specifically connected to the control chip 20; the display 131 is used to display the function detection result of the fast charging protocol chip to be tested output by the control chip 20.

[0097] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip function detection circuit, used to perform function detection on a fast charging protocol chip to be tested after being burned, characterized in that: The function detection circuit comprises: a control chip, a voltage deception chip, a power chip and a power detection chip; The communication pin of the control chip is connected to the communication pin of the voltage deception chip; the fast charging protocol communication pin of the voltage deception chip is used to connect to the fast charging protocol communication pin of the fast charging protocol chip to be tested; The voltage control pin of the power chip is used to connect to the voltage control pin of the fast charging protocol chip to be tested; the charging signal pin of the power chip is connected to the charging signal pin of the power detection chip; The communication pin of the power detection chip is also connected to the communication pin of the control chip; Among them, the control chip is used to send a function detection signal to the voltage deception chip; the voltage deception chip is used to send a charging request signal to the fast charging protocol chip to be tested according to the function detection signal, and the charging request signal includes a target charging power value during charging; The fast charging protocol chip to be tested is used to send a charging control signal to the power chip according to the charging request signal; the power chip is used to output a corresponding charging power signal according to the charging control signal; The power detection chip is used to receive the charging power signal, detect the actual charging power value of the charging power signal, and send the detected actual charging power value to the control chip; The control chip is used to determine whether the actual charging power value matches the target charging power value, and output the function detection result of the fast charging protocol chip to be tested according to the matching result.

2. The chip function detection circuit according to claim 1, characterized in that: The burning pin of the control chip is used to connect with the burning pin of the fast charging protocol chip to be tested; The control chip is also used to transmit the file to be burned to the fast charging protocol chip to be tested through the burning pin.

3. The chip function detection circuit according to claim 1 or 2, characterized in that: Also includes a first power supply circuit and a second power supply circuit; The input end of the first power supply circuit is used to connect to a power supply, and the output end of the first power supply circuit is used to connect to a power supply pin of the fast charging protocol chip to be tested; The input end of the second power supply circuit is used to connect to a power supply, and the output end of the second power supply circuit is connected to a power supply pin of the power chip; The control chip further includes a first power supply control pin and a second power supply control pin, the first power supply control pin is connected to the control end of the first power supply circuit, and the second power supply control pin is connected to the control end of the second power supply circuit; The control chip is also used to output corresponding control signals to the first power supply circuit and the second power supply circuit respectively; the control signal is used to control the first power supply circuit and the second power supply circuit to be turned on or off, thereby controlling the fast charging protocol chip to be tested and the power supply chip to be powered on or off.

4. The chip function detection circuit according to claim 3, characterized in that: The first power supply circuit includes a first transistor, a first resistor, a second resistor, a first capacitor and a second capacitor; The first pole of the first transistor is the input end of the first power supply circuit, and the input end of the first power supply circuit is used to connect to the power supply; the second pole of the first transistor is the output end of the first power supply circuit; the first pole of the first transistor is also grounded through the first capacitor, and the second pole of the first transistor is grounded through the second capacitor; the first end of the first resistor is connected to the first pole of the first transistor, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is the control end of the first power supply circuit; the control pole of the first transistor is connected to the second end of the first resistor; The second power supply circuit includes a second transistor, a third resistor, a fourth resistor, a third capacitor and a fourth capacitor; The first pole of the second transistor is the input end of the second power supply circuit, and the input end of the second power supply circuit is used to connect to the power supply; the second pole of the second transistor is the output end of the second power supply circuit; the first pole of the second transistor is also grounded through the third capacitor, and the second pole of the second transistor is grounded through the fourth capacitor; the first end of the third resistor is connected to the first pole of the second transistor, the second end of the third resistor is connected to the first end of the fourth resistor, and the second end of the fourth resistor is the control end of the second power supply circuit; the control pole of the second transistor is connected to the second end of the third resistor.

5. The chip function detection circuit according to claim 4, characterized in that: Also includes a voltage conversion circuit, the voltage conversion circuit includes a fifth capacitor, a sixth capacitor and a voltage conversion chip; The input end of the voltage conversion chip is the input end of the voltage conversion circuit, and the input end of the voltage conversion circuit is used to connect the power supply; the output end of the voltage conversion chip is the output end of the voltage conversion circuit, and the output end of the voltage conversion circuit is used to connect to one or more of the power supply end of the control chip, the power supply end of the voltage deception chip, the power supply end of the power detection chip, and the input end of the first power supply circuit to output the converted voltage signal; The input end of the voltage conversion chip is grounded through the fifth capacitor, and the output end of the voltage conversion chip is grounded through the sixth capacitor.

6. The chip function detection circuit according to claim 1 or 2, characterized in that: Also including a first pull-up circuit and a second pull-up circuit; The first pull-up circuit includes a fifth resistor and a sixth resistor; the control chip includes a first programming pin and a second programming pin, the first end of the fifth resistor is used to connect to the power supply, and the second end of the fifth resistor is connected to the first programming pin; the first end of the sixth resistor is also used to connect to the power supply, and the second end of the sixth resistor is connected to the second programming pin; The second pull-up circuit includes a seventh resistor and an eighth resistor; the control chip includes a first communication pin and a second communication pin, the first end of the seventh resistor is used to connect to the power supply, and the second end of the seventh resistor is connected to the first communication pin; the first end of the eighth resistor is also used to connect to the power supply, and the second end of the eighth resistor is connected to the second communication pin.

7. The chip function detection circuit according to claim 1 or 2, characterized in that: Also includes a reset circuit, the reset circuit includes a ninth resistor and a seventh capacitor; The first end of the ninth resistor is used to connect to the power supply, the second end of the ninth resistor is connected to the first end of the seventh capacitor, and the second end of the seventh capacitor is grounded; The control chip comprises a reset pin, and the second end of the ninth resistor is connected to the reset pin; the reset circuit is used for outputting a reset signal to the reset pin.

8. The chip function detection circuit according to claim 1 or 2, characterized in that: Also includes a clock chip, an eighth capacitor and a ninth capacitor; The control chip comprises a first clock pin and a second clock pin; the first output pin of the clock chip is connected to the first clock pin of the control chip, and the second output pin of the clock chip is connected to the second clock pin of the control chip; The first output pin of the clock chip is also grounded through the eighth capacitor, and the second output pin of the clock chip is also grounded through the ninth capacitor.

9. The chip function detection circuit according to claim 1 or 2, characterized in that: It also includes filtering circuits, The input end of the filter circuit is connected to the charging signal pin of the power detection chip, and the output end of the filter circuit is grounded; the filter circuit includes at least one capacitor.

10. A chip function detection device, characterized in that: The invention comprises a chip function detection circuit as described in any one of claims 1 to 9.

11. The chip function detection device according to claim 10, characterized in that: Also includes a display, the display is connected to the control chip; The display is used to display the function detection result of the fast charging protocol chip to be tested output by the control chip.

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