Salient point structure and chip
By designing a bump structure with a rough surface metal adhesion layer, the problem of cracking in the traditional bump structure is solved, the heat resistance and vibration resistance are improved, and the reliability and electrical performance of the chip are enhanced.
Patent Information
- Application Number
- CN202420723527.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-09
- Publication Date
- 2025-03-28
- Estimated Expiration
- 2034-04-09
AI Technical Summary
Traditional convex structures are prone to cracks under the influence of thermal shock and other factors, which affects the reliability and electrical performance of the product.
A bump structure including a pad, a metal adhesive layer and a bump is designed. The top surface of the metal adhesive layer is a rough surface, which is closely combined with the bump to improve heat resistance and vibration resistance.
The heat resistance and vibration resistance of the convex structure are improved, cracks occur, and contact reliability and electrical performance are improved.
Smart Images
Figure CN222690675U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor chips, in particular to a convex point structure and a chip. Background Art
[0002] With the rapid development of the semiconductor industry, the requirements for chip integration are getting higher and higher. Packaging technology is developing towards high density, thinness and miniaturization, and flip chip technology has emerged. Different from the previous chip packaging method, flip chip is interconnected with the substrate through bumps. This technology can make the ratio of chip area to packaging area closer to the ideal 1:1. As the chip is used for a longer time and the use environment becomes more severe, the traditional bump structure is prone to cracks in the bumps due to thermal shock and other effects, thus affecting the reliability of the product. Utility Model Content
[0003] One of the purposes of the utility model is to provide a bump structure and a chip, which can improve the heat resistance and vibration resistance of the bump structure, improve the problem that the bump structure is prone to cracks, reduce the poor contact caused by the bump cracks, reduce the connection resistance and signal loss of the bump structure, improve the connection reliability of the bump structure, and improve the reliability and electrical performance of the chip.
[0004] In order to achieve the above-mentioned purpose, the utility model provides a bump structure on one hand. The bump structure includes a pad, a metal adhesion layer and a bump, wherein the pad is located on the surface of a substrate, the metal adhesion layer is located above the pad, and the bump is located on the metal adhesion layer, wherein the top surface of the metal adhesion layer contacts the bump, and the top surface of the metal adhesion layer is a rough surface.
[0005] Optionally, the roughness of the top surface of the metal adhesion layer is Ra, 100nm <Ra<500nm。
[0006] Optionally, Ra is less than 250 nm.
[0007] Optionally, a passivation layer and a dielectric layer located on the passivation layer are formed on the substrate, and a via hole is provided on the pad, wherein the via hole penetrates the passivation layer and the dielectric layer on the pad, and a portion of the metal adhesion layer is filled in the via hole or the metal adhesion layer is located above the via hole.
[0008] Optionally, the bump structure also includes a bottom metal layer and an intermediate metal layer; the bottom metal layer conformally covers the inner surface of the via hole; the intermediate metal layer is located on the bottom metal layer, and a portion of the intermediate metal layer fills the via hole, and another portion protrudes out of the via hole; the metal adhesion layer is located on the intermediate metal layer.
[0009] Optionally, the intermediate metal layer is columnar.
[0010] Optionally, the metal adhesion layer covers the inner surface of the via hole but does not completely fill the via hole; a portion of the bump fills the via hole, and another portion of the bump protrudes out of the via hole.
[0011] Optionally, the passivation layer has a first window corresponding to the position of the pad, the dielectric layer covers the passivation layer and fills a portion of the first window of the passivation layer, and the via is located in the passivation layer and within the first window.
[0012] Optionally, a surface of the bump away from the metal adhesion layer is arc-shaped.
[0013] Another aspect of the present invention provides a chip, which includes a substrate and a bump structure located on the substrate.
[0014] In the bump structure and chip provided by the utility model, the bump structure includes a pad, a metal adhesion layer and a bump, the pad is located on the surface of the substrate, the metal adhesion layer is located above the pad, and the bump is located on the metal adhesion layer, wherein the top surface of the metal adhesion layer is in contact with the bump, and the top surface of the metal adhesion layer is a rough surface, so that the bump and the metal adhesion layer are tightly combined, which can improve the heat resistance and vibration resistance of the bump structure, improve the problem that the bump structure is prone to cracks, reduce the poor contact caused by bump cracks, reduce the connection resistance and signal loss of the bump structure, improve the connection reliability of the bump structure, and improve the reliability and electrical performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 A schematic diagram of a bump structure provided in one embodiment of the utility model.
[0016] Figure 2 A schematic diagram of a bump structure provided in another embodiment of the utility model.
[0017] Figure 3 This is a slice diagram of the rough surface of the metal adhesion layer in one embodiment of the utility model.
[0018] Explanation of the reference numerals: 10 - substrate; 11 - pad; 12 - passivation layer; 13 - dielectric layer; 14 - metal adhesion layer; 15 - bump; 16 - via hole; 17 - intermediate metal layer; 18 - bottom metal layer. DETAILED DESCRIPTION
[0019] The inventors have found that as the chip is used for a longer time and in more harsh environments, the traditional bump structure is prone to cracks due to influences such as thermal shock, and the probability of cracks forming between the solder bump and the metal layer in the bump structure is relatively high, affecting the reliability and electrical performance of the product.
[0020] To this end, the utility model provides a bump structure and a chip including the bump structure, wherein the bump structure includes a pad, a metal adhesion layer and a bump, the pad is located on the surface of the substrate, the metal adhesion layer is located above the pad, and the bump is located on the metal adhesion layer, wherein the top surface of the metal adhesion layer is in contact with the bump, and the top surface of the metal adhesion layer is a rough surface, so that the bump and the metal layer are tightly combined, which can improve the heat resistance and vibration resistance of the bump structure, improve the problem of cracks in the bump structure, reduce poor contact caused by bump cracks, reduce the connection resistance and signal loss of the bump structure, improve the connection reliability of the bump structure, and improve the reliability and electrical performance of the chip.
[0021] The bump structure and chip proposed by the utility model are further described in detail below in combination with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the utility model will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the utility model.
[0022] As used in the present invention, the singular forms "a", "an", and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. The terms "first", "second", and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.
[0023] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it may be directly on, adjacent to, or connected to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. Unless otherwise indicated, "upper / upper layer" and / or "lower / lower layer" and the like are merely for ease of description and are not limited to one position or one spatial orientation.
[0024] Figure 1Schematic diagram of the bump structure provided by an embodiment of the present utility model. Figure 2 Schematic diagram of the bump structure provided by another embodiment of the present utility model. Refer to Figure 1 and Figure 2 As shown, the bump structure provided by the present application includes a pad 11, a metal adhesion layer 14, and a bump 15. The pad 11 is located on the surface of the substrate 10. The metal adhesion layer 14 is located above the pad 11. The bump 15 is located on the metal adhesion layer 14. Among them, the top surface of the metal adhesion layer 14 is in contact with the bump 15, and the top surface of the metal adhesion layer 14 is a rough surface.
[0025] Exemplarily, the substrate 10 includes but is not limited to a silicon substrate, a gallium arsenide substrate, a lithium tantalate or lithium niobate substrate. The material of the pad 11 includes but is not limited to aluminum or copper.
[0026] Exemplarily, the material of the bump 15 includes tin. For example, the bump 15 can be a pure tin solder ball or a tin-based alloy solder ball. The tin-based alloy can be a tin-silver alloy or a tin-silver-copper alloy, etc.
[0027] As Figure 1 and Figure 2 shown, the bump 15 is directly in contact and bonded with the metal adhesion layer 14. The surface of the bump 15 away from the metal adhesion layer 14 can be arc-shaped. The material of the metal adhesion layer 14 includes copper and / or titanium, but is not limited thereto.
[0028] As Figure 1 and Figure 2 shown, the top surface of the metal adhesion layer 14 in contact with the bump 15 is a rough surface to improve the bonding force between the bump 15 and the metal adhesion layer 14.
[0029] Exemplarily, the top surface of the metal adhesion layer 14 can be made into a rough surface by mechanical sandblasting or chemical sandblasting. It should be noted that the method of making the top surface of the metal adhesion layer 14 into a rough surface is not limited to mechanical sandblasting and chemical sandblasting.
[0030] Figure 3 Cross-sectional view of the rough surface of the metal adhesion layer in an embodiment of the present utility model. As Figure 3 shown, the rough surface of the metal adhesion layer 14 is a non-smooth surface in microscopic morphology, and can even be a surface with burrs.
[0031] In this embodiment, the roughness of the top surface of the metal adhesion layer 14 is Ra, and Ra can be greater than 100 nm and less than 500 nm, that is, 100 nm < Ra < 500 nm. Exemplarily, Ra is greater than 100 nm and less than 250 nm.
[0032] When the space reserved for the bumps in the chip structure is small, the corresponding bump size will also be small. At this time, by forming a rough surface through sandblasting, the bonding force between the metal adhesion layer and the bumps can be increased as much as possible in a limited area.
[0033] refer to Figure 1 and Figure 2 As shown, a passivation layer 12 and a dielectric layer 13 located on the passivation layer 12 are formed on the substrate 10, and a via hole 16 is provided on the pad 11. The via hole 16 penetrates the passivation layer 12 and the dielectric layer 13 on the pad 11, and the bottom surface of the via hole 16 is located on the surface of the pad 11.
[0034] like Figure 1 and Figure 2 As shown, in some embodiments, the passivation layer 12 has a first window corresponding to the position of the pad 11, the dielectric layer 13 covers the passivation layer 12 and fills part of the first window of the passivation layer 12, and the via 16 is located in the passivation layer 12 and in the first window. Figure 1 As shown, the via hole 16 can be a via hole that is wide at the top and narrow at the bottom, which makes it easy to fill the via hole 16 to form a bump structure, and the filling quality of the via hole 16 is good, which is beneficial to improving the reliability and electrical performance of the bump structure.
[0035] In some other embodiments, the passivation layer 12 has a first window corresponding to the position of the pad 11, the dielectric layer 13 has a second window corresponding to the position of the first window, the second window and the first window are stacked to form a conductive hole 16, and the width of the second window can be equal to the width of the first window.
[0036] Exemplarily, the passivation layer 12 is a protective layer formed on the surface of the substrate 10, and its main function is to prevent the surface of the substrate from being contaminated and oxidized. The material of the passivation layer 12 includes but is not limited to silicon dioxide and silicon nitride. The material of the dielectric layer 13 can be polyimide (PI), poly(p-phenylene benzobisoxazole) (PBO) and benzocyclobutene (BCB), etc.
[0037] For example, in some embodiments, Figure 1 As shown, the metal adhesion layer 14 is located above the via hole 16. Specifically, the bump structure may include a bottom metal layer 18 and an intermediate metal layer 17; the bottom metal layer 18 conformally covers the inner surface of the via hole 16; the intermediate metal layer 17 is located on the bottom metal layer 18, a part of the intermediate metal layer 17 is filled in the via hole 16, and another part protrudes from the via hole 16; the metal adhesion layer 14 is located on the intermediate metal layer 17.
[0038] The material of the bottom metal layer 18 includes titanium and / or copper, but is not limited thereto. The bottom metal layer 18 may be formed by a sputtering process, but is not limited thereto.
[0039] The intermediate metal layer 17 may be columnar. The intermediate metal layer 17 may be a single-layer structure or a multi-layer stacked structure. The intermediate metal layer 17 may be formed by an electroplating process, and the material of the intermediate metal layer 17 includes but is not limited to copper. The metal adhesion layer 14 is attached to the top of the intermediate metal layer 17, and the material of the metal adhesion layer 14 includes but is not limited to copper.
[0040] In some embodiments, Figure 2 As shown, part of the metal adhesion layer 14 is filled in the via hole 16. Specifically, as Figure 2 As shown, the metal adhesion layer 14 covers the inner surface of the via hole 16 but does not fill the via hole 16. The metal adhesion layer 14 serves as the bottom metal layer of the bump structure and is partially adhered to the pad 11. The bump 15 is directly disposed on the top surface of the metal adhesion layer 14. A portion of the bump 15 is filled in the via hole 16, and another portion of the bump 15 protrudes out of the via hole 16. Exemplarily, the material of the metal adhesion layer 14 includes, but is not limited to, titanium and / or copper; the material of the bump 15 includes, but is not limited to, pure tin.
[0041] like Figure 2 As shown, the metal adhesion layer 14 may extend from the via hole 16 to cover a portion of the surface of the dielectric layer 13 , so that the metal adhesion layer 14 may completely support the bump 15 .
[0042] The present application also provides a chip, which includes a substrate 10 and the above-mentioned bump structure located on the substrate 10 .
[0043] Exemplarily, the chip may be a flip chip, which is electrically connected to other components such as a circuit board via a bump structure on the surface.
[0044] In the bump structure and chip provided by the utility model, the bump structure includes a pad 11, a metal adhesion layer 14 and a bump 15, the pad 11 is located on the surface of the substrate 10, the metal adhesion layer 14 is located above the pad 11, and the bump 15 is located on the metal adhesion layer 14, wherein the top surface of the metal adhesion layer 14 is in contact with the bump 15, and the top surface of the metal adhesion layer 14 is a rough surface, so that the bump 15 and the metal adhesion layer 14 are tightly combined, which can improve the heat resistance and vibration resistance of the bump structure, improve the problem that the bump structure is prone to cracks, reduce the poor contact caused by bump cracks, reduce the connection resistance and signal loss of the bump structure, improve the connection reliability of the bump structure, and improve the reliability and electrical performance of the chip.
[0045] It should be noted that "one embodiment" or "some embodiments" mentioned throughout the specification means that the specific components, structures or features described together with the embodiment are included in at least one embodiment. Therefore, the phrases "one embodiment" or "some embodiments" appearing in various places throughout the specification do not necessarily refer to the same embodiment. Moreover, in one or more embodiments, specific components, structures or features can be combined in any suitable manner.
[0046] The above description is only a description of the preferred embodiment of the utility model, and is not any limitation on the scope of rights of the utility model. Any technical personnel in this field can make possible changes and modifications to the technical solution of the utility model by using the methods and technical contents disclosed above without departing from the spirit and scope of the utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the utility model without departing from the content of the technical solution of the utility model are within the protection scope of the technical solution of the utility model.
Claims
1. A bump structure, characterized in that: The bump structure includes a pad, a metal adhesion layer and a bump, wherein the pad is located on the surface of the substrate, the metal adhesion layer is located above the pad, and the bump is located on the metal adhesion layer, wherein the top surface of the metal adhesion layer contacts the bump, and the top surface of the metal adhesion layer is a rough surface.
2. The bump structure according to claim 1, characterized in that: The roughness of the top surface of the metal adhesion layer is Ra, 100nm <Ra<500nm。 3. The bump structure according to claim 2, characterized in that: Ra is less than 250nm.
4. The bump structure according to claim 1, characterized in that: A passivation layer and a dielectric layer located on the passivation layer are formed on the substrate, and a via hole is provided on the pad, wherein the via hole penetrates the passivation layer and the dielectric layer on the pad, and a portion of the metal adhesion layer is filled in the via hole or the metal adhesion layer is located above the via hole.
5. The bump structure according to claim 4, characterized in that: The bump structure also includes a bottom metal layer and an intermediate metal layer; the bottom metal layer conformally covers the inner surface of the via hole; the intermediate metal layer is located on the bottom metal layer, and a portion of the intermediate metal layer fills the via hole, and another portion protrudes from the via hole; the metal adhesion layer is located on the intermediate metal layer.
6. The bump structure according to claim 5, characterized in that: The intermediate metal layer is columnar.
7. The bump structure according to claim 4, characterized in that: The metal adhesion layer covers the inner surface of the via hole but does not fill up the via hole; a portion of the bump is filled in the via hole, and another portion of the bump protrudes out of the via hole.
8. The bump structure according to claim 4, characterized in that: The passivation layer has a first window corresponding to the position of the pad, the dielectric layer covers the passivation layer and fills a portion of the first window of the passivation layer, and the via is located in the passivation layer and within the first window.
9. The bump structure according to claim 1, characterized in that: The surface of the bump away from the metal adhesion layer is arc-shaped.
10. A chip, characterized in that: The invention comprises a substrate and a bump structure as claimed in any one of claims 1 to 9 located on the substrate.