Double-skew integral AD conversion device with high conversion resolution

Abstract

The utility model discloses a double-skew integral AD conversion device with high conversion resolution, which comprises a frequency generator, an n frequency divider, a double-skew integral AD converter, a gating counting sampler, a counter, a data buffer and a central processing unit which are sequentially connected, and the central processing unit is respectively connected with the double-skew integral AD converter and the counter. And the frequency generator is connected with the gating counting sampler. According to the utility model, through introducing the frequency generator and the n frequency divider, double groups of frequency signals are obtained, the AD conversion resolution can be improved from the original s to s / n, and the problem of insufficient resolution is well solved.

Description

Technical Field

[0001] The utility model relates to a double-slope integral AD conversion device with high conversion resolution, belonging to the technical field of sensors and measurements. Background Art

[0002] The dual-integration A / D converter uses an integrator to integrate the measured voltage twice, in the forward and reverse directions (such as Figure 1 As shown), the time interval T which is linearly related to the average value of the input voltage is obtained. Finally, the reference pulses in the time interval T are counted, and the value corresponding to the measured voltage value is further output based on the count value. Due to the use of the integral circuit, the dual-integral A / D converter has significant anti-interference ability, and also has the advantages of high conversion accuracy and low cost. It is widely used in sensors and detection circuits where the conversion speed requirement is not high.

[0003] The ICL7135 chip is the most widely used dual-slope integral AD converter chip in engineering. ICL7135 has five fields of "ten thousand, thousand, hundred, ten, and individual", and can output 39998 digital numbers in the range of -19999 to +19999. It has a measurement resolution of 1 / 20000, which can meet most measurement needs. However, for measurement needs with higher precision (such as the measurement circuit of the differential resistance sensor requires a measurement resolution of 1 / 100000), it is impossible to achieve it by directly using the ICL7135 dual-slope integral. Utility Model Content

[0004] Purpose of the utility model: In view of the problem that the insufficient AD conversion resolution of the dual-slope integral AD converter may lead to the inability to meet certain high-precision measurement requirements, the utility model provides a dual-slope integral AD conversion device with high conversion resolution.

[0005] Technical solution: To achieve the above purpose, the technical solution adopted by this utility model is:

[0006] A dual-slope integral AD conversion device with high conversion resolution comprises a frequency generator, an n-frequency divider, a dual-slope integral AD converter, a gated counting sampler, a counter, a data buffer and a central processing unit which are connected in sequence. The central processing unit is connected to the dual-slope integral AD converter and the counter respectively, and the frequency generator is connected to the gated counting sampler.

[0007] Preferably: the frequency generator is used to generate a frequency f H The n frequency divider is used to divide the continuous pulse signal according to the frequency f H A continuous pulse signal with a frequency of f L The continuous pulse signal 2 is a continuous pulse signal, and the frequency of the continuous pulse signal 1 is n times the frequency of the continuous pulse signal 2.

[0008] Preferably: the double slope integrating AD converter is used to convert the L The continuous pulse signal 2, the reference voltage Vref and the input voltage Vin are positively and negatively integrated to obtain the indication signal BUSY.

[0009] Preferably: the gated counting sampler is based on the indication signal BUSY to obtain a frequency of f H The continuous pulse signal is used for pulse acquisition; the frequency of the counter used for pulse acquisition is f H The continuous pulse signal is counted; the data buffer is used to store the count of the counter.

[0010] Preferably: the central processing unit is used to clear the counter before starting counting each time.

[0011] Preferably: the dual-slope integrating AD converter is an ICL7135 chip; the POL pin of the ICL7135 chip is connected to the input port one I1 of the central processing unit, the BUSY pin of the ICL7135 chip is connected to the input port two I2 of the central processing unit, the output pin of the data buffer is connected to the input port three I3 of the central processing unit, and the output port two O2 and output port three O3 of the central processing unit are connected to the input pin of the data buffer.

[0012] Preferably, the frequency generator is an active crystal oscillator in the form of a HO-12C packaged crystal oscillator; the n-frequency divider is a 74HC4040 binary serial counter chip.

[0013] Preferably, the central processing unit is an AT89C55WD single-chip microcomputer; the gated counting sampler is a 74HC08 dual-input AND gate.

[0014] Preferably: the counter comprises two 74HC4040 binary serial counter chips cascaded together; the data buffer comprises three 74HC165 serial input shift registers cascaded together.

[0015] Compared with the prior art, the utility model has the following beneficial effects:

[0016] The utility model obtains a double set of frequency signals by introducing a frequency generator and an n frequency divider. Since the frequency generated by the frequency generator is f H The continuous pulse signal is generated by the n-frequency divider with a frequency of f L The output data of the double slope integral AD converter in the original design is based on f L The count value N LTherefore, the dual-slope integrating AD converter is based on f H The synchronization count value N H will be N L n times, which can increase the AD conversion resolution from the original s to The problem of insufficient resolution has been solved better. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of the working principle of the dual-slope integrating AD converter.

[0018] Figure 2 Schematic diagram of the structure of a dual-slope integral AD conversion device with high conversion resolution.

[0019] Figure 3 Schematic diagram of the double-set standard frequency counting measurement method. DETAILED DESCRIPTION

[0020] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. It should be understood that these examples are only used to illustrate the present invention and are not used to limit the scope of the present invention. After reading the present invention, various equivalent forms of modifications to the present invention by those skilled in the art all fall within the scope defined by the claims attached to this application.

[0021] For the measurement requirements of higher precision (such as the measurement circuit of the differential resistance sensor requires a measurement resolution of 1 / 100000), it is impossible to directly use the ICL7135 dual-slope integral AD converter. After a comprehensive and detailed study of the working principle of the dual-integral A / D converter, we found that for a specified reference frequency f L , input voltage U in Regardless of size, the time T of the forward integration process 正 is fixed. Taking ICL7135 chip as an example, T 正 is 10,000 pulses, that is, T 正 =10000 / f L . Such as f L =250KHz, Tforward = 40 (ms). The time of the reverse integration process Treverse is related to the input voltage U in The size of the chip is proportional to the reference frequency f. L The count is used to realize T 反 Taking ICL7135 as an example, T 反 The maximum value of corresponds to about 20,000 pulses. The value of 20,000 determines the resolution that ICL7135 can achieve, s = 1 / 20,000, which is equivalent to a 14-bit resolution. H =n×f LAs the new reference frequency to measure T 反 , T 反 The maximum value of can correspond to the new reference frequency f H The number of pulses is 20000×n, making the measurement resolution s new achieve The measurement resolution is improved. The larger the n, the better the resolution. new The more the resolution is, the more obvious the improvement is. Taking n=8 as an example, it is equivalent to reaching 17-bit resolution.

[0022] Based on the above analysis, we designed a high conversion resolution dual slope integral AD conversion device, such as Figure 2 As shown, it includes a frequency generator, an n-divider, a dual-slope integrating AD converter, a gated counting sampler, a counter, a data buffer and a central processing unit which are connected in sequence. The central processing unit is connected to the dual-slope integrating AD converter and the counter respectively, and the frequency generator is connected to the gated counting sampler.

[0023] In another embodiment, if Figure 2 and 3 As shown, the frequency generator is used to generate a frequency f H The n frequency divider is used to divide the continuous pulse signal according to the frequency f H A continuous pulse signal with a frequency of f L The continuous pulse signal of f L =f H / n.

[0024] The dual-slope integrating AD converter is used to convert the frequency f L The continuous pulse signal 2, the reference voltage Vref and the input voltage Vin are positively and negatively integrated to obtain the indication signal BUSY. The frequency is f L The continuous pulse signal is connected to the CLOCKIN pin of the dual slope integral AD converter as the time base for the AD converter to perform forward integration and reverse integration. Each conversion process of the AD converter includes three processes: self-calibration (zero adjustment), forward integration and reverse integration. The self-calibration (zero adjustment) process takes a time length of T 自 Yes L The number of pulses of a fixed signal, taking ICL7135 as an example, T 自 =10001 / f L The forward integration process takes time T 正 It is also fixed. Taking ICL7135 as an example, T 正 is 10,000 pulses, that is, T 正 =10000 / f LThe forward integration is the integration process for the reference voltage |Vin|. The reverse integration process is the integration process for the measured voltage - Vref. The duration of the reverse integration process is determined by Vref and |Vin|. During the conversion process of the AD converter, an indication signal BUSY is given from the beginning of the forward integration to the end of the reverse integration. Taking ICL7135 as an example, when BUSY is high, it means that the AD converter is in the process of forward integration and reverse integration ( Figure 3 ). Length of time that BUSY high level lasts

[0025] The BUSY signal is used as the start and stop control signal of the gated counter sampler. When the BUSY signal changes from low level to high level, the gated counter sampler starts to H The pulse signal is collected by the counter. When the BUSY signal changes from high level to low level, the gated counting sampler ends the sampling of f H The pulses of the signal are collected and the counter stops counting.

[0026] This utility model inherits the f L Perform "positive integral fixed count + reverse integral variable count (reverse integral count value and The original design of "is proportional to" and a new design based on f H Synchronous counting method, where f H Yes L The output data of the dual slope integral AD converter in the original design is based on f L The count value N L Generate, now using the double counting method, based on f H The synchronization count value N H will be N L n times, which can increase the AD conversion resolution from the original s to

[0027] In another embodiment, the gated counter sampler generates a signal of frequency f according to the indication signal BUSY. H The continuous pulse signal is used for pulse acquisition; the frequency of the counter used for pulse acquisition is f H The continuous pulse signal is counted; the data buffer is used to store the count of the counter. The BUSY signal is used as the start and stop control signal of the gated counting sampler. When the BUSY signal changes from a low level to a high level, the gated counting sampler starts to count f HThe pulse signal is collected by the counter. When the BUSY signal changes from high level to low level, the gated counting sampler ends the sampling of f H The signal pulse is collected and the counter stops counting. The counter value N H It is stored in the data buffer and read by the CPU through a serial bus (such as an SPI serial bus, which is composed of the CPU's input port I3 and output ports O2 and O3).

[0028] The value of the counter N H Stored in the data buffer, the CPU reads it through a serial bus (such as an SPI serial bus, which is composed of the CPU's input port I3 and output ports O2 and O3). In order to facilitate the determination of the input voltage Vin, and thus let the customer know the resolution of the utility model, the central processor calculates the resolution of the input voltage Vin according to the count and the frequency f H The continuous pulse signal 1 and the reference voltage Vref are used to obtain the input voltage Vin. B There are two ways to calculate: have to: Further:

[0029] The central processing unit is used to determine the positive and negative polarity of the input voltage Vin according to the positive and negative polarity indication signal of the dual-slope integral AD converter. The dual-slope integral AD converter will distinguish the positive and negative polarity of the input voltage Vin and indicate it through the POL pin. Taking ICL7135 as an example, when POL is high, it means that Vin is positive, and when POL is low, it means that Vin is negative. The POL pin is connected to the input port I1 of the CPU, and the CPU obtains the positive and negative polarity of Vin by reading the state of I1.

[0030] In another embodiment, the central processor is used to clear the counter before starting counting each time. H The counter should be cleared before starting counting each time, so a clear control signal needs to be set. The control signal is determined by the CPU according to the logical relationship of the input port I2 (connected to the BUSY signal) and is implemented in hardware through the output port O1.

[0031] In another embodiment, the dual-slope integrating AD converter is an ICL7135 chip; the central processing unit is an AT89C55WD single-chip microcomputer; the POL pin of the ICL7135 chip is connected to the input port one I1 of the AT89C55WD single-chip microcomputer, the BUSY pin of the ICL7135 chip is connected to the input port two I2 of the AT89C55WD single-chip microcomputer, the output pin of the data buffer is connected to the input port three I3 of the AT89C55WD single-chip microcomputer, and the output port two O2 and output port three O3 of the AT89C55WD single-chip microcomputer are connected to the input pin of the data buffer.

[0032] In another embodiment, the frequency generator can be implemented by an active crystal oscillator in a HO-12C package, preferably with a frequency of 4 MHz. The n-frequency divider can be implemented by a 74HC4040 binary (12-bit) serial counter chip, and n can preferably be 4, 8 or 16.

[0033] In another embodiment, the gated counter sampler is preferably implemented by a 74HC08 dual-input AND gate.

[0034] In another embodiment, the counter can be implemented by cascading two 74HC4040 binary (12-bit) serial counter chips. The data buffer can be implemented by cascading three 74HC165 serial input shift registers (8-bit). The CPU can be implemented by a single-chip microcomputer with more than three input ports and more than three output ports, such as an AT89C55WD single-chip microcomputer.

[0035] Under the orderly scheduling control of the CPU, based on a full understanding of the working mechanism of the dual slope integral AD converter, the utility model introduces two sets of frequency signals (the frequencies are f H 、f L ). Inherited from f L Perform "positive integral fixed count + reverse integral variable count (reverse integral count value and The original design of "is proportional to" and a new design based on f H Synchronous counting method, where f H Yes L The output data of the dual slope integral AD converter in the original design is based on f L The count value N L Generate, now using the double counting method, based on f H The synchronization count value N H will be N L n times, which can increase the AD conversion resolution from the original s to Better solve the problem of insufficient resolution

[0036] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A dual-slope integral AD conversion device with high conversion resolution, characterized in that: The invention comprises a frequency generator, an n-frequency divider, a dual-slope integral AD converter, a gated counting sampler, a counter, a data buffer and a central processing unit which are connected in sequence. The central processing unit is respectively connected to the dual-slope integral AD converter and the counter, and the frequency generator is connected to the gated counting sampler.

2. The double-slope integral AD conversion device with high conversion resolution according to claim 1, characterized in that: The frequency generator is used to generate a frequency f H The n frequency divider is used to divide the continuous pulse signal according to the frequency f H A continuous pulse signal with a frequency of f L The continuous pulse signal 2 is a continuous pulse signal, and the frequency of the continuous pulse signal 1 is n times the frequency of the continuous pulse signal 2.

3. The double-slope integral AD conversion device with high conversion resolution according to claim 2, characterized in that: The dual-slope integrating AD converter is used to convert the frequency f L The continuous pulse signal 2, the reference voltage Vref and the input voltage Vin are positively and negatively integrated to obtain the indication signal BUSY.

4. The double-slope integral AD conversion device with high conversion resolution according to claim 3, characterized in that: The gated counter sampler samples the frequency f according to the indication signal BUSY H The continuous pulse signal is used for pulse acquisition; the frequency of the counter used for pulse acquisition is f H The continuous pulse signal is counted; the data buffer is used to store the count of the counter.

5. The double-slope integral AD conversion device with high conversion resolution according to claim 4, characterized in that: The central processing unit is used to clear the counter before starting counting each time.

6. The double-slope integral AD conversion device with high conversion resolution according to claim 5, characterized in that: The dual-slope integrating AD converter is an ICL7135 chip; the POL pin of the ICL7135 chip is connected to the input port one I1 of the central processing unit, the BUSY pin of the ICL7135 chip is connected to the input port two I2 of the central processing unit, the output pin of the data buffer is connected to the input port three I3 of the central processing unit, and the output port two O2 and output port three O3 of the central processing unit are connected to the input pin of the data buffer.

7. The double-slope integral AD conversion device with high conversion resolution according to claim 6, characterized in that: The frequency generator is an active crystal oscillator in the form of a HO-12C packaged crystal oscillator; the n-frequency divider is a 74HC4040 binary serial counter chip.

8. The double-slope integral AD conversion device with high conversion resolution according to claim 7, characterized in that: The central processor is an AT89C55WD single-chip microcomputer; the gate-controlled counting sampler is a 74HC08 double-input AND gate.

9. The double-slope integral AD conversion device with high conversion resolution according to claim 8, characterized in that: The counter includes two 74HC4040 binary serial counter chips cascaded together; the data buffer includes three 74HC165 serial input shift registers cascaded together.

Images