Power unit, power supply device of processor core and server

Abstract

The embodiment of the utility model discloses a power unit, a power supply device of a processor core and a server. The power unit comprises 2N power paths; each of the 2N power paths is coupled in parallel between a voltage input terminal corresponding to the respective power path and a voltage output terminal corresponding to the respective power path, the voltage adjusting modules are used for adjusting the voltage of the direct current flowing in from the voltage input ends corresponding to the respective power paths and providing the adjusted direct current to the voltage output ends corresponding to the respective power paths; the voltage input ends corresponding to the respective power paths and the voltage output ends corresponding to the respective power paths are arranged on the first substrate, and N is a positive integer of at least 2; the 2N power channels are arranged at N arrangement positions on the first substrate in a spatial stacking manner, and two power channels are arranged at each arrangement position in a spatial stacking manner. Power channels are arranged in a space stacking mode to improve energy density, and the device is suitable for various power supply scenes.

Description

Technical Field

[0001] The utility model relates to the field of electronic equipment, and more specifically, to a power supply device for a power unit, a processor core, and a server. Background Art

[0002] As a power converter, a power block can convert high voltage DC input into low voltage DC output. A power block usually mainly includes a power switch and an inductor. For example, a power switch can include a metal-oxide-semiconductor field-effect transistor (MOSFET) and a power stage.

[0003] How to improve the energy density of power units on a printed circuit board (PCB) with limited space is a focus of the industry. Utility Model Content

[0004] The utility model provides a power unit, a power supply device for a processor core, and a server, which are helpful to improve the energy density of the power unit.

[0005] The technical solution of the utility model implementation is as follows:

[0006] A power unit, comprising:

[0007] 2N power paths;

[0008] Each of the 2N power paths is coupled in parallel between a voltage input terminal corresponding to the respective power path and a voltage output terminal corresponding to the respective power path, and is used to adjust the voltage of the direct current flowing from the voltage input terminal corresponding to the respective power path and provide the adjusted direct current to the voltage output terminal corresponding to the respective power path; wherein the voltage input terminal corresponding to the respective power path and the voltage output terminal corresponding to the respective power path are arranged on the first substrate, and N is a positive integer of at least 2;

[0009] The 2N power paths are arranged in a spatially stacked manner at N arrangement positions on the first substrate, wherein two power paths are arranged in a spatially stacked manner at each arrangement position.

[0010] In one embodiment, N is equal to 2.

[0011] In one embodiment, the 2N power paths include a first power path, a second power path, a third power path, and a fourth power path; wherein:

[0012] The first power path includes: a first power switch, arranged on the second substrate, coupled to a voltage input terminal corresponding to the first power path; a first inductor, arranged on the third substrate, connected in series between the first power switch and a voltage output terminal corresponding to the first power path;

[0013] The second power path includes: a second power switch, arranged on the first substrate, coupled to a voltage input terminal corresponding to the second power path; a second inductor, arranged on the second power switch, and connected in series between the second power switch and a voltage output terminal corresponding to the second power path;

[0014] The third power path includes: a third power switch, arranged on the second substrate, coupled to a voltage input terminal corresponding to the third power path; a third inductor, arranged on the third substrate, connected in series between the third power switch and a voltage output terminal corresponding to the third power path;

[0015] The fourth power path includes: a fourth power switch, arranged on the first substrate and coupled to a voltage input terminal corresponding to the fourth power path; a fourth inductor, arranged on the fourth power switch and connected in series between the fourth power switch and a voltage output terminal corresponding to the fourth power path;

[0016] The second substrate, the third substrate and the first substrate are spatially stacked with a fourth substrate, and the fourth substrate comprises an onboard voltage input terminal and an onboard voltage output terminal corresponding to respective power paths;

[0017] The second substrate and the third substrate are electrically connected to the first substrate via conductive pillars; the first substrate is electrically connected to the fourth substrate via a ball grid array;

[0018] The voltage input terminals corresponding to the respective power paths are electrically connected to the onboard voltage input terminals; and the voltage output terminals corresponding to the respective power paths are electrically connected to the onboard voltage output terminals corresponding to the respective power paths.

[0019] In one embodiment, the first inductor, the second inductor, the third inductor, and the fourth inductor are inductors in separate packages.

[0020] In one embodiment, the first inductor and the third inductor are packaged as a first integrated inductor, and the second inductor and the fourth inductor are packaged as a second integrated inductor; or

[0021] The first inductor, the second inductor, the third inductor and the fourth inductor are packaged into a third integrated inductor.

[0022] A power supply device for a processor core, comprising:

[0023] 2N power paths;

[0024] Each of the 2N power paths is coupled in parallel between a voltage input terminal corresponding to the respective power path and a voltage output terminal corresponding to the respective power path, and is used to adjust the voltage of the direct current flowing from the voltage input terminal corresponding to the respective power path and provide the adjusted direct current to the voltage output terminal corresponding to the respective power path; wherein the voltage input terminal corresponding to the respective power path and the voltage output terminal corresponding to the respective power path are arranged on the first substrate, and N is a positive integer of at least 2;

[0025] The voltage output terminals corresponding to the respective power paths are electrically connected to the processor cores corresponding to the respective power paths;

[0026] The 2N power paths are arranged in a spatially stacked manner at N arrangement positions on the first substrate, wherein two power paths are arranged in a spatially stacked manner at each arrangement position.

[0027] In one embodiment, N is equal to 2.

[0028] In one embodiment, the 2N power paths include a first power path, a second power path, a third power path, and a fourth power path; wherein:

[0029] The first power path includes: a first power switch, arranged on the second substrate, coupled to a voltage input terminal corresponding to the first power path; a first inductor, arranged on the third substrate, connected in series between the first power switch and a voltage output terminal corresponding to the first power path;

[0030] The second power path includes: a second power switch, arranged on the first substrate, coupled to a voltage input terminal corresponding to the second power path; a second inductor, arranged on the second power switch, and connected in series between the second power switch and a voltage output terminal corresponding to the second power path;

[0031] The third power path includes: a third power switch, arranged on the second substrate, coupled to a voltage input terminal corresponding to the third power path; a third inductor, arranged on the third substrate, connected in series between the third power switch and a voltage output terminal corresponding to the third power path;

[0032] The fourth power path includes: a fourth power switch, arranged on the first substrate and coupled to the voltage input terminal corresponding to the fourth power path; a fourth inductor, arranged on the fourth power switch and connected in series between the fourth power switch and the voltage output terminal corresponding to the fourth power path;

[0033] The second substrate, the third substrate and the first substrate are spatially stacked with a fourth substrate, and the fourth substrate comprises an onboard voltage input terminal and an onboard voltage output terminal corresponding to respective power paths;

[0034] The second substrate and the third substrate are electrically connected to the first substrate via conductive pillars; the first substrate is electrically connected to the fourth substrate via a ball grid array;

[0035] The voltage input terminals corresponding to the respective power paths are electrically connected to the onboard voltage input terminals; and the voltage output terminals corresponding to the respective power paths are electrically connected to the onboard voltage output terminals corresponding to the respective power paths.

[0036] A server, comprising:

[0037] 2N processor cores;

[0038] A power board, the power board comprising 2N power paths, an onboard voltage input terminal and 2N onboard voltage output terminals;

[0039] Each of the 2N power paths is coupled to the 2N processor cores in a one-to-one correspondence manner, and is used to power the corresponding processor core via an onboard voltage output terminal corresponding to the respective power path;

[0040] Each of the 2N power paths is coupled in parallel between a voltage input terminal corresponding to the respective power path and a voltage output terminal corresponding to the respective power path, and is used to adjust the voltage of the direct current flowing in from the voltage input terminal corresponding to the respective power path and provide the adjusted direct current to the voltage output terminal corresponding to the respective power path; wherein the voltage input terminal corresponding to the respective power path and the voltage output terminal corresponding to the respective power path are arranged on the first substrate, and N is a positive integer of at least 2; the 2N power paths are arranged in N arrangement positions on the first substrate in a spatially stacked manner, wherein 2 power paths are arranged in a spatially stacked manner at each arrangement position; wherein the voltage input terminal corresponding to the respective power path is electrically connected to the on-board voltage input terminal; and the voltage output terminal corresponding to the respective power path is electrically connected to the on-board voltage output terminal corresponding to the respective power path.

[0041] In one embodiment, the server is an artificial intelligence server.

[0042] It can be seen from the above technical solution that the power unit includes: 2N power paths; each of the 2N power paths is coupled in parallel between the voltage input terminal corresponding to the respective power path and the voltage output terminal corresponding to the respective power path. The voltage input terminal corresponding to the respective power path and the voltage output terminal corresponding to the respective power path are arranged on the first substrate, and N is a positive integer of at least 2; the 2N power paths are arranged in N arrangement positions on the first substrate in a spatially stacked manner, wherein 2 power paths are arranged in a spatially stacked manner at each arrangement position. It can be seen that the embodiment of the utility model does not directly install each power channel on the substrate, but arranges 2 power paths in a spatially stacked manner at each arrangement position of the substrate, saving substrate space. Under the same substrate size, the embodiment of the utility model can improve the energy density.

[0043] Moreover, the power unit is suitable for a variety of power supply environments with small space and high power consumption. The inductor in the power path also has a variety of packaging methods, which improves the packaging selectivity. In addition, the inductor itself is a good thermal conductive material, which is conducive to the thermal uniformity of the power unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is an exemplary structural diagram of a power unit including multiple power paths.

[0045] Figure 2 is an exemplary circuit diagram of a single power path.

[0046] Figure 3 FIG. 4 is a diagram showing an exemplary arrangement of a power unit on a substrate in the related art.

[0047] Figure 4A It is a first schematic diagram of the arrangement structure of the power unit according to the embodiment of the present utility model.

[0048] Figure 4B This is a second schematic diagram of the arrangement structure of the power unit according to an embodiment of the present utility model.

[0049] Figure 4C This is a third schematic diagram of the arrangement structure of the power unit according to an embodiment of the present utility model.

[0050] Figure 4D This is a fourth schematic diagram of the arrangement structure of the power unit according to an embodiment of the present utility model. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the utility model clearer, the utility model is further described in detail below with reference to the accompanying drawings.

[0052] For the sake of brevity and intuitiveness in description, the scheme of the utility model is explained below by describing several representative implementations. A large number of details in the implementation methods are only used to help understand the scheme of the utility model. However, it is obvious that the technical scheme of the utility model may not be limited to these details when implemented. In order to avoid unnecessary descriptions that blur the scheme of the utility model, some implementation methods are not described in detail, but only a framework is given. In the following, "including" means "including but not limited to", and "according to..." means "at least according to..., but not limited to only according to...". Due to the language habits of Chinese, when the number of a component is not specifically specified below, it means that the component can be one or more, or can be understood as at least one.

[0053] A power unit can contain a single or multiple power paths. Each power path can independently convert the input high voltage DC power into a low voltage DC power output to the load. When the load current is large, a power unit with a single power path usually cannot meet the power supply requirements. At this time, multiple power paths connected in parallel are required to supply power.

[0054] Figure 1 FIG. 1 is an exemplary structural diagram of a power unit including multiple power paths. Figure 1 In the embodiment, power unit 10 includes power path 11, power path 12, power path 13 and power path 14 connected in parallel.

[0055] The power path 11 is connected to the power path 11 via a voltage input terminal ( Figure 1 The power path 11 is connected to the power path 12 via the voltage input terminal (Vin) coupled to the power path 12. The power path 12 is connected to the power path 12 via the voltage input terminal (Vout1) coupled to the power path 12. Figure 1 The power path 13 is connected to the power path 13 via the voltage input terminal (Vin) and the voltage output terminal (Vout2) coupled to the power path 13. The power path 13 is connected to the power path 13 via the voltage input terminal (Vin) coupled to the power path 13. Figure 1The power path 14 is connected to the power path 14 via the voltage input terminal (Vin) and the voltage output terminal (Vout3) coupled to the power path 13. The power path 14 is connected to the power path 14 via the voltage input terminal (Vin) coupled to the power path 14. Figure 1 (not shown) inputs high voltage (e.g., 12 volts) direct current from a voltage input terminal (Vin), converts the high voltage direct current into low voltage (e.g., 1 volt) direct current, and provides the low voltage direct current to the outside via a voltage output terminal (Vout4) coupled to a power path 14.

[0056] The power paths 11, 12, 13 and 14 have the same structure and include respective power switches and inductors. For example, the power path 11 includes a first power switch 111 and a first inductor 112 connected in series between a voltage input terminal (Vin) and a voltage output terminal (Vout1) of the power path 11.

[0057] In the above description, the example of the power unit 10 including 4 power channels is used for exemplary explanation. In fact, the number of power channels included in the power unit 10 can be increased or decreased, and the embodiments of the present utility model are not limited to this. The various power paths in the power unit 10 can be implemented as the same circuit structure or different circuit structures. For example, the power path can be implemented as a Buck circuit or a Pre-Drive circuit or other circuits. Moreover, the Buck circuit can include an asynchronous Buck circuit and a synchronous Buck circuit.

[0058] The following takes the case where the power path is implemented as a synchronous Buck circuit as an example to illustrate an exemplary circuit structure of the power path. Figure 2 is an exemplary circuit diagram of a single power path. Figure 2 In the embodiment, the power channel 11 includes a power switch 111 and an inductor 112 arranged between a voltage input terminal (Vin) and a voltage output terminal (Vout). The voltage output terminal (Vout) is connected in series with a capacitor C and coupled to a ground (GND). The power switch 111 includes a first MOSFET tube (Q1) and a second MOSFET tube (Q2). When the first MOSFET tube (Q1) is turned on, the voltage input terminal (Vin) passes through the first MOSFET tube (Q1) and the inductor 112 to supply power to the voltage output terminal (Vout). When the second MOSFET tube (Q2) is turned on, the energy stored in the inductor 112 is passed through the second MOSFET tube (Q2) and the inductor 112 to continue the flow. Moreover, the first MOSFET tube (Q1) and the second MOSFET tube (Q2) cannot be turned on at the same time.

[0059] The above describes the circuit structure of the power path by taking the synchronous Buck circuit as an example. Those skilled in the art can appreciate that such description is only exemplary and is not intended to limit the protection scope of the embodiments of the present utility model.

[0060] Figure 3 FIG. 1 is an exemplary layout diagram of a power unit on a substrate in the related art. Figure 3 In the embodiment, a power unit 10 including four power channels is used for exemplary description. The power unit 10 includes a first power channel 11, a second power channel 12, a third power channel 13, and a fourth power channel 14. The first power channel 11, the second power channel 12, the third power channel 13, and the fourth power channel 14 are all directly mounted on the substrate 20. That is, the first power channel 11, the second power channel 12, the third power channel 13, and the fourth power channel 14 have respective planar mounting positions on the substrate.

[0061] However, considering the limited planar layout space on the substrate, this planar layout method of directly mounting each power channel on the substrate will occupy a large amount of substrate space, making it difficult to increase energy density and thus unable to continue to increase power consumption, thereby limiting the scope of application and performance.

[0062] In the embodiment of the utility model, each power channel is not directly installed on the substrate, but two power channels are arranged in a spatial stacking manner at each plane layout position of the substrate, thereby saving substrate space and improving energy density at the same substrate size.

[0063] The above disclosure details the technical defects existing in the prior art, the causes of the technical defects, and the thinking and analysis process of overcoming the technical defects. In fact, the cognition of the above technical defects is not common knowledge in the field, but a novel discovery made by the inventor in his research. In addition, the tracing of the causes of the technical defects and the thinking and analysis process of overcoming the technical defects are also the gradual analysis results of the inventor in the actual research process, and are not common knowledge in the field.

[0064] The utility model embodiment proposes a power unit. The power unit includes: 2N power paths; each power path in the 2N power paths is coupled in parallel between a voltage input terminal corresponding to the respective power path and a voltage output terminal corresponding to the respective power path, and is used to adjust the voltage of the direct current flowing from the voltage input terminal corresponding to the respective power path and provide the adjusted direct current to the voltage output terminal corresponding to the respective power path; wherein the voltage input terminal corresponding to the respective power path and the voltage output terminal corresponding to the respective power path are arranged on a first substrate, and N is a positive integer of at least 2; the 2N power paths are arranged in N arrangement positions on the first substrate in a spatially stacked manner, wherein two power paths are arranged in a spatially stacked manner at each arrangement position.

[0065] It can be seen that the implementation method of the utility model does not directly install each power channel on the substrate, but arranges two power channels in a spatial stacking manner at each arrangement position of the substrate, thereby saving substrate space and improving energy density at the same substrate size.

[0066] In one embodiment, N is equal to 2. Specifically: 2N power paths include a first power path, a second power path, a third power path, and a fourth power path; wherein: the first power path includes: a first power switch, arranged on the second substrate, coupled to a voltage input terminal corresponding to the first power path; a first inductor, arranged on the third substrate, connected in series between the first power switch and a voltage output terminal corresponding to the first power path; the second power path includes: a second power switch, arranged on the first substrate, coupled to a voltage input terminal corresponding to the second power path; a second inductor, arranged on the second power switch, connected in series between the second power switch and a voltage output terminal corresponding to the second power path; the third power path includes: a third power switch, arranged on the second substrate, coupled to a voltage input terminal corresponding to the third power path; The fourth power path includes: a fourth power switch arranged on the first substrate and coupled to the voltage input terminal corresponding to the fourth power path; a fourth inductor arranged on the fourth power switch and connected in series between the fourth power switch and the voltage output terminal corresponding to the fourth power path; wherein the second substrate, the third substrate and the first substrate are spatially stacked with the fourth substrate; the fourth substrate includes an on-board voltage input terminal and an on-board voltage output terminal corresponding to the respective power paths; the second substrate and the third substrate are electrically connected to the first substrate via conductive pillars; the first substrate is electrically connected to the fourth substrate via a ball grid array. The voltage input terminals corresponding to the respective power paths are electrically connected to the on-board voltage input terminals; the voltage output terminals corresponding to the respective power paths are electrically connected to the on-board voltage output terminals corresponding to the respective power paths.

[0067] It can be seen that the embodiment of the utility model also proposes a specific structure of a power unit including four power paths, which saves substrate space through a three-dimensional arrangement. Under the same substrate size, the energy density can be increased exponentially. Moreover, the power unit can be suitable for a variety of power supply environments with small space and high power consumption. The inductor in the power path also has a variety of packaging methods, which improves the packaging selectivity. In addition, the inductor itself is a good thermal conductive material, which is conducive to the thermal uniformity of the power unit.

[0068] Figure 4A FIG. 1 is a first schematic diagram of the arrangement structure of the power unit according to an embodiment of the present utility model. Figure 4A In the embodiment, the power unit 40 includes: a first power path, a second power path, a third power path and a fourth power path.

[0069] The first power path includes: a first power switch 41, arranged on the second substrate 31 and coupled to the voltage input terminal corresponding to the first power path; a first inductor 43, arranged on the third substrate 32 and connected in series between the first power switch 41 and the voltage output terminal corresponding to the first power path.

[0070] The second power path includes: a second power switch 47, arranged on the first substrate 33 and coupled to the voltage input terminal corresponding to the second power path; a second inductor 45, arranged on the second power switch 47 and connected in series between the second power switch 47 and the voltage output terminal corresponding to the second power path.

[0071] The third power path includes: a third power switch 42, arranged on the second substrate 31 and coupled to the voltage input terminal corresponding to the third power path; a third inductor 44, arranged on the third substrate 32 and connected in series between the third power switch 42 and the voltage output terminal corresponding to the third power path.

[0072] The fourth power path includes: a fourth power switch 48, arranged on the first substrate 33 and coupled to the voltage input terminal corresponding to the fourth power path; a fourth inductor 46, arranged on the fourth power switch 48 and connected in series between the fourth power switch 48 and the voltage output terminal corresponding to the fourth power path.

[0073] The second substrate 31, the third substrate 32 and the first substrate 33 are spatially stacked with the fourth substrate 30. Figure 4A As shown, extending upward from the upper surface of the fourth substrate 30, there are the first substrate 33, the third substrate 32 and the second substrate 31 in sequence. The second substrate 31 and the third substrate 32 are connected via conductive pillars ( Figure 4A The first substrate 33 is electrically connected to the fourth substrate 30 via a ball grid array.

[0074] The voltage input terminal corresponding to the first power path, the voltage input terminal corresponding to the second power path, the voltage input terminal corresponding to the third power path, and the voltage input terminal corresponding to the fourth power path are all arranged on the first substrate 33. Moreover, the voltage output terminal corresponding to the first power path, the voltage output terminal corresponding to the second power path, the voltage output terminal corresponding to the third power path, and the voltage output terminal corresponding to the fourth power path are also arranged on the first substrate 33.

[0075] An onboard voltage input terminal (Vin), an onboard voltage output terminal (Vout1) corresponding to the first power path, an onboard voltage output terminal (Vout2) corresponding to the second power path, an onboard voltage output terminal (Vout3) corresponding to the third power path, and an onboard voltage output terminal (Vout4) corresponding to the fourth power path are arranged on the fourth substrate 30. The voltage input terminal corresponding to the first power path, the voltage input terminal corresponding to the second power path, the voltage input terminal corresponding to the third power path, and the voltage input terminal corresponding to the fourth power path are respectively electrically connected to the onboard voltage input terminal (Vin), so that each power path can input high voltage direct current. Moreover, the voltage output terminal corresponding to the first power path is electrically connected to the onboard voltage output terminal (Vout1) corresponding to the first power path, the voltage output terminal corresponding to the second power path is electrically connected to the onboard voltage output terminal (Vout2) corresponding to the second power path, the voltage output terminal corresponding to the third power path is electrically connected to the onboard voltage output terminal (Vout3) corresponding to the third power path, and the voltage output terminal corresponding to the fourth power path is electrically connected to the onboard voltage output terminal (Vout4) corresponding to the fourth power path. Therefore, through each onboard voltage output terminal connected to the respective load, the low voltage direct current output by the respective power channel can be provided to the respective load, thereby powering the respective load.

[0076] exist Figure 4A In the embodiment, the first inductor 43, the second inductor 45, the third inductor 44 and the fourth inductor 46 are all independently packaged inductors.

[0077] During the use of the power unit 40, the first power switch 41 and the third power switch 42 located at the top layer are thermally connected to the heat sink. The power unit 40 can achieve heat dissipation through the heat sink and the bottom fourth substrate 30. The inductor itself contains heat-conducting metal materials such as iron and copper, which are good heat-conducting devices. Therefore, the power unit 40 including four inductors is also conducive to the uniformity of the heat of the power unit 40.

[0078] Figure 4B This is a second schematic diagram of the arrangement structure of the power unit according to an embodiment of the present utility model.

[0079] exist Figure 4B In the embodiment, the power unit 40 includes: a first power path, a second power path, a third power path and a fourth power path.

[0080] The first power path includes: a first power switch 41, arranged on the second substrate 31 and coupled to the voltage input terminal corresponding to the first power path; a first inductor 43, arranged on the third substrate 32 and connected in series between the first power switch 41 and the voltage output terminal corresponding to the first power path.

[0081] The second power path includes: a second power switch 47, arranged on the first substrate 33 and coupled to the voltage input terminal corresponding to the second power path; a second inductor 45, arranged on the second power switch 47 and connected in series between the second power switch 47 and the voltage output terminal corresponding to the second power path.

[0082] The third power path includes: a third power switch 42, arranged on the second substrate 31 and coupled to the voltage input terminal corresponding to the third power path; a third inductor 44, arranged on the third substrate 32 and connected in series between the third power switch 42 and the voltage output terminal corresponding to the third power path.

[0083] The fourth power path includes: a fourth power switch 48, arranged on the first substrate 33 and coupled to the voltage input terminal corresponding to the fourth power path; a fourth inductor 46, arranged on the fourth power switch 48 and connected in series between the fourth power switch 48 and the voltage output terminal corresponding to the fourth power path.

[0084] The second substrate 31, the third substrate 32 and the first substrate 33 are spatially stacked with the fourth substrate 30. Figure 4B As shown, extending upward from the upper surface of the fourth substrate 30, there are the first substrate 33, the third substrate 32 and the second substrate 31 in sequence. The second substrate 31 and the third substrate 32 are connected via conductive pillars ( Figure 4B The first substrate 33 is electrically connected to the fourth substrate 30 via a ball grid array.

[0085] The voltage input terminal corresponding to the first power path, the voltage input terminal corresponding to the second power path, the voltage input terminal corresponding to the third power path, and the voltage input terminal corresponding to the fourth power path are all arranged on the first substrate 33. Moreover, the voltage output terminal corresponding to the first power path, the voltage output terminal corresponding to the second power path, the voltage output terminal corresponding to the third power path, and the voltage output terminal corresponding to the fourth power path are also arranged on the first substrate 33.

[0086] An onboard voltage input terminal (Vin), an onboard voltage output terminal (Vout1) corresponding to the first power path, an onboard voltage output terminal (Vout2) corresponding to the second power path, an onboard voltage output terminal (Vout3) corresponding to the third power path, and an onboard voltage output terminal (Vout4) corresponding to the fourth power path are arranged on the fourth substrate 30. The voltage input terminal corresponding to the first power path, the voltage input terminal corresponding to the second power path, the voltage input terminal corresponding to the third power path, and the voltage input terminal corresponding to the fourth power path are respectively electrically connected to the onboard voltage input terminal (Vin), so that each power path can input high voltage direct current. Moreover, the voltage output terminal corresponding to the first power path is electrically connected to the onboard voltage output terminal (Vout1) corresponding to the first power path, the voltage output terminal corresponding to the second power path is electrically connected to the onboard voltage output terminal (Vout2) corresponding to the second power path, the voltage output terminal corresponding to the third power path is electrically connected to the onboard voltage output terminal (Vout3) corresponding to the third power path, and the voltage output terminal corresponding to the fourth power path is electrically connected to the onboard voltage output terminal (Vout4) corresponding to the fourth power path. Therefore, through each onboard voltage output terminal connected to the respective load, the low voltage direct current output by the respective power channel can be provided to the respective load, thereby powering the respective load.

[0087] exist Figure 4B In the embodiment, the first inductor 43 and the third inductor 44 are packaged into a first integrated inductor 50. The second inductor 45 and the fourth inductor 46 are packaged into a second integrated inductor 51. It can be seen that by packaging the four inductors into two integrated inductors, the packaging process of the inductors is reduced.

[0088] During the use of the power unit 40, the first power switch 41 and the third power switch 42 located at the top layer are thermally connected to the heat sink. The power unit 40 can achieve heat dissipation through the heat sink and the bottom fourth substrate 30. The inductor itself contains heat-conducting metal materials such as iron and copper, which are good heat-conducting devices. Therefore, the power unit 40 including four inductors is also conducive to the uniformity of the heat of the power unit 40.

[0089] Figure 4C This is a third schematic diagram of the arrangement structure of the power unit according to an embodiment of the present utility model.

[0090] exist Figure 4C In the embodiment, the power unit 40 includes: a first power path, a second power path, a third power path and a fourth power path.

[0091] The first power path includes: a first power switch 41, arranged on the second substrate 31 and coupled to the voltage input terminal corresponding to the first power path; a first inductor 43, arranged on the third substrate 32 and connected in series between the first power switch 41 and the voltage output terminal corresponding to the first power path.

[0092] The second power path includes: a second power switch 47, arranged on the first substrate 33 and coupled to the voltage input terminal corresponding to the second power path; a second inductor 45, arranged on the second power switch 47 and connected in series between the second power switch 47 and the voltage output terminal corresponding to the second power path.

[0093] The third power path includes: a third power switch 42, arranged on the second substrate 31 and coupled to the voltage input terminal corresponding to the third power path; a third inductor 44, arranged on the third substrate 32 and connected in series between the third power switch 42 and the voltage output terminal corresponding to the third power path.

[0094] The fourth power path includes: a fourth power switch 48, arranged on the first substrate 33 and coupled to the voltage input terminal corresponding to the fourth power path; a fourth inductor 46, arranged on the fourth power switch 48 and connected in series between the fourth power switch 48 and the voltage output terminal corresponding to the fourth power path.

[0095] The second substrate 31, the third substrate 32, the first substrate 33, and the fourth substrate 30 are spatially stacked. Figure 4C As shown, extending upward from the upper surface of the fourth substrate 30, there are the first substrate 33, the third substrate 32 and the second substrate 31 in sequence. The second substrate 31 and the third substrate 32 are connected via conductive pillars ( Figure 4C The first substrate 33 is electrically connected to the fourth substrate 30 via a ball grid array.

[0096] The voltage input terminal corresponding to the first power path, the voltage input terminal corresponding to the second power path, the voltage input terminal corresponding to the third power path, and the voltage input terminal corresponding to the fourth power path are all arranged on the first substrate 33. Moreover, the voltage output terminal corresponding to the first power path, the voltage output terminal corresponding to the second power path, the voltage output terminal corresponding to the third power path, and the voltage output terminal corresponding to the fourth power path are also arranged on the first substrate 33.

[0097] An onboard voltage input terminal (Vin), an onboard voltage output terminal (Vout1) corresponding to the first power path, an onboard voltage output terminal (Vout2) corresponding to the second power path, an onboard voltage output terminal (Vout3) corresponding to the third power path, and an onboard voltage output terminal (Vout4) corresponding to the fourth power path are arranged on the fourth substrate 30. The voltage input terminal corresponding to the first power path, the voltage input terminal corresponding to the second power path, the voltage input terminal corresponding to the third power path, and the voltage input terminal corresponding to the fourth power path are all electrically connected to the onboard voltage input terminal (Vin), so that each power path can input high voltage direct current. Moreover, the voltage output terminal corresponding to the first power path is electrically connected to the onboard voltage output terminal (Vout1) corresponding to the first power path, the voltage output terminal corresponding to the second power path is electrically connected to the onboard voltage output terminal (Vout2) corresponding to the second power path, the voltage output terminal corresponding to the third power path is electrically connected to the onboard voltage output terminal (Vout3) corresponding to the third power path, and the voltage output terminal corresponding to the fourth power path is electrically connected to the onboard voltage output terminal (Vout4) corresponding to the fourth power path. Therefore, the low voltage direct current output by each power channel can be provided to the respective load via each onboard voltage output terminal connected to the respective load.

[0098] exist Figure 4C In the embodiment of the present invention, the first inductor 43, the second inductor 45, the third inductor 44 and the fourth inductor 46 are packaged into a third integrated inductor 52. It can be seen that by packaging all four inductors into one integrated inductor, the packaging process of the inductors is significantly reduced.

[0099] During the use of the power unit 40, the first power switch 41 and the third power switch 42 located at the top layer are thermally connected to the heat sink. The power unit 40 can achieve heat dissipation through the heat sink and the bottom fourth substrate 30. The inductor itself contains heat-conducting metal materials such as iron and copper, which are good heat-conducting devices. Therefore, the power unit 40 including four inductors is also conducive to the uniformity of the heat of the power unit 40.

[0100] exist Figure 4C In the embodiment, the first inductor 43 and the third inductor 44 are arranged on the third substrate 32. In an optional embodiment, the third substrate 32 may be removed, the first inductor 43 may be arranged on the second inductor 45, and the third inductor 44 may be arranged on the fourth inductor 46.

[0101] Figure 4D FIG. 4 is a fourth schematic diagram of the arrangement structure of the power unit according to an embodiment of the present utility model. Figure 4C The arrangement shown, Figure 4DIn the illustrated arrangement structure, the third substrate 32 is removed, and the first inductor 43 is arranged on the second inductor 45 , and the third inductor 44 is arranged on the fourth inductor 46 . Figure 4D In the illustrated arrangement, all four inductors are packaged into one integrated inductor, and the third substrate 32 is removed, which significantly reduces the packaging process of the inductor.

[0102] The above is an exemplary description using N equal to 2, that is, the power unit includes 4 power paths. Those skilled in the art can appreciate that this description is only exemplary and is not intended to limit the protection scope of the embodiments of the present utility model.

[0103] The power unit of the embodiment of the utility model can be applied to a variety of power supply scenarios, especially suitable for power supply environments with small space and high power consumption. For example, it can be applied to power processor cores, memory and high-speed serial computer expansion bus (PCIE) devices, etc.

[0104] The following description is based on the example of power supply for a processor core. The embodiment of the utility model also proposes a power supply device for a processor core. The power supply device includes: 2N power paths; each power path in the 2N power paths is coupled in parallel between a voltage input terminal corresponding to the respective power path and a voltage output terminal corresponding to the respective power path, and is used to adjust the voltage of the direct current flowing from the voltage input terminal corresponding to the respective power path and provide the adjusted direct current to the voltage output terminal corresponding to the respective power path; wherein the voltage input terminal corresponding to the respective power path and the voltage output terminal corresponding to the respective power path are arranged on the first substrate, and N is a positive integer of at least 2; the voltage output terminal corresponding to the respective power path is electrically connected to the processor core corresponding to the respective power path; the 2N power paths are arranged in N arrangement positions on the first substrate in a spatially stacked manner, wherein 2 power paths are arranged in a spatially stacked manner at each arrangement position. The processor may include a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU) or a microcontroller unit (MCU), etc.

[0105] In one embodiment, N is equal to 2. In one embodiment, the 2N power paths include a first power path, a second power path, a third power path, and a fourth power path; wherein: the first power path includes: a first power switch, arranged on the second substrate, coupled to a voltage input terminal corresponding to the first power path; a first inductor, arranged on the third substrate, connected in series between the first power switch and a voltage output terminal corresponding to the first power path; the second power path includes: a second power switch, arranged on the first substrate, coupled to a voltage input terminal corresponding to the second power path; a second inductor, arranged on the second power switch, connected in series between the second power switch and a voltage output terminal corresponding to the second power path; the third power path includes: a third power switch, arranged on the second substrate, coupled to a voltage input terminal corresponding to the third power path; a third inductor, arranged on the third substrate, connected in series between the third power switch and the voltage output terminal corresponding to the second power path. switch and the voltage output terminal corresponding to the third power path; the fourth power path includes: a fourth power switch, arranged on the first substrate, coupled to the voltage input terminal corresponding to the fourth power path; a fourth inductor, arranged on the fourth power switch, and connected in series between the fourth power switch and the voltage output terminal corresponding to the fourth power path; wherein the second substrate, the third substrate and the first substrate are spatially stacked with the fourth substrate, and the fourth substrate includes an on-board voltage input terminal and an on-board voltage output terminal corresponding to the respective power paths; the second substrate and the third substrate are electrically connected to the first substrate via conductive columns; the first substrate is electrically connected to the fourth substrate via a ball grid array; wherein the voltage input terminals corresponding to the respective power paths are electrically connected to the on-board voltage input terminals; the voltage output terminals corresponding to the respective power paths are electrically connected to the on-board voltage output terminals corresponding to the respective power paths.

[0106] Based on the above description, the embodiment of the utility model also proposes a server. The server includes: 2N processor cores; a power board, the power board includes 2N power paths, an onboard voltage input terminal and 2N onboard voltage output terminals; each of the 2N power paths is coupled to the 2N processor cores in a one-to-one correspondence manner, and is used to power the corresponding processor core via the onboard voltage output terminal corresponding to the respective power path; each of the 2N power paths is coupled in parallel between the voltage input terminal corresponding to the respective power path and the voltage output terminal corresponding to the respective power path, and is used to adjust the voltage of the direct current flowing in from the voltage input terminal corresponding to the respective power path and to The adjusted direct current is provided to the voltage output terminal corresponding to the respective power path; wherein the voltage input terminal corresponding to the respective power path and the voltage output terminal corresponding to the respective power path are arranged on the first substrate, and N is a positive integer of at least 2; 2N power paths are arranged in N arrangement positions on the first substrate in a spatially stacked manner, wherein 2 power paths are arranged in a spatially stacked manner at each arrangement position; wherein the voltage input terminal corresponding to the respective power path is electrically connected to the onboard voltage input terminal; and the voltage output terminal corresponding to the respective power path is electrically connected to the onboard voltage output terminal corresponding to the respective power path. In one embodiment, the server is an artificial intelligence server.

[0107] It should be noted that not all modules in the above structural diagrams are necessary, and some steps or modules in the above description can be ignored according to actual needs. The execution order of each step is not fixed and can be adjusted as needed. The division of each module is only for the convenience of describing the functional division adopted. In actual implementation, a module can be implemented by multiple modules, and the functions of multiple modules can also be implemented by the same module. These modules can be located in the same device or in different devices.

[0108] The hardware modules in each embodiment can be implemented mechanically or electronically. For example, a hardware module may include a specially designed permanent circuit or logic device (such as a dedicated processor, such as an FPGA or ASIC) for performing a specific operation. The hardware module may also include a programmable logic device or circuit (such as a general-purpose processor or other programmable processor) temporarily configured by software to perform a specific operation. As for whether to implement the hardware module mechanically, or using a dedicated permanent circuit, or using a temporarily configured circuit (such as configured by software), it can be decided based on cost and time considerations.

[0109] In this article, "schematic" means "serving as an example, an example or an illustration", and any diagram or implementation method described as "schematic" in this article should not be interpreted as a more preferred or more advantageous technical solution. In order to make the drawings concise, each figure only schematically shows the parts related to the utility model, and does not represent its actual structure as a product. In addition, in order to make the drawings concise and easy to understand, in some figures, only one of the parts with the same structure or function is schematically drawn, or only one of them is marked. In this article, "one" does not mean that the number of the relevant parts of the utility model is limited to "only one", and "one" does not mean that the number of the relevant parts of the utility model is "more than one". In this article, "upper", "lower", "front", "back", "left", "right", "inside", "outside", etc. are only used to indicate the relative position relationship between the relevant parts, rather than to limit the absolute position of these relevant parts.

[0110] The above is only a preferred embodiment of the utility model, and is not intended to limit the protection scope of the utility model. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. A power unit, characterized in that: include: 2N power paths; Each of the 2N power paths is coupled in parallel between a voltage input terminal corresponding to the respective power path and a voltage output terminal corresponding to the respective power path, and is used to adjust the voltage of the direct current flowing from the voltage input terminal corresponding to the respective power path and provide the adjusted direct current to the voltage output terminal corresponding to the respective power path; wherein the voltage input terminal corresponding to the respective power path and the voltage output terminal corresponding to the respective power path are arranged on the first substrate, and N is a positive integer of at least 2; The 2N power paths are arranged in a spatially stacked manner at N arrangement positions on the first substrate, wherein two power paths are arranged in a spatially stacked manner at each arrangement position.

2. The power unit according to claim 1, characterized in that: The N is equal to 2.

3. The power unit according to claim 2, characterized in that: The 2N power paths include a first power path, a second power path, a third power path and a fourth power path; wherein: The first power path includes: a first power switch, arranged on the second substrate, coupled to a voltage input terminal corresponding to the first power path; a first inductor, arranged on the third substrate, connected in series between the first power switch and a voltage output terminal corresponding to the first power path; The second power path includes: a second power switch, arranged on the first substrate, coupled to a voltage input terminal corresponding to the second power path; a second inductor, arranged on the second power switch, and connected in series between the second power switch and a voltage output terminal corresponding to the second power path; The third power path includes: a third power switch, arranged on the second substrate, coupled to a voltage input terminal corresponding to the third power path; a third inductor, arranged on the third substrate, connected in series between the third power switch and a voltage output terminal corresponding to the third power path; The fourth power path includes: a fourth power switch, arranged on the first substrate and coupled to a voltage input terminal corresponding to the fourth power path; a fourth inductor, arranged on the fourth power switch and connected in series between the fourth power switch and a voltage output terminal corresponding to the fourth power path; The second substrate, the third substrate and the first substrate are spatially stacked with a fourth substrate, and the fourth substrate comprises an onboard voltage input terminal and an onboard voltage output terminal corresponding to respective power paths; The second substrate and the third substrate are electrically connected to the first substrate via conductive pillars; the first substrate is electrically connected to the fourth substrate via a ball grid array; The voltage input terminals corresponding to the respective power paths are electrically connected to the onboard voltage input terminals; and the voltage output terminals corresponding to the respective power paths are electrically connected to the onboard voltage output terminals corresponding to the respective power paths.

4. The power unit according to claim 3, characterized in that: The first inductor, the second inductor, the third inductor and the fourth inductor are independently packaged inductors.

5. The power unit according to claim 3, characterized in that: The first inductor and the third inductor are packaged as a first integrated inductor, and the second inductor and the fourth inductor are packaged as a second integrated inductor; or The first inductor, the second inductor, the third inductor and the fourth inductor are packaged into a third integrated inductor.

6. A power supply device for a processor core, characterized in that: include: 2N power paths; Each of the 2N power paths is coupled in parallel between a voltage input terminal corresponding to the respective power path and a voltage output terminal corresponding to the respective power path, and is used to adjust the voltage of the direct current flowing from the voltage input terminal corresponding to the respective power path and provide the adjusted direct current to the voltage output terminal corresponding to the respective power path; wherein the voltage input terminal corresponding to the respective power path and the voltage output terminal corresponding to the respective power path are arranged on the first substrate, and N is a positive integer of at least 2; The voltage output terminals corresponding to the respective power paths are electrically connected to the processor cores corresponding to the respective power paths; The 2N power paths are arranged in a spatially stacked manner at N arrangement positions on the first substrate, wherein two power paths are arranged in a spatially stacked manner at each arrangement position.

7. The power supply device for a processor core according to claim 6, characterized in that: The N is equal to 2.

8. The power supply device for a processor core according to claim 7, characterized in that: The 2N power paths include a first power path, a second power path, a third power path and a fourth power path; wherein: The first power path includes: a first power switch, arranged on the second substrate, coupled to a voltage input terminal corresponding to the first power path; a first inductor, arranged on the third substrate, connected in series between the first power switch and a voltage output terminal corresponding to the first power path; The second power path includes: a second power switch, arranged on the first substrate, coupled to a voltage input terminal corresponding to the second power path; a second inductor, arranged on the second power switch, and connected in series between the second power switch and a voltage output terminal corresponding to the second power path; The third power path includes: a third power switch, arranged on the second substrate, coupled to a voltage input terminal corresponding to the third power path; a third inductor, arranged on the third substrate, connected in series between the third power switch and a voltage output terminal corresponding to the third power path; The fourth power path includes: a fourth power switch, arranged on the first substrate and coupled to the voltage input terminal corresponding to the fourth power path; a fourth inductor, arranged on the fourth power switch and connected in series between the fourth power switch and the voltage output terminal corresponding to the fourth power path; The second substrate, the third substrate and the first substrate are spatially stacked with a fourth substrate, and the fourth substrate comprises an onboard voltage input terminal and an onboard voltage output terminal corresponding to respective power paths; The second substrate and the third substrate are electrically connected to the first substrate via conductive pillars; the first substrate is electrically connected to the fourth substrate via a ball grid array; The voltage input terminals corresponding to the respective power paths are electrically connected to the onboard voltage input terminals; and the voltage output terminals corresponding to the respective power paths are electrically connected to the onboard voltage output terminals corresponding to the respective power paths.

9. A server, characterized in that: include: 2N processor cores; A power board, the power board comprising 2N power paths, an onboard voltage input terminal and 2N onboard voltage output terminals; Each of the 2N power paths is coupled to the 2N processor cores in a one-to-one correspondence manner, and is used to power the corresponding processor core via an onboard voltage output terminal corresponding to the respective power path; Each of the 2N power paths is coupled in parallel between a voltage input terminal corresponding to the respective power path and a voltage output terminal corresponding to the respective power path, and is used to adjust the voltage of the direct current flowing in from the voltage input terminal corresponding to the respective power path and provide the adjusted direct current to the voltage output terminal corresponding to the respective power path; wherein the voltage input terminal corresponding to the respective power path and the voltage output terminal corresponding to the respective power path are arranged on the first substrate, and N is a positive integer of at least 2; the 2N power paths are arranged in N arrangement positions on the first substrate in a spatially stacked manner, wherein 2 power paths are arranged in a spatially stacked manner at each arrangement position; wherein the voltage input terminal corresponding to the respective power path is electrically connected to the on-board voltage input terminal; and the voltage output terminal corresponding to the respective power path is electrically connected to the on-board voltage output terminal corresponding to the respective power path.

10. The server according to claim 9, characterized in that The server is an artificial intelligence server.

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