DSP + FPGA architecture microsystem circuit of simplified discrete device

Abstract

The utility model relates to a DSP + FPGA architecture microsystem circuit of a simplified discrete device. The DSP + FPGA architecture microsystem circuit comprises a DSP bare core, an FPGA bare core, two DDR3 microassemblies, a DDR2 microassembly, a storage device bare core and 48 passive devices. Meanwhile, the bare core, the micro component and the discrete device comprising the memory bare core and the passive device are packaged and integrated on a 28-layer CCGA1512 packaging type ceramic tube shell in a heterogeneous manner; the FPGA bare core is hung on the DSP bare core through a PCIe interface, and data exchange is carried out between the FPGA bare core and the DSP bare core through a 4Lane PCIE 1.0 protocol; according to the micro-system circuit, the power supply integrity design is optimized based on power supply simulation, the external power supply voltage is raised through the real installation design, a power supply and a signal can meet chip application requirements without adding multiple passive power supply filter devices on a ceramic tube shell, and meanwhile design and manufacturing of a micro-system are simplified.

Description

Technical Field

[0001] The utility model relates to the technical field of microcircuits, in particular to a DSP+FPGA architecture microsystem circuit with simplified discrete devices. Background Art

[0002] With the rapid development of electronic technology, there have been great breakthroughs in integrated circuits and packaging processes, and microsystem (System in Package) technology has become one of the important ways to integrate systems. Based on system-level packaging technology, bare chips, microcomponents and passive devices can be interconnected on a ceramic shell and integrated into the same package, achieving the goals of high system integration, miniaturization, low power consumption, high reliability and high efficiency.

[0003] For an electronic system, the number of passive devices usually accounts for more than 80% of the number of BOM devices, and the area occupied by the board is almost as high as 70%. How to reduce the packaging volume of these devices is one of the key tasks in the miniaturization of electronic systems. Integrated passive devices (IPD), as the name suggests, integrate passive devices together. The yield rate of passive devices made into IPD is not high and the price is high. Packaging IPD into microsystem circuits will increase the production cost of the microsystem to a certain extent and reduce the yield rate of the microsystem. The discrete form of passive devices has low functional density and inconsistent physical sizes. Packaging them separately into microsystem circuits will affect the physical size of the microsystem.

[0004] The core voltage and current of the bare core are relatively large, and the power integrity requirements are high. The number of nuclear power filter capacitors is large. The functional density of passive devices is low, and the yield of IPD packaging is low, which will restrict the design, manufacture and application of microsystems. Utility Model Content

[0005] In order to solve the above technical problems, the utility model provides a DSP+FPGA architecture microsystem circuit with simplified discrete devices, including 1 DSP bare core, 1 FPGA bare core, 2 DDR3 microcomponents, 1 DDR2 microcomponent, 1 memory device bare core and 48 passive devices; at the same time, the above bare core, microcomponents and discrete devices including memory device bare core and passive devices are heterogeneously packaged and integrated on a ceramic tube shell in the form of a 28-layer CCGA1512 package;

[0006] The FPGA bare core is hung on the DSP bare core through the PCIe interface, and the two exchange data through the 4LanePCIE 1.0 protocol; and the DSP bare core is integrated with two DDR3 memory controllers, each memory controller corresponds to a DDR3 memory interface with a 64-bit data width, that is, the DSP bare core is connected to the DDR3 microcomponent through the DDR3 controller;

[0007] The FPGA bare core has a DDR2 memory controller externally developed through MIG, and is connected to the DDR2 microcomponents, while the FPGA bare core is connected to the memory device bare core through parallel communication;

[0008] At the same time, the DSP bare core lead-out is equipped with 2 groups of RapidIO interfaces, EMIF interface, 2 groups of UART interfaces, 2 groups of SPI interfaces, 2 groups of I2C interfaces, 2 groups of CAN interfaces, one group of LPC interface, 20 GPIOs and 2 groups of SGMII interfaces; the FPGA bare core lead-out is equipped with some IO ports and 3 groups of MGT for high-speed data communication.

[0009] In one embodiment of the utility model, the DSP bare core adopts the Huarui No. 2 eight-core DSP chip HR2080, wherein the single-core main frequency of HRDSP2080 is 1G, the processing core is 8 cores, and the peak computing power: fixed point is greater than 64GMAC, floating point is 400GFLOPS; the FPGA bare core adopts the chip JYXLX350, the programmable device JYXLX350 has an equivalent logic gate count of 35 million gates, and is aimed at information processing and communication applications. It internally supports dual-channel analog-to-digital converters and supports communication applications that require high performance, low cost, and multi-functions.

[0010] In one embodiment of the present invention, the DDR3 memory interface supports ECC check of "64-bit data + 8-bit check code", and the stable data transmission rate can reach 800Mbps.

[0011] In one embodiment of the present invention, each DDR3 controller is connected to a corresponding DDR3 micro-component with a capacity of 5GB and a data bit width of 64 bits.

[0012] The above technical solution of the utility model has the following advantages over the prior art: the microsystem circuit described in the utility model optimizes the power integrity design based on power simulation, and then raises the external power supply voltage through the actual installation design, and does not need to add more passive power filter components on the ceramic tube shell, so that the power supply and signal can meet the chip application requirements, ensuring the normal operation of the microsystem while simplifying the design and manufacture of the microsystem. It bypasses the risk of low yield of integrated IPD in the existing microsystem design, and improves the integration of the microsystem and the yield of microsystem manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to make the content of the utility model more clearly understood, the utility model is further described in detail below based on specific embodiments of the utility model in combination with the accompanying drawings.

[0014] Figure 1It is a system block diagram of the principle prototype of the DSP+FPGA architecture microsystem in the utility model;

[0015] Figure 2 It is a schematic diagram of the interconnection between the components inside the microsystem of the utility model;

[0016] Figure 3a It is the temperature cloud diagram of each chip under the 25°C working condition of the utility model;

[0017] Figure 3b It is the temperature distribution cloud diagram of the substrate described in the utility model;

[0018] Figure 3c It is the temperature distribution cloud diagram of the Z-section microsystem of the utility model;

[0019] Figure 3d is the temperature value of each chip described in the utility model;

[0020] Figure 4 It is a schematic diagram of the layout of the microsystem in the utility model;

[0021] Figure 5 It is a screenshot of the simulation results of the ceramic tube shell of the micro system in this utility model. DETAILED DESCRIPTION

[0022] This embodiment provides a DSP+FPGA architecture microsystem circuit that streamlines discrete devices. Before the system-level design of the microsystem is carried out, the function and performance need to be verified through a principle prototype. The circuit is designed according to the functional requirements of the microsystem to ensure that when designing the microsystem schematic, it can be reused except for the power supply circuit. After the shell design is completed, it is necessary to perform signal integrity simulation and power integrity simulation, thermal simulation, stress simulation, thermal stress simulation, etc., and adjust the layout layout and wiring according to the simulation results, and perform iterative optimization of the simulation design. After the optimization is completed, the shell processing and packaging are started, and finally the actual installation test board is designed to complete the microsystem device testing and application.

[0023] The prototype verification principle prototype system block diagram corresponding to the utility model is as follows Figure 1 As shown;

[0024] In the microsystem with DSP+FPGA architecture, the DSP chip HR2080 is the core, and the FPGA chip JYXLX350 is connected to the DSP through the PCIe interface. At the same time, the microsystem integrates 2 DDR3 microcomponents, 1 DDR2 microcomponent, 1 PROM bare core and several passive devices. The interconnection relationship of each component on the microsystem ceramic tube shell is as follows Figure 2 As shown;

[0025] The microsystem is simulated. When the ambient temperature is 25°C, the overall temperature distribution cloud diagram under natural heat dissipation conditions is as follows: Figure 4 As shown by Figure 3a , 3b , 3c, and 3d, we can see that the heat generation area is concentrated in the DSP / HR2080 chip area, where the highest chip temperature is 325.90°C, and the main heat dissipation path is conduction through the cover and substrate, which is 175°C higher than the failure temperature of the Si chip.

[0026] The main reason is that the maximum current of the 0.9V DSP core power is as high as 30A, which requires high power stability, and inevitably requires the addition of many filter capacitors. According to statistics, there are 88 0.9V filter capacitors on the prototype.

[0027] The microsystem adopts a 54mm×46mm×8.65mm CCGA ceramic package. The overall model contains 6 components and several resistors and capacitors. The assembly form is FC (bottom-fill). The overall model parameters and geometric dimensions are shown in the following table.

[0028]

[0029] There is not enough space on the ceramic tube shell to accommodate 88 filter capacitors, so the power plane and the number of capacitors are optimized through power simulation. Before the capacitor reduction, the number of filter capacitors for the DSP core power 0.9V was 88. After the reduction, only 3 were retained. The final microsystem product layout is as follows Figure 4 As shown;

[0030] The power supplies of the microsystem design ceramic tube shell are simulated. The DC voltage drop of the DSP core power supply VDD_0V9_DSPVDD is 0.0257V, which exceeds the required fluctuation range of 3%. The DC voltage drops of other power supplies can meet the requirements, such as Figure 5 As shown. The risk needs to be further verified on the prototype. Through the DC voltage drop simulation of all power planes, it can be found that the DC voltage drop of FT_VDD_CORE, MGTAVCC, MGTAVTT, VCCINT, and VDD_DDR power supplies cannot meet the requirements, such as Figure 5 Metal material: tungsten, conductivity: 6.67x10 6 S / m.

[0031] According to the DSP HR2080 chip manual, the minimum operating voltage of VDD_0V9_DSPVDD is 0.81V and the maximum is 0.99V. VDD_0V9_DSPVDD is powered by the DCDC power chip. Adjust the DCDC output voltage and confirm that the voltage of VDD_0V9_DSPVDD at the DSP end of the prototype can be as low as 0.845V and as high as 0.939V, and it can work normally.

[0032] The DSP+FPGA architecture microsystem was installed on the microsystem actual test board for testing and application. The external DCDC power supply circuit was adjusted to make the DSP core power VDD_0V9_DSPVDD voltage 0.926V. The 0.0257V DC voltage drop caused by transmission attenuation on the ceramic tube shell was removed, and the power supply voltage at the foot of the microsystem DSP core power pin was 0.9V, which met the rated working voltage requirements of the DSP device. The functional performance of the actual test microsystem was consistent with the principle prototype.

[0033] The overall package of the microsystem circuit described in this embodiment is shown in the figure below: it mainly includes 1 DSP bare core, 1 FPGA bare core, 2 DDR3 microcomponents, 1 DDR2 microcomponent, 1 memory device bare core and 48 passive devices. The above bare cores, microcomponents and discrete devices are heterogeneously packaged and integrated on a ceramic tube shell in the form of a 28-layer CCGA1512 package.

[0034] The data flow is as follows: In the microsystem of DSP+FPGA architecture, the core is the Huarui No. 2 eight-core DSP chip HR2080, and the FPGA chip JYXLX350 is hung on the DSP through the PCIe interface. The HRDSP2080 single-core main frequency is 1G, the processing core is 8 cores, the peak computing power: fixed point is greater than 64GMAC, floating point is 400GFLOPS, and the programmable device JYXLX350 has an equivalent logic gate count of 35 million gates. For information processing and communication applications, it supports dual-channel analog-to-digital converters internally, and supports communication applications that require high performance, low cost, and multi-functions. At the same time, the microsystem integrates 2 DDR3 microcomponents, 1 DDR2 microcomponent, and 1 PROM bare core.

[0035] DSP bare core HR2080 integrates two DDR3 memory controllers, each of which corresponds to a DDR3 memory interface with a data width of 64 bits. The interface supports ECC check of "64-bit data + 8-bit check code" (can correct single errors and detect double errors), and the stable data transmission rate can reach 800Mbps. Each DDR3 controller is connected to a DDR3 microcomponent with a capacity of 5GB and a data width of 64 bits. After the DSP is powered on and reset, the corresponding registers in the DSP memory controller are configured according to the type of DDR3 SDRAM memory used in the microsystem, and then the registers in the DDR3 PHY are configured to start the DDR3 memory interface for initialization. After the memory interface of the DSP processor is initialized, the memory interface link training is required. Link training is the process of calibrating the data bus of the memory interface with the corresponding differential data selection signal (DQS) in units of 8 bits and aligning the bytes bit by bit. Link training can improve the integrity of the output signal of the memory interface and improve the anti-interference ability. Afterwards, the DDR3 microcomponent is used to store temporary data and DSP instructions, responsible for data exchange between system peripherals and DSP, improving data processing efficiency, meeting the needs of program operation and multi-tasking, and supporting the normal operation of the DSP system.

[0036] FPGA has built a DDR2 memory controller through MIG, which is equipped with a customized DDR2 micro-component with a capacity of 4Gb, a data width of 32 bits, and a running speed of up to 800Mbps to support complex and high-speed applications.

[0037] PROM provides a persistent and reliable configuration information storage and loading mechanism for FPGA. When the FPGA loses power, the internal information will disappear, but PROM can provide the necessary configuration information when the FPGA is powered on again, so that the FPGA can be restored to the functional chip required by the user.

[0038] Data is exchanged between DSP and FPGA via the 4Lane PCIE 1.0 protocol, with a theoretical rate of up to 1.0GB / s.

[0039] The DSP bare core leads to 2 groups of Rapid IO interfaces, EMIF interface, 2 groups of UART interfaces, 2 groups of SPI interfaces, 2 groups of I2C interfaces, 2 groups of CAN interfaces, one group of LPC interface, 20 GPIO and 2 groups of SGMII interfaces. The FPGA bare core leads to some IO ports and 3 groups of MGT for high-speed data communication.

[0040] The DSP+FPGA architecture microsystem of the utility model uses simulation to simplify the filter capacitor, improves the utilization rate of the microsystem ceramic tube shell, reduces the design cost of the microsystem and the requirements for the processing technology, the technical difficulty is relatively controllable, and the yield rate of the microsystem is improved. The realized microsystem has the characteristics of many interconnection layers, high integration density, strong mechanical stress, stable shape, etc., and is particularly suitable for aerospace and military electronic devices.

[0041] This new technology uses power integrity simulation innovatively to simplify the passive components required on the microsystem shell. By simulating and raising the application power supply technology, the cost of developing IPD is saved and the efficiency and yield of microsystem design are improved. The use of simulation technology and voltage raising to simplify the passive components required for the microsystem is original in the field of microsystem design, manufacturing and application.

[0042] Obviously, the above embodiments are merely examples for the purpose of clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the scope of protection of the invention of the utility model.

Claims

1. A DSP+FPGA architecture microsystem circuit with simplified discrete devices, characterized in that: It includes 1 DSP bare core, 1 FPGA bare core, 2 DDR3 microcomponents, 1 DDR2 microcomponent, 1 memory device bare core and 48 passive devices; at the same time, the above bare cores, microcomponents and discrete devices including memory device bare core and passive devices are heterogeneously packaged and integrated on a ceramic tube shell in the form of a 28-layer CCGA1512 package; The FPGA bare core is hung on the DSP bare core through the PCIe interface, and the two exchange data through the 4Lane PCIE 1.0 protocol; and the DSP bare core is integrated with two DDR3 memory controllers, each memory controller corresponds to a DDR3 memory interface with a 64-bit data width, that is, the DSP bare core is connected to the DDR3 microcomponent through the DDR3 controller; The FPGA bare core has a DDR2 memory controller externally developed through MIG, and is connected to the DDR2 microcomponents, while the FPGA bare core is connected to the memory device bare core through parallel communication; At the same time, the DSP bare core lead-out is equipped with 2 groups of RapidIO interfaces, EMIF interface, 2 groups of UART interfaces, 2 groups of SPI interfaces, 2 groups of I2C interfaces, 2 groups of CAN interfaces, one group of LPC interface, 20 GPIOs and 2 groups of SGMII interfaces; the FPGA bare core lead-out is equipped with some IO ports and 3 groups of MGT for high-speed data communication.

2. The microsystem circuit according to claim 1, characterized in that: The DSP bare core uses the Huarui No. 2 eight-core DSP chip HR2080, of which the single-core main frequency of HRDSP2080 is 1G, the processing core is 8 cores, and the peak computing power: fixed-point is greater than 64GMAC, floating-point is 400GFLOPS; the FPGA bare core uses the chip JYXLX350, and the programmable device JYXLX350 has an equivalent logic gate count of 35 million gates.

3. The microsystem circuit according to claim 1, characterized in that: The DDR3 memory interface supports "64-bit data + 8-bit check code" ECC check, and the stable data transmission rate can reach 800Mbps.

4. The microsystem circuit according to claim 1, characterized in that: Each DDR3 controller is connected to a DDR3 micro-component with a capacity of 5GB and a data bit width of 64 bits.

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