Overcurrent protection circuit and power switch using same

Abstract

The utility model relates to the field of switching power supply circuits, and discloses an over-current protection circuit and a power supply switch using the same, which solve the problems in the background technology and are formed by sequentially connecting a reference voltage module, a sampling circuit module, a comparator, a triode Q1, a current limiting module and a delayer, the reference voltage module and the sampling circuit module output signals after comparison processing through the comparator, and control the conduction state of the triode Q1, the purpose of current limiting can be achieved by lowering the grid voltage of the output power tube, the triode Q1 is added to assist overcurrent, and elements in a chip are protected from being damaged by large current.

Description

Technical Field

[0001] The utility model belongs to the field of switch power supply circuits, in particular to an overcurrent protection circuit and a power switch using the same. Background Art

[0002] As a power management chip, the power switch is an intelligent power control system that includes some protection circuits. It is a perfect solution to ensure that the various modules of the system can cooperate with each other to achieve performance indicators such as reducing system power consumption and improving system life. The utility model proposes an overcurrent protection circuit that can protect the internal components of the power switch chip and the safety of electronic equipment connected to the power switch chip under large load current conditions.

[0003] Traditional overcurrent protection circuits such as Figure 3 As described above, the operational amplifier AMP2 is used to clamp the source voltages of M1 and M2 at an equal potential. When the load current increases, the feedback loop is used to map the change of I2 on I1, thereby reducing the gate voltages of M1 and M2, and then reducing the drain voltages of M1 and M2 to achieve the current limiting function. However, when the load is short-circuited, the load current will increase rapidly, exceeding the current limiting threshold of the traditional overcurrent protection, and the overcurrent protection of the chip cannot be achieved. Therefore, how to ensure that the overcurrent protection circuit can complete the current limiting function under any conditions and improve the reliability of the power switch chip has become a problem to be solved. To this end, we propose an overcurrent protection circuit and a power switch using the same. Utility Model Content

[0004] The purpose of the utility model is to provide an overcurrent protection circuit and a power switch using the same, so as to solve the shortcomings of the traditional overcurrent circuit, which has a single function and a complex circuit, and effectively enable the system to immediately shut down the power switch system under different overcurrent conditions and send an alarm signal to the control center of the connected equipment, so as to ensure the safety of the internal circuit of the power switch.

[0005] To achieve the above-mentioned purpose, the technical solution of the utility model is: an overcurrent protection circuit, comprising a first end OUT, a second end OCP, and a reference voltage module, a sampling circuit module, a comparator, a transistor Q1, a current limiting structure, a sampling resistor R and a delay device connected in sequence; the reference voltage module is connected to the positive output port of the comparator, the sampling circuit module is connected to the reverse end of the comparator, and the output end of the comparator is connected to the emitter of the transistor Q1; the collector of the transistor Q1 is connected to its own base and connected to the current limiting structure; one end of the resistor R is connected to the port OUT and serves as a pull-up resistor to sample OUT, and the other end is connected to the current limiting structure; the output end of the current limiting structure is connected to the delay device.

[0006] When the power switch system works normally, the comparator forward input voltage is higher than the reverse input voltage, and the transistor Q1 is a two-port connection mode, which is analogous to a diode device. Due to the unidirectional conductive characteristics of the diode, Q1 is not turned on at this time, and the overcurrent protection circuit is not started; when the load gradually decreases or the load is short-circuited, the output voltage of the sampling circuit increases, causing the comparator output to change, and the voltage difference between the upper and lower circuits of Q1 exceeds its threshold voltage, Q1 is turned on, and the circuit system starts to perform overcurrent protection. In the case of overcurrent, the current limiting structure shuts off the output power tube and reduces the load current. After the overcurrent state exceeds the delay time set by the delayer, the power switch system issues a warning to the equipment control center.

[0007] The utility model also proposes a current limiting structure, including a PMOS tube PM1, NMOS tubes NM1, NM2, NM3, NM4, and a triode Q2; the gate and source of the PMOS tube PM1 are connected in series and connected to one end of the sampling resistor R, and the drain is connected to the drain of the NMOS tube NM1; the gate of the NMOS tube NM1 and the gate of the NMOS tube NM2 are connected to the internal bias signal of the chip to provide a bias current for the entire current limiting structure, and the source is connected to the ground of the circuit system; the source of the NMOS tube NM2 is connected to the ground of the circuit system; The circuit system is connected to the ground, and the drain is connected to the emitter of the transistor Q2; the base and collector of the transistor Q2 are connected in series and then connected to the power supply of the circuit system; the gate of the NMOS tube NM3 is connected to the drain of the PMOS tube PM1, the source is connected to the source of the NMOS tube NM4 and the collector of the transistor Q1, and the drain is connected to the drain of the NMOS tube NM4 and the gate of the output power tube inside the chip, so that the voltage value of the OUT output can be adjusted; the gate of the NMOS tube NM4 is connected to the emitter of the transistor Q2.

[0008] In the current limiting module, no matter which situation causes the system to be in an overcurrent state, the voltage value of the OUT port will change. The sampling resistor R reflects the change of the OUT port voltage signal on the gate of the NMOS tube NM3; after the transistor Q1 is turned on, the source voltage of the NMOS tubes NM3 and NM4 will be pulled down, causing NM4 to be turned on, and the drain voltage of NM3 and NM4 will be reduced. The drain voltage is externally connected to the gate of the power tube, so as to achieve the purpose of reducing the load current and realize the accurate and fast overcurrent protection function.

[0009] In the utility model, the sampling circuit and the internal reference voltage generating module, an overcurrent protection circuit and a delay device are all integrated in the same circuit, reducing external ports, and the power switch chip has a high degree of integration.

[0010] Compared with the prior art, the beneficial effects of the utility model are:

[0011] The utility model can capture the change of the voltage of the output port OUT of the power switch through the sampling resistor in the circuit, and reflect the voltage change in the transistor state parameter. If the output current is too large, it will immediately send out the shutdown signal OCP, turn off the power switch system and limit the current until the system is relieved of the overcurrent state, and the power switch chip can resume normal operation. When the power switch system is turned off, the delay device starts timing, and sends a warning to the equipment control center after the delay period is reached. This technology ensures the reliability of the power switch system, guarantees the safety of the connected electronic equipment, and has good use value. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0013] Figure 1 This is a circuit connection diagram of the overcurrent protection circuit of the utility model;

[0014] Figure 2 This is a schematic diagram of the circuit structure of the current limiting structure of the overcurrent protection circuit of the utility model;

[0015] Figure 3 This is a schematic diagram of a traditional overcurrent protection circuit. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, rather than all of the embodiments; based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the utility model.

[0017] The utility model provides an overcurrent protection circuit and a power switch using the same, which are connected together in sequence by a reference voltage module, a delay device, a sampling circuit, a sampling resistor R, a comparator, a transistor Q1 and a current limiting module.

[0018] For details, see Figure 1 , Figure 1: is a structural schematic diagram of the overcurrent protection circuit of this example. In the figure, a reference voltage module, a sampling circuit module, a comparator, a transistor Q1, a current limiting structure, a sampling resistor R and a delay device are electrically connected together. The reference voltage module is connected to the positive output port of the comparator, the sampling circuit module is connected to the reverse input end of the comparator, and the output end of the comparator is connected to the emitter of the transistor Q1; the collector of the transistor Q1 is connected to its own base and connected to the current limiting structure; one end of the sampling resistor R is connected to the OUT port and serves as a pull-up resistor to sample OUT, and the other end is connected to the current limiting structure; the output end of the current limiting structure is connected to the delay device.

[0019] The working principle of the overcurrent protection circuit is as follows:

[0020] The voltage VSNS obtained by the sampling circuit is placed at the reverse input end of the comparator and compared with the output signal VREF of the reference voltage module to generate an output control signal. The control signal and the current limiting structure together determine the conduction state of the two-port connection form Q1. When the power switch is working normally, VREF>VSNS, the comparator outputs a high level, and due to the unidirectional conductive characteristics, Q1 is not turned on, and the overcurrent protection circuit is not started. Under the condition of gradually reducing the load or short-circuiting the load, the sampling circuit is affected, so VSNS>VREF, the comparator outputs a low level, the voltage difference between the upper and lower circuits of Q1 exceeds its threshold voltage, Q1 is turned on, and the power switch chip starts to perform overcurrent protection. In the overcurrent state, the current limiting structure turns off the output power tube to reduce the load current. After the overcurrent state exceeds the delay time set by the delayer, the power switch system issues a warning to the device control center. Therefore, the utility model can not only turn off the power tube in time to achieve overcurrent protection, but also avoid false triggering caused by various interferences and erroneously alarm the device control center.

[0021] When the power switch chip is working normally, the load current I OUT Equal to V OUT Divided by the load resistance, the system will be in an overcurrent state when the load resistance decreases and the load is short-circuited. The utility model can be applied to the situation where the power switch system is in an overcurrent state due to the reduction of the load resistance, and can also be applied to the overcurrent situation caused by the load short circuit.

[0022] In order to allow the general technical personnel to better understand the present invention, the working principle of the present invention is further described below in conjunction with the circuit.

[0023] See also Figure 2A current limiting module circuit used in an overcurrent protection current includes a PMOS tube PM1, NMOS tubes NM1, NM2, NM3, NM4, and a triode Q2; the gate of the PMOS tube PM1 is connected in series with its own source and connected to the other end of a sampling resistor R, and the drain is connected to the drain of the NMOS tube NM1; the gate of the NMOS tube NM1 and the gate of the NMOS tube NM2 are connected to a chip internal bias signal to provide a bias current for the entire current limiting structure, and the source is connected to the ground of the circuit system; the source of the NMOS tube NM2 is connected to the ground of the circuit system The ground of the circuit system is connected to the drain of the transistor Q2; the base of the transistor Q2 is connected to its own collector and then to the power supply VDD of the circuit system; the gate of the NMOS tube NM3 is connected to the drain of the PMOS tube PM1, the source is connected to the source of the NMOS tube NM4 and the collector of the transistor Q1 outside the current limiting structure, the drain is connected to the drain of the NMOS tube NM4 and the gate of the output power tube inside the chip, and the output voltage value of the OUT port can be adjusted; the gate of the NMOS tube NM4 is connected to the emitter of the transistor Q2.

[0024] The working principle of the current limiting structure is as follows:

[0025] When the circuit system is in an overcurrent state, the voltage at the OUT port decreases, and the amplitude of the corresponding sampling signal connected to the current limiting structure also decreases. The gate voltage decreases, causing the NM3 source voltage to decrease. The NM4 source and the NM3 source are connected to the Q1 collector, so the NM4 source voltage also decreases, and current flows through the transistor Q1.

[0026] I E,Q1 =I S,NM3 +I S,NM4 (1)

[0027] Among them I S,NM3 and I S,NM4 The value of I changes with the load current in the overcurrent state. The larger the load current, the larger the S,NM3 The smaller, I S,NM4 The larger the value, the greater the voltage. The sum of the two always remains the same. As NM4 is turned on, its drain voltage is pulled down, and the drains of NM3 and NM4 in the power switch chip are connected to the gate of the output power tube. As the gate voltage of the output power tube decreases, the OUT output voltage gradually stabilizes, and the load current gradually decreases until the system is out of the overcurrent state. At the same time, the OCP signal, in conjunction with the internal enable structure of the chip, turns off the chip. And flows to the internal delay device of the chip. The delay device sets the delay period T = 9ms, which means that when the circuit system is in the overcurrent state for more than 9ms delay period, the delay device will issue a warning to the equipment control center. On the contrary, if the circuit system is out of the overcurrent state within 9ms, the delay device will give up the current timing and reset the delay device until the next overcurrent situation occurs before restarting the timing.

[0028] In the utility model, the sampling circuit, the internal reference voltage generating module, an overcurrent protection circuit and a delay device are all integrated in the same circuit, thus reducing external ports, and the power switch chip has a high degree of integration.

[0029] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0030] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An overcurrent protection circuit and a power switch using the same, characterized in that: It includes a first terminal OUT and a second terminal OCP, and includes a reference voltage module, a sampling circuit module, a comparator, a first transistor Q1, a current limiting structure, a sampling resistor R and a delay device connected in sequence; when the power switch system works normally, the comparator forward input voltage is higher than the reverse input voltage, the first transistor Q1 is not turned on, and the overcurrent protection circuit is not started; when the load gradually decreases and the load is short-circuited, the voltage value of the first port OUT changes, the output voltage of the sampling circuit increases, resulting in a change in the comparator output, the voltage difference between the upper and lower circuits of the first transistor Q1 exceeds its threshold voltage, the first transistor Q1 is turned on, and the circuit system starts to perform overcurrent protection; The reference voltage module is connected to the positive output port of the comparator, the sampling circuit module is connected to the reverse end of the comparator, the reverse input end of the comparator is connected to the sampling circuit, and the output end is connected to the emitter of the first transistor Q1; The collector of the first transistor Q1 is connected in series with its base to a current limiting structure; One end of the sampling resistor R is connected to the first port OUT and serves as a pull-up resistor to sample OUT, and the other end is connected to a current limiting structure; The output end of the current limiting structure is connected to the delay device.

2. The overcurrent protection circuit and the power switch using the same according to claim 1, characterized in that: The current limiting structure includes a PMOS tube PM1, NMOS tubes NM1, NM2, NM3, NM4, and a second triode Q2; The gate of the PMOS tube PM1 is connected to its own source and the other end of the sampling resistor R, and the drain is connected to the drain of the NMOS tube NM1; the gate of the NMOS tube NM1 and the gate of the NMOS tube NM2 are commonly connected to the chip internal bias signal to provide bias current for the entire current limiting structure, and the source is connected to the ground of the circuit system; the source of the NMOS tube NM2 is connected to the ground of the circuit system, and the drain is connected to the emitter of the second transistor Q2; the base of the second transistor Q2 is connected to its own collector and the power supply of the circuit system; the gate of the NMOS tube NM3 is connected to the drain of the PMOS tube PM1, the source is connected to the source of the NMOS tube NM4 and the collector of the first transistor Q1, and the drain is connected to the drain of the NMOS tube NM4 and the gate of the output power tube inside the chip, so that the voltage value of the first end OUT can be adjusted; the gate of the NMOS tube NM4 is connected to the emitter of the second transistor Q2.

3. An overcurrent protection circuit and a power switch using the same according to claim 1 or 2, characterized in that: The current limiting structure also includes a power supply for providing a power supply voltage and an OCP interface for connecting a delay device, and a circuit system power supply of the current limiting structure is connected to the power supply.

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