Electrostatic self-protection circuit suitable for integrated power tube
By designing the driving circuit in the electrostatic self-protection circuit of the integrated power tube, turning on the power tube and clamping the gate voltage, the problem that the integrated power tube cannot effectively release the ESD current during the ESD event is solved, and the normal opening of the power tube and the release of the ESD current are achieved.
Patent Information
- Application Number
- CN202421218443.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-30
- Publication Date
- 2025-04-18
- Estimated Expiration
- 2034-05-30
AI Technical Summary
The existing integrated power tube cannot effectively release ESD current during ESD events, resulting in possible damage.
An electrostatic self-protection circuit is designed, which is connected to the gate of the power tube through a driving circuit, and the power tube is turned on and static discharge is performed through its conduction path, while clamping the gate voltage to prevent the gate oxide layer from breaking down.
Provide higher gate voltage when the ESD event arrives, ensuring that the power tube is turned on, and the ESD current is normally discharged through the channel to avoid damage.
Smart Images
Figure CN222776523U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of integrated circuits, and in particular relates to an electrostatic self-protection circuit suitable for integrated power tubes. Background Art
[0002] As the requirements for miniaturization and lightweight of electronic products become higher and higher, the integration of chips is also getting higher and higher. Among them, the switching power supply chip has also changed from only integrating the controller in the past to integrating the controller, driver and power devices on the same chip. Due to the difficulty of integrating inductive components, the current integrated power tube still needs to have a port leading out of the chip to connect to the external inductive component, which means that the electrostatic protection of the integrated power tube needs to be considered.
[0003] There are currently two directions for electrostatic protection of integrated power tubes. One is to use ESD protection devices such as diodes and transistors in parallel with the power tube, and use the ESD protection devices to discharge the ESD current. The other is to use the power tube parasitic devices or channels to discharge the ESD current by themselves, that is, self-protection.
[0004] Self-protection mechanisms of large-size power devices such as Figure 1 As shown in the figure, when the ESD positive pulse arrives, the SW voltage rises and couples to the gate of the power tube through a large gate-drain capacitance, turning it on. However, due to the effect of the PM1 parasitic diode D1 of the driver stage, the gate potential will be clamped to VDD+VF. If the ESD event occurs between SW and VDD, the gate voltage will be clamped to VF, making it unable to turn on normally and damaged. Utility Model Content
[0005] In view of the problems existing in the prior art, the utility model provides an electrostatic self-protection circuit suitable for an integrated power tube.
[0006] The technical solution of the utility model is:
[0007] An electrostatic self-protection circuit suitable for an integrated power tube comprises an integrated power tube unit, wherein the integrated power tube unit comprises a power tube MN1, wherein the power tube MN1 is an N-channel MOS tube, and is formed by connecting a plurality of unit MOS tubes in parallel, wherein the drain of the power tube MN1 is led out as the drain pin of the integrated power tube unit, and the source of the power tube MN1 is led out as the ground pin GND of the integrated power tube unit; the circuit is characterized in that it also comprises a driving circuit, wherein the driving circuit is connected to the gate of the power tube MN1, and when an ESD event occurs at the drain pin of the power tube, the driving circuit turns on the power tube MN1, and discharges electrostatic electricity through the conduction path of the power tube MN1, and at the same time, the driving circuit clamps the gate voltage of the power tube MN1, so that the power tube MN1 can be turned on but does not cause a gate oxide layer breakdown.
[0008] Further, the driving circuit includes a MOS tube MP1, a MOS tube MP2, a MOS tube MN2, a MOS tube MN3, a resistor R1, a first inverter, and a second inverter; the PWM signal is input into the gate of the MOS tube MN2 after passing through the first inverter, and the PWM signal is input into the gate of the MOS tube MP1 after passing through the first inverter and the second inverter in sequence; the source of the MOS tube MP1 is connected to the power supply, and the drain thereof is connected to the drain of the MOS tube MP2, and the source and substrate of the MOS tube MP2 are connected to the gate of the power tube MN1 and the drain of the MOS tube MN2; the gate of the MOS tube MN3 is connected to the enable signal, and the drain thereof is connected to the gate of the MOS tube MP2 and one end of the resistor R1; the source of the MOS tube MN2, the source of the MOS tube MN3, and the other end of the resistor R1 are all grounded GND.
[0009] Furthermore, the driving circuit includes a MOS tube MP1, a MOS tube MP2, a MOS tube MN2, a MOS tube MN3, a resistor R1, a first inverter, a second inverter, a first Schottky diode D1 and a second Schottky diode D2; the PWM signal is input to the gate of the MOS tube MN2 after passing through the first inverter, and the PWM signal is input to the gate of the MOS tube MP1 after passing through the first inverter and the second inverter in sequence; the source of the MOS tube MP1 is connected to the power supply, and the drain thereof is connected to the source of the MOS tube MP2, and the MOS tube MP The drain of the first Schottky diode D1 is connected to the gate of the power tube MN1, the drain of the MOS tube MN2 is connected to the gate of the power tube MN1 and the drain of the MOS tube MN2; the gate of the MOS tube MN3 is connected to the enable signal, and the drain thereof is connected to the gate of the MOS tube MP2 and one end of the resistor R1; the source of the MOS tube MN2, the source of the MOS tube MN3, and the other end of the resistor R1 are all grounded GND; the anode of the first Schottky diode D1 is connected to the gate of the power tube MN1, the cathode of the first Schottky diode D1 and the cathode of the second Schottky diode D2 are connected to the substrate of the MOS tube MP2, and the anode of the second Schottky diode D2 is connected to the power supply.
[0010] The beneficial effect of the present invention is that the present invention can provide a higher gate voltage when an ESD event occurs to ensure that the power tube is turned on and the ESD current is discharged normally through the channel. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 It is a schematic diagram of the self-protection circuit structure of traditional large-size power devices.
[0012] Figure 2 It is a structural schematic diagram of Example 1.
[0013] Figure 3 It is a structural schematic diagram of Example 2.
[0014] Figure 4 It is a simulation schematic diagram. DETAILED DESCRIPTION
[0015] The utility model is described in detail below with reference to the accompanying drawings and embodiments.
[0016] Example 1
[0017] The structure of this example is as follows Figure 2 As shown, it includes a power tube MN1, a MOS tube MP1, a MOS tube MP2, a MOS tube MN3, a resistor R1, a first inverter, and a second inverter; the drain of MN1 is connected to the SW node voltage, and the source is grounded; the PWM signal is input to the gate of the MOS tube MN2 after passing through the first inverter, and the PWM signal is input to the gate of the MOS tube MP1 after passing through the first inverter and the second inverter in sequence; the source of the MOS tube MP1 is connected to the power supply, the drain of the MOS tube MP2 is connected to the source of the MOS tube MP2, the source and substrate of the MOS tube MP2 are connected to the gate of the power tube MN1 and the drain of the MOS tube MN2; the gate of the MOS tube MN3 is connected to the enable signal, and the drain of the MOS tube MN3 is connected to the gate of the MOS tube MP2 and one end of the resistor R1; the source of the MOS tube MN2, the source of the MOS tube MN3, and the other end of the resistor R1 are all grounded GND.
[0018] In this example, the substrate of MP2 is connected to the gate of MN1, forming a back-to-back diode, blocking the diode path that originally clamped the gate voltage. When the ESD pulse arrives, the voltage of the SW node jumps, and the C gd Coupled to GATE, causing GATE to rise, while the change of GATE is also passed through MP2's C gd Coupled to the gate of MP2, causing its voltage to rise, and the GATE voltage is thus clamped to V G2 +V GS_MP2 , V GATE It can be calculated by the following formula:
[0019]
[0020] Since the gate-drain capacitance of MN1 is much larger than the gate-drain capacitance of MP2, this formula can be simplified to:
[0021]
[0022] By designing the resistance value of R1, different gate peak voltages can be obtained to meet different ESD current requirements.
[0023] MN3 controlled by the chip global enable signal EN ensures that MP2 remains turned on during normal operation to avoid false triggering and entering the ESD protection state during normal operation.
[0024] Example 2
[0025] The structure of this example is as follows Figure 3As shown, compared with the structure of Example 1, this example further includes a first Schottky diode D1 and a second Schottky diode D2, the anode of the first Schottky diode D1 is connected to the gate of the power tube MN1, the cathode of the first Schottky diode D1 and the cathode of the second Schottky diode D2 are connected to the substrate of the MOS tube MP2, and the anode of the second Schottky diode D2 is connected to the power supply. In this example, MP2 can obtain the correct substrate potential both during ESD events and during normal operation. Specifically, when an ESD event occurs, GATE will be higher than VDD, and the substrate potential of MP2 is GATE-VF at this time. When it is working normally, VDD is higher than GATE, and the substrate potential of MP2 is VDD-VF at this time.
[0026] The advantage of this example over Example 1 is that the structure of Example 1 has a stage of parasitic PNP conduction during normal operation. Specifically, when MP1 is turned on, the drain end of MP2 is higher than the source end, Drain-BULK-PSUB is turned on, and current flows from the drain end to PSUB, which reduces the driving speed and causes additional power consumption. This example uses a substrate selection circuit to ensure that MP2 can obtain the correct substrate potential both during ESD events and during normal operation.
[0027] Similarly, MN3 controlled by the chip global enable signal EN ensures that MP2 remains turned on during normal operation, thereby avoiding false triggering to enter the ESD protection state during normal operation.
[0028] pass Figure 4 The simulation diagram can prove that the solution of the utility model can provide a higher gate voltage to ensure that the power tube is turned on when an ESD event occurs, while clamping the gate voltage.
Claims
1. An electrostatic self-protection circuit suitable for an integrated power tube, comprising an integrated power tube unit, wherein the integrated power tube unit comprises a power tube MN1, wherein the power tube MN1 is an N-channel MOS tube, and is composed of a plurality of unit MOS tubes connected in parallel, wherein the drain of the power tube MN1 is led out as the drain pin of the integrated power tube unit, and the source of the power tube MN1 is led out as the ground pin GND of the integrated power tube unit; wherein: The device also includes a driving circuit, which is connected to the gate of the power tube MN1. When an ESD event occurs at the drain pin of the power tube, the driving circuit turns on the power tube MN1, discharges static electricity through the conduction path of the power tube MN1, and clamps the gate voltage of the power tube MN1, so that the power tube MN1 can be turned on but does not cause a breakdown of the gate oxide layer; The driving circuit comprises a MOS tube MP1, a MOS tube MP2, a MOS tube MN2, a MOS tube MN3, a resistor R1, a first inverter, a second inverter, a first Schottky diode D1 and a second Schottky diode D2; a PWM signal is input to the gate of the MOS tube MN2 after passing through the first inverter, and the PWM signal is input to the gate of the MOS tube MP1 after passing through the first inverter and the second inverter in sequence; a source of the MOS tube MP1 is connected to a power supply, a drain thereof is connected to the source of the MOS tube MP2, and a drain thereof is connected to the gate of the power tube MN1 and the drain of the MOS tube MN2; a gate of the MOS tube MN3 is connected to an enable signal, and a drain thereof is connected to the gate of the MOS tube MP2 and one end of the resistor R1; a source of the MOS tube MN2, a source of the MOS tube MN3 and the other end of the resistor R1 are all grounded GND; an anode of the first Schottky diode D1 is connected to the gate of the power tube MN1, a cathode of the first Schottky diode D1 and a cathode of the second Schottky diode D2 are connected to the substrate of the MOS tube MP2, and an anode of the second Schottky diode D2 is connected to a power supply.