Pixel unit structure

Abstract

The utility model relates to a pixel unit structure, which comprises a supporting substrate, a pixel main body and an outer edge wall body, and is characterized in that the supporting substrate is provided with a first surface and a second surface; the pixel main body is arranged on the first surface and comprises a second semiconductor layer, an active layer and a first semiconductor layer which are sequentially stacked in the first direction; the outer edge wall body is arranged on the side wall of the pixel main body, the outer edge wall body comprises a first wall body layer, and the first wall body layer is attached to the side wall of the pixel main body; the first semiconductor layer and the second semiconductor layer are insulated from each other through the first wall body layer. According to the utility model, the phenomena of electric leakage and failure of the pixel unit structure can be effectively prevented, a photoetching machine does not need to be adopted when the outer edge wall body is prepared, the defects caused by using the photoetching machine to carry out graphical etching in the prior art are avoided, and meanwhile, the preparation precision can be effectively ensured.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a pixel unit structure. Background Art

[0002] As LED displays gradually develop towards high integration and high resolution, pixel size is also becoming smaller. When insulating and passivating the sidewalls of existing pixel unit structures, they are generally covered with a passivation layer and then patterned by a photolithography machine. However, when the pixel size is reduced to the micron level or even the submicron level, there are greater challenges for the minimum line width and overlay accuracy of the photolithography machine. During the photolithography process, patterning failure and large overlay offset (alignment deviation between the lower and upper layers of graphics in different areas on different wafers) are prone to occur, resulting in short-circuit leakage in different compound functional areas of the pixel unit, which in turn leads to performance degradation or failure of the LED device, which cannot meet the processing and use requirements. At the same time, the higher the overlay accuracy of the photolithography machine, the higher its purchase cost, which further increases the production cost. Utility Model Content

[0003] Therefore, the technical problem to be solved by the present invention is mainly to overcome the defects of the prior art that the pixel unit structure is prone to leakage failure and the manufacturing effect is poor.

[0004] In order to solve the above technical problems, the utility model provides a pixel unit structure, including:

[0005] A support substrate having a first surface and a second surface arranged opposite to each other along a first direction;

[0006] A pixel body, wherein the pixel body is disposed on the first surface, and the pixel body comprises a second semiconductor layer, an active layer, and a first semiconductor layer sequentially disposed along a first direction;

[0007] An outer edge wall body is arranged on the side wall of the pixel body, and the outer edge wall body includes a first wall body layer, and the first wall body layer is insulated from the side wall of the pixel body; the first wall body layer is an insulator, and the first semiconductor layer and the second semiconductor layer are insulated from each other by the first wall body layer.

[0008] In one embodiment of the present invention, one end of the outer edge wall body close to the supporting substrate is in direct contact with the supporting substrate.

[0009] In one embodiment of the present invention, one end of the outer edge wall body close to the supporting substrate is separated from the supporting substrate by the second semiconductor layer to expose the second semiconductor layer.

[0010] In one embodiment of the present invention, the thickness of the first wall layer is 50 nm to 1500 nm.

[0011] In one embodiment of the present invention, the outer edge wall body further includes a second wall body layer, and the second wall body layer is in contact with the outer wall of the first wall body layer.

[0012] In one embodiment of the present invention, a step portion is formed on one end of the first wall layer close to the support substrate, and the second wall layer is located on the step portion.

[0013] In one embodiment of the present invention, the second wall layer is a reflective layer or a conductive layer, or a composite layer consisting of a reflective layer and a conductive layer.

[0014] In one embodiment of the present invention, the outer edge wall further includes a metal barrier layer, and the second wall layer is located between the first wall layer and the metal barrier layer.

[0015] In one embodiment of the present invention, the length of the pixel body along the second direction is 0.35 um to 50 um, and the second direction is perpendicular to the first direction.

[0016] In one embodiment of the present invention, the angle between the pixel body and the supporting substrate is 45° to 135°.

[0017] In one embodiment of the present invention, the angle between the pixel body and the supporting substrate is 70° to 110°.

[0018] In one embodiment of the present invention, the first semiconductor layer is a P-type semiconductor layer or an N-type semiconductor layer, and the second semiconductor layer is an N-type semiconductor layer or a P-type semiconductor layer.

[0019] The above technical solution of the utility model has the following advantages compared with the prior art:

[0020] The pixel unit structure described in the utility model can effectively prevent the pixel unit structure from leakage failure. At the same time, when preparing the outer edge wall at the side wall of the pixel body, there is no need to use a photolithography machine, but instead a dry etching method is used, thereby avoiding the defects of graphic failure, large overlay offset, high production cost, etc. caused by using a photolithography machine for graphic etching in the prior art, and at the same time, the preparation accuracy can be effectively guaranteed; it is also convenient to customize the outer edge wall structure to enhance the optical and electrical functions, realize optical or electrical regulation, and improve the convenience of use. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to make the content of the utility model more clearly understood, the utility model is further described in detail below based on specific embodiments of the utility model in combination with the accompanying drawings.

[0022] Figure 1 It is a structural schematic diagram of an implementation mode of the pixel unit structure of the utility model (including the second wall layer);

[0023] Figure 2 This is a structural schematic diagram of another embodiment of the pixel unit structure of the utility model (including the second wall layer)

[0024] Figure 3 This is a structural schematic diagram of an implementation of the pixel unit structure of the utility model (only having the first wall layer)

[0025] Figure 4 This is a structural schematic diagram of another embodiment of the pixel unit structure of the utility model (only having the first wall layer)

[0026] Figure 5 This is a structural schematic diagram of an implementation of the pixel unit structure of the utility model (including a metal barrier layer)

[0027] Figure 6 This is a schematic diagram of the preparation process of an embodiment of the pixel unit structure of the utility model.

[0028] (with only the first wall layer);

[0029] Figure 7 It is a schematic diagram of the preparation process of an embodiment of the pixel unit structure of the utility model (including the second wall layer);

[0030] Figure 8 It is a schematic diagram of the preparation process of another embodiment of the pixel unit structure of the utility model (including the second wall layer);

[0031] Fig. 9 It is a schematic diagram of the preparation process of an embodiment of the pixel unit structure of the utility model (including a metal barrier layer);

[0032] Description of the Figures in the Specification:

[0033] 10. Support substrate; 101. First surface; 102. Second surface;

[0034] 20, pixel body; 201, first semiconductor layer; 202, active layer; 203, second semiconductor layer;

[0035] 30, outer edge wall; 301, first wall layer; 3011, step portion; 302, second wall layer; 303, metal barrier layer;

[0036] 40. Etching barrier layer. DETAILED DESCRIPTION

[0037] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present disclosure and its application or use.

[0038] In the description of the present utility model, it should be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, unless otherwise specified, "multiple" means two or more.

[0039] The present embodiment provides a pixel unit structure, which can prevent the pixel unit from failing due to leakage, improve the manufacturing effect, improve the production efficiency, and effectively reduce the production cost.

[0040] The structure of this embodiment will be further described below in conjunction with the accompanying drawings.

[0041] Embodiment 1

[0042] See also Figure 1 , this embodiment discloses a pixel unit structure, including a supporting substrate 10, a pixel body 20 and an outer edge wall 30;

[0043] The first direction and the second direction are as follows: Figure 1 As shown in;

[0044] The support substrate 10 has a first surface 101 and a second surface 102 arranged opposite to each other along a first direction;

[0045] The pixel body 20 is disposed on the first surface 101 , and the pixel body 20 includes a second semiconductor layer 203 , an active layer 202 , and a first semiconductor layer 201 sequentially disposed along a first direction; wherein the active layer 202 is used for emitting light.

[0046] The outer edge wall 30 is arranged on the side wall of the pixel body 20, and the outer edge wall 30 includes a first wall layer 301. The first wall layer 301 is in contact with the side wall of the pixel body 20, and there is no gap between the two. The first wall layer 301 is an insulator, and the first semiconductor layer 201 and the second semiconductor layer 203 are insulated from each other by the first wall layer 301.

[0047] The above-mentioned pixel unit structure, by setting an outer edge wall body 30 at the side wall of the pixel body 20 of the optical element, makes the first semiconductor layer 201 and the second semiconductor layer 203 insulated from each other by the first wall body layer 301, which can effectively avoid the short circuit leakage phenomenon between the first semiconductor layer 201 and the second semiconductor layer 203; in addition, through the setting of the above-mentioned outer edge wall body 30, the exposed opening of the first semiconductor layer 201 is maximized, that is, the contact area of ​​the first semiconductor layer 201 is maximized, which is more conducive to the subsequent ohmic contact use, thereby better ensuring the reliability of the pixel unit structure.

[0048] Furthermore, the above pixel unit is mainly made of compound semiconductor materials, which generally refer to compounds formed by two or more elements. For example, the compound semiconductor here is mainly a light-emitting diode epitaxial material, such as InGaN ternary material system or AlGaInP quaternary material system, and its luminous wavelength can cover the entire band from ultraviolet, visible light and infrared.

[0049] In one embodiment, the first semiconductor layer 201 is a P-type semiconductor layer, and the second semiconductor layer 203 is an N-type semiconductor layer; or, the first semiconductor layer 201 is an N-type semiconductor layer, and the second semiconductor layer 203 is a P-type semiconductor layer.

[0050] Among them, the support substrate 10 can be gallium nitride (GaN), silicon (Si), silicon carbide (SiC), sapphire (Sapphire), gallium arsenide (GaAs), indium phosphide (InP) and the like.

[0051] Taking the Micro-LED field as an example, some compound materials involved in this embodiment are shown in Table 1 below. In some practical applications, the film layer of the compound will be more complicated, or there will be cross-use of materials, mainly including P-type semiconductor layer materials, N-type semiconductor layer materials and an active layer (MQW quantum well) sandwiched between the two:

[0052] Table 1. Materials of various compound films

[0053] Layer Name Material Material Material Material Material Material Material P-type semiconductor layer GaP GaAs GaAs GaAs AlGaN GaN GaN MQW Active Quantum Well AlGaInP AlGaInP InGaAs AlGaAs InGaN InGaN InGaN N-type semiconductor layer GaAs AlGaAs AlGaAs GaAs GaN GaN GaN Support substrate GaAs GaAs GaAs GaAs GaN Si Sapphire

[0054] A P-type ohmic contact layer can also be set on the surface of the P-type semiconductor layer. The above-mentioned materials used to form the P-type ohmic contact layer include a single layer or a stack of transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or a single layer or a stack of metals such as Ni, Cr, Au, Ag, Zn, Be, Al (nickel, chromium, gold, silver, zinc, beryllium, aluminum), or an alloy, or a stack of transparent metal oxides and metals; an N-type ohmic contact layer can also be set on the surface of the N-type semiconductor layer. The materials used to form the N-type ohmic contact include a single layer or a stack of transparent metal oxides such as ITO, IZO, ZnO, or a single layer or a stack of metals such as Ni (nickel), Cr (chromium), Ti (titanium), Au (gold), Ge (germanium), Al (aluminum), or an alloy, or a stack of transparent metal oxides and metals.

[0055] In one embodiment, if Figure 1 , Figure 2 , Figure 3 and Figure 5 As shown, one end of the outer wall 30 close to the support substrate 10 is directly in contact with the support substrate 10. In this way, the outer wall 30 is directly in contact with the support substrate 10, and the second semiconductor layer 203 is not exposed outside the outer wall 30.

[0056] In one embodiment, if Figure 1 As shown, the thickness L1 of the first wall layer 301 is 50 nm to 1500 nm. The selection of this thickness range can maximize the thickness requirements of the dielectric layer of the omnidirectional reflection structure required for different wavelengths while achieving ideal insulation packaging.

[0057] In one embodiment, if Figure 1 and Figure 2 As shown, the outer edge wall 30 further includes a second wall layer 302 , and the second wall layer 302 is tightly fitted to the outer wall of the first wall layer 301 .

[0058] Among them, Figure 1 As shown, the end of the first wall layer 301 close to the supporting substrate 10 may adopt the following step portion 3011 structure:

[0059] A step portion 3011 is formed at one end of the first wall layer 301 close to the support substrate 10 , and the second wall layer 302 is located on the step portion 3011 .

[0060] Among them, Figure 2 As shown, the end of the first wall layer 301 close to the supporting substrate 10 may also adopt a structure without a step portion.

[0061] In one embodiment, the second wall layer 302 is a reflective layer or a conductive layer, or a composite layer consisting of a reflective layer and a conductive layer, so as to enhance the optical and electrical functions.

[0062] By providing a reflective layer in the second wall layer 302, the effect of side reflection can be achieved, which is more conducive to the realization of omnidirectional reflection, greatly improving the brightness of the pixel unit and the collimation of light, and obtaining better performance and a smaller divergence angle.

[0063] By providing a conductive layer in the second wall layer 302 , it is easier to electrically connect the pixel unit with other components.

[0064] Furthermore, the reflective layer may be deposited from a metal with high reflectivity such as aluminum (Al), silver (Ag), gold (Au), rhodium (Rh) or platinum (Pt);

[0065] The conductive layer can be formed by depositing highly conductive metals such as aluminum (Al), copper (Cu), tungsten (W), and titanium (Ti).

[0066] The second wall layer 302 may also be a laminate of a transparent conductive layer and a metal layer, such as a silver or titanium tungsten film layer laminated on zinc oxide.

[0067] In one embodiment, if Figure 5 As shown, the outer edge wall 30 further includes a metal barrier layer 303 , and the second wall layer 302 is located between the first wall layer 301 and the metal barrier layer 303 .

[0068] The metal barrier layer 303 is mainly used to block the migration of metal ions at the periphery.

[0069] The metal barrier layer 303 may be a single-layer structure or a multi-layer structure.

[0070] The metal barrier layer 303 may be a combination layer of a metal layer and a dielectric layer, or may be a separate metal layer or dielectric layer. For example, the metal layer may be made of Ag, Al, Cu or Ti, and the dielectric layer may be made of silicon nitride.

[0071] In one embodiment, if Figure 1 As shown, the length L2 of the pixel body 20 along the second direction is 0.35um to 50um, and the second direction is perpendicular to the first direction. This length range covers the size of the light-emitting unit for micro-display and micro-projection applications, and the pixel size can be minimized while meeting the performance of Micro LED.

[0072] In one embodiment, if Figure 6As shown in stage b, the angle θ between the pixel body 20 and the supporting substrate 10 is approximately 90°, and may specifically be 45° to 135°, such as 50°, 60°, 90°, 120°, etc.

[0073] Furthermore, the angle θ between the pixel body 20 and the supporting substrate 10 is 70° to 110°, for example, 80°, 90°, 100°, etc. The above angle range can meet different light extraction requirements.

[0074] like Figure 6 As shown, this embodiment also discloses a method for preparing a pixel unit structure, the method comprising:

[0075] Step S1), refer to Figure 6 In the middle stage a, a second semiconductor layer 203, an active layer 202, a first semiconductor layer 201 and an etching stop layer 40 are sequentially formed on the first surface 101 of the support substrate 10 along a first direction;

[0076] The etching stop layer 40 , in addition to being in contact with the first semiconductor layer 201 , is mainly used as a mask and etching stop layer for pattern etching and subsequent etching of the outer edge wall 30 .

[0077] The etching stop layer 40 may be a dielectric layer (such as silicon oxide, silicon nitride, etc.), a contact layer (such as) or a stacked layer with a contact layer at the bottom and a dielectric layer at the top.

[0078] The mask layer is a dielectric layer such as silicon oxide, silicon nitride, etc., or a contact layer (such as ITO or other metals, etc.), or a stacked layer with a contact layer at the bottom and a dielectric layer at the top.

[0079] Step S2), refer to Figure 6 In stage b, the pixel body 20 is obtained by dry etching or wet etching with the etching stop layer 40 as a mask. The length of the pixel body 20 along the second direction is the same as the length of the etching stop layer 40, and the second direction is perpendicular to the first direction.

[0080] The above-mentioned dry etching can adopt dry etching methods such as inductively coupled plasma etching (ICP) and reactive ion etching (RIE), and the wet etching method can adopt wet etching methods such as potassium hydroxide (KOH) and hydrochloric acid (HCl).

[0081] Furthermore, the angle θ between the pixel body 20 obtained by etching and the supporting substrate 10 is about 90°, specifically, it can be 45° to 135°, and preferably 70° to 110°.

[0082] Furthermore, if Figure 6As shown in stage b, the total thickness H1 from the second semiconductor layer 203 to the first semiconductor layer 201 is 0.3 um to 5 um. It should be noted that the thickness includes the thickness of the first semiconductor layer 201 and the second semiconductor layer 203 themselves.

[0083] Step S3), refer to Figure 6 In the middle stage c, a first wall layer 301 is deposited outside the pixel body 20, and the etching stop layer 40 is located between the pixel body 20 and the first wall layer 301, that is, at this time, the first wall layer 301 also covers the etching stop layer 40;

[0084] The first wall layer 301 is etched by dry etching, and only the first wall layer 301 located at the side wall of the pixel body is retained after etching. Figure 6 and controlling the etching time to remove the etching stop layer 40 so that the first semiconductor layer 201 is exposed, so as to facilitate the subsequent ohmic contact.

[0085] In one embodiment, in step S3), when the first wall layer 301 is deposited outside the pixel body 20, the deposition thickness of the first wall layer located at the top of the pixel body is defined as D1, and the deposition thickness of the first wall layer located at the side wall of the pixel body is defined as D2, then D1≥D2, so that the thickness of the first wall layer at the side wall can be better retained during subsequent etching.

[0086] The first wall layer 301 may include only a single layer or a multi-layer structure.

[0087] Furthermore, the first wall layer 301 includes at least two layers, and the materials of two adjacent layers are different.

[0088] For example, the first wall layer 301 may be a stack of a silicon oxide layer and an aluminum oxide layer, so as to construct a distributed Bragg reflector (DBR) structure by utilizing the refractive index difference between the two materials.

[0089] In one embodiment, the first wall layer 301 includes one or more of silicon oxide, aluminum oxide, silicon nitride, titanium oxide or niobium oxide.

[0090] The preparation method of the above-mentioned pixel unit structure does not need to use a photolithography machine when preparing the outer edge wall 30 at the side wall of the pixel body, but instead adopts dry etching. This can get rid of the need for more advanced photolithography machines and does not require an exposure process. It avoids the defects of graphic failure, large overlay offset, and high production cost caused by using a photolithography machine for graphic etching in the prior art. At the same time, it can also effectively ensure the preparation accuracy, achieve in-situ or self-alignment type accuracy, and achieve sub-micron accuracy using micron-level equipment technology; at the same time, it can ensure that the contact area of ​​the first semiconductor layer is exposed to the maximum extent, and when necessary, the outer edge wall structure can be customized to enhance the optical and electrical functions, realize optical or electrical regulation, and the structural form is more flexible.

[0091] Embodiment 2

[0092] See also Figure 4 The main difference between this embodiment and embodiment 1 is that the end of the outer edge wall 30 close to the supporting substrate 10 is separated from the supporting substrate 10 by the second semiconductor layer 203 to expose the second semiconductor layer 203. This method can make the second semiconductor directly exposed to the outside of the outer edge wall 30, so as to make it easier to use the second semiconductor for electrical connection, for example, it can be used as a common cathode, etc.

[0093] Embodiment 3

[0094] See also Figure 7 The main difference between this embodiment and the first embodiment is that this embodiment also needs to prepare the second wall layer 302, and the preparation is carried out by overall etching. The specific preparation method is as follows:

[0095] First complete the preparation of step S1) and step S2), and then proceed to step S3). In step S3), refer to Figure 7 In the middle stage d, after the first wall layer 301 is deposited on the outside of the pixel body 20, the second wall layer 302 needs to be deposited. After all the deposition is completed, the entire structure composed of the first wall layer 301 and the second wall layer 302 is etched as a whole by dry etching. After etching, only the first wall layer 301 and the second wall layer 302 located at the side wall of the pixel body are retained, and the following is obtained: Figure 7 The structure shown in stage e; and controlling the etching time to remove the etching stop layer 40 so that the first semiconductor layer 201 is exposed;

[0096] In the pixel unit structure obtained by the above-mentioned preparation method, a step portion 3011 is formed at one end of the first wall layer 301 close to the supporting substrate, and the second wall layer 302 is located on the step portion 3011 .

[0097] The second wall layer 302 may be a single-layer or multi-layer structure.

[0098] The second wall layer 302 may be a reflective layer or a conductive layer, or a composite layer consisting of a reflective layer and a conductive layer, so as to enhance the optical and electrical functions.

[0099] The reflective layer can be formed by depositing a high reflectivity metal such as aluminum (Al), silver (Ag), gold (Au), rhodium (Rh) or platinum (Pt); the conductive layer can be formed by depositing a high conductive metal such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti) or the like.

[0100] By setting the second wall layer 302 as a reflective layer, the effect of side reflection can be achieved, which is more conducive to the realization of omnidirectional reflection, greatly improving the brightness of the pixel unit and the collimation of light, obtaining better performance and a smaller divergence angle, and while forming omnidirectional reflection, the exposure process for preparing each film layer can be omitted, without the need for a photolithography machine, with a narrow engraving distance and high precision.

[0101] Embodiment 4

[0102] See also Figure 8 The main difference between this embodiment and the first embodiment is that this embodiment also needs to prepare the second wall layer 302. The difference from the second embodiment is that the layered etching method is used during the preparation. The specific preparation method is as follows:

[0103] First, the preparation of step S1) and step S2) is completed, and then step S3) is performed. In step S3), after the first wall layer 301 is deposited outside the pixel body 20, the first wall layer 301 is first etched by dry etching, and only the first wall layer 301 located at the side wall of the pixel body is retained after etching, and then Figure 8 As shown in stage e, a second wall layer 302 is deposited outside the first wall layer 301, so that the etching stop layer 40, the pixel body 20 and the first wall layer 301 are all located inside the second wall layer 302. After the deposition is completed, the second wall layer 302 is etched by dry etching. After etching, only the second wall layer 302 located at the side wall of the pixel body is retained, and the second wall layer 302 is obtained. Figure 8 and controlling the etching time to remove the etching stop layer 40 so that the first semiconductor layer 201 is exposed.

[0104] In the pixel unit structure obtained by the above-mentioned preparation method, there is no step portion between the first wall layer 301 and the second wall layer 302 .

[0105] The second wall layer 302 may be a single-layer or multi-layer structure.

[0106] The second wall layer 302 may be a reflective layer or a conductive layer, or a composite layer consisting of a reflective layer and a conductive layer, so as to enhance the optical and electrical functions.

[0107] The reflective layer can be formed by depositing a high reflectivity metal such as aluminum (Al), silver (Ag), gold (Au), rhodium (Rh) or platinum (Pt); the conductive layer can be formed by depositing a high conductive metal such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti) or the like.

[0108] Embodiment 5

[0109] The main difference between this embodiment and embodiments 3 and 4 is that this embodiment also requires the preparation of a metal barrier layer 303, and the specific preparation method is as follows:

[0110] One preparation method is: Fig. 9 As shown, in the third embodiment, after etching, only the first wall layer 301 and the second wall layer 302 located at the side wall of the pixel body are retained, and then a metal barrier layer 303 is deposited outside the second wall layer 302, so that the etching barrier layer 40, the pixel body 20, the first wall layer 301 and the second wall layer 302 are all located inside the metal barrier layer 303. After the deposition is completed, the metal barrier layer 303 is etched by dry etching, and only the metal barrier layer 303 located at the side wall of the pixel body is retained after etching; and the etching time is controlled to remove the etching barrier layer 40 so that the first semiconductor layer 201 is exposed.

[0111] Another preparation method is: after etching in Example 4, only the first wall layer 301 and the second wall layer 302 located at the side wall of the pixel body 20 are retained, and a metal barrier layer 303 is deposited outside the second wall layer 302, so that the etching barrier layer 40, the pixel body 20, the first wall layer 301 and the second wall layer 302 are all located inside the metal barrier layer 303. After the deposition is completed, the metal barrier layer 303 is etched by dry etching, and only the metal barrier layer 303 located at the side wall of the pixel body is retained after etching; and the etching time is controlled to remove the etching barrier layer 40 so that the first semiconductor layer 201 is exposed.

[0112] The metal barrier layer 303 is mainly used to block the migration of metal ions at the periphery.

[0113] The metal barrier layer 303 may be a single-layer structure or a multi-layer structure.

[0114] The metal barrier layer 303 may be a combination of a metal layer and a dielectric layer, or may be a separate metal layer or dielectric layer. For example, the metal layer may be made of Ag, Al, Cu or Ti, and the dielectric layer may be made of silicon nitride.

[0115] The preparation methods of the pixel unit structures of the above-mentioned embodiments do not need to use a photolithography machine when preparing the outer edge wall at the side wall of the pixel body, but use dry etching to achieve it, thereby avoiding defects such as patterning failure, large overlay offset, and high production cost caused by using a photolithography machine for patterning etching in the prior art, and can also effectively ensure the preparation accuracy; at the same time, the outer edge wall structure can also be customized to enhance the optical and electrical functions and realize optical or electrical regulation. .

[0116] All of the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of the present invention, that is, any multiple embodiments can be combined to meet the needs of different application scenarios. They are all within the protection scope of this application and will not be described one by one here.

[0117] It should be noted that the above embodiments are merely examples for the purpose of clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the scope of protection of the invention.

Claims

1. A pixel unit structure, characterized in that: include, A support substrate having a first surface and a second surface arranged opposite to each other along a first direction; A pixel body, wherein the pixel body is disposed on the first surface, and the pixel body comprises a second semiconductor layer, an active layer, and a first semiconductor layer sequentially disposed along a first direction; An outer edge wall body is arranged on the side wall of the pixel body, and the outer edge wall body includes a first wall body layer, and the first wall body layer is insulated from the side wall of the pixel body; the first wall body layer is an insulator, and the first semiconductor layer and the second semiconductor layer are insulated from each other by the first wall body layer.

2. The pixel unit structure according to claim 1, characterized in that: One end of the outer edge wall body close to the support substrate directly contacts the support substrate.

3. The pixel unit structure according to claim 1, characterized in that: One end of the outer edge wall body close to the support substrate is separated from the support substrate by the second semiconductor layer to expose the second semiconductor layer.

4. The pixel unit structure according to claim 1, characterized in that: The thickness of the first wall layer is 50 nm to 1500 nm.

5. The pixel unit structure according to claim 1, characterized in that: The outer edge wall body also includes a second wall body layer, and the second wall body layer is in contact with the outer wall of the first wall body layer.

6. The pixel unit structure according to claim 5, characterized in that: A step portion is formed at one end of the first wall layer close to the support substrate, and the second wall layer is located on the step portion.

7. The pixel unit structure according to claim 5, characterized in that: The second wall layer is a reflective layer or a conductive layer, or a composite layer consisting of a reflective layer and a conductive layer.

8. The pixel unit structure according to claim 5, characterized in that: The outer edge wall also includes a metal barrier layer, and the second wall layer is located between the first wall layer and the metal barrier layer.

9. The pixel unit structure according to claim 1, characterized in that: The length of the pixel body along the second direction is 0.35um-50um, and the second direction is perpendicular to the first direction.

10. The pixel unit structure according to claim 1, characterized in that: The angle between the pixel body and the supporting substrate is 45° to 135°.

11. The pixel unit structure according to claim 1, characterized in that: The angle between the pixel body and the supporting substrate is 70° to 110°.

12. The pixel unit structure according to claim 1, characterized in that: The first semiconductor layer is a P-type semiconductor layer or an N-type semiconductor layer, and the second semiconductor layer is an N-type semiconductor layer or a P-type semiconductor layer.

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