Packaging structure and printed circuit board

Abstract

The utility model relates to the technical field of semiconductors, and discloses a packaging structure and a printed circuit board, the packaging structure comprises a substrate, a plurality of first solder balls and a plurality of second solder balls, the substrate is provided with a first area and a second area, and the first area is arranged around the peripheral side of the second area; the plurality of first solder balls are arranged in the first area and are arranged in multiple rows and multiple columns in the first area, and the first solder balls in two adjacent rows are arranged in a staggered manner; the plurality of second solder balls are arranged in the second area and are arranged in a rectangular array in the second area. According to the invention, the first solder balls are arranged in a staggered manner, so that the distance between the first solder balls in the same column and the same row can be increased, the number of the leads which can be fanned out between the adjacent first solder balls is increased, the number of the leads which can be fanned out from the surface layer of the PCB is increased, the number of the leads which need to be fanned out from the inner layer of the PCB in a punching manner is reduced, and the number of the leads which need to be fanned out from the inner layer of the PCB is reduced. And the number of layers in the required PCB is reduced, so that the thickness and the cost of the PCB are reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a packaging structure and a printed circuit board. Background Art

[0002] The rapid development of smart mobile devices has driven the development of more advanced chip packaging technologies to meet the requirements of mobile devices for smaller size, lower power consumption and more powerful functions. In chip packaging technology, ball grid array (BGA) packaging technology is one of the mainstream packaging technologies. BGA packaging technology is to make array solder balls at the bottom of the package substrate, which are connected to the printed circuit board (PCB) as the I / O end of the circuit. In BGA packaging technology, the arrangement of solder balls will directly affect parameters such as the solder ball spacing and the number of solder balls. Parameters such as the solder ball spacing and the number of solder balls will not only affect the package size, but also affect the fan-out method on the PCB board.

[0003] Currently, if Figure 1 As shown, the solder balls 2 at the bottom of the substrate 1 are generally arranged in a rectangular array, and the solder balls are arranged at equal intervals. The solder ball spacing in the outer circle area is 0.8 mm, and the solder ball spacing in the center area is 1.0 mm. The leads can only fan out from the solder ball spacing in the outermost circle area. Due to the small spacing, when the leads 5 are fanned out on the PCB board, only one lead 5 can be fanned out from the surface layer of the PCB board between the adjacent solder balls 2 in the outermost circle, and the other solder ball leads 5 must be fanned out from the inner layer of the PCB board by punching, resulting in a larger number of layers required for the PCB board to meet the fan-out requirements, which increases the thickness and cost of the PCB board. Utility Model Content

[0004] The utility model aims to provide a packaging structure and a printed circuit board, so as to increase the fan line of the surface layer of the PCB board and reduce the thickness and cost of the PCB board.

[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0006] One aspect of the present application is to provide a packaging structure, comprising:

[0007] A substrate, the substrate having a first area and a second area, the first area being arranged around an outer periphery of the second area;

[0008] A plurality of first solder balls are provided in the first region and arranged in a plurality of rows and columns in the first region, the first solder balls in two adjacent rows are arranged in a staggered manner, the spacing between the centers of two adjacent first solder balls in the same column is a first spacing D1, the spacing between the centers of two adjacent first solder balls in the same row is a second spacing D2, and D1 and D2 satisfy: D1≥D pad+2W1+2W2+W3, and D2≥D pad +2W1+2W2+W3, where D pad is the pad diameter, W1 is the lead width; W2 represents the distance from the lead to the adjacent pad; W3 is the lead spacing; and

[0009] A plurality of second solder balls are disposed in the second area and arranged in a rectangular array in the second area.

[0010] Compared with arranging the solder balls in a rectangular array as a whole, the present application arranges the first solder balls in a staggered manner, which can increase the ball spacing between the first solder balls in the same column and the same row. The first spacing between two adjacent first solder balls in the same column and the second spacing between two adjacent first solder balls in the same row are both sufficient to fan out at least two leads, thereby increasing the number of leads that can be fanned out between adjacent first solder balls, increasing the number of leads that can be fanned out from the surface layer of the PCB board, thereby reducing the number of leads that need to be fanned out from the inner layer of the PCB board by punching, reducing the number of required inner layers of the PCB board, and thus reducing the thickness and cost of the PCB board.

[0011] In some embodiments, the first distance D1 and the second distance D2 satisfy: D1 ≥ D pad +3W1+2W2+2W3, and D2≥D pad +3W1+2W2+2W3, where D pad is the pad diameter, W1 is the lead width; W2 represents the distance from the lead to the adjacent pad; W3 is the lead spacing.

[0012] This arrangement allows at least three leads to be fanned out between two adjacent first solder balls in the same column, and at least three leads to be fanned out between two adjacent first solder balls in the same row, further increasing the number of leads that can be fanned out from the surface of the PCB board and reducing the thickness of the PCB board.

[0013] In some embodiments, a distance between the first solder ball and the center of the first solder ball adjacent to an adjacent column and adjacent row is a third distance D3, satisfying: D3<D1, and D3<D2.

[0014] By setting the relative size of the third spacing to the first spacing and the second spacing, the row spacing between adjacent rows and the column spacing between adjacent columns can be reduced, and the space on the substrate 1 can be fully utilized. More solder balls can be arranged on a substrate of the same size.

[0015] In some embodiments, the third distance D3 satisfies: D3 ≥ D pad +W1+2W2, where D pad is the pad diameter, W1 is the lead width; W2 is the distance from the lead to the adjacent pad.

[0016] With this arrangement, at least one lead can be fanned out between a first solder ball and its adjacent column and adjacent first solder balls in an adjacent row, thereby facilitating fanning out the leads of solder balls in the row within the first region.

[0017] In some implementations, the first solder balls in a row are arranged at equal intervals, and the first solder balls in a column are arranged at equal intervals.

[0018] This arrangement makes the first solder balls in each row and column evenly distributed, making it easier to form the first solder balls on the substrate.

[0019] In some embodiments, the first solder ball is disposed on a perpendicular bisector of a line connecting centers of two adjacent first solder balls in an adjacent row.

[0020] The above arrangement makes the distance between the first solder ball and two adjacent first solder balls in an adjacent row equal, and the first solder balls are arranged more regularly in the first area, which facilitates the arrangement of the first solder balls in the first area.

[0021] In some embodiments, within the first region, centers of the first solder balls in the outermost circle are sequentially connected to form a polygonal contour line, and each inner angle of the polygonal contour line is an obtuse angle.

[0022] Since the inner angles of the polygonal contour line are all obtuse angles, the first solder balls at the corners of the substrate are arranged tilted, and the centers of the tilted first solder balls are located on the same straight line. No solder balls are arranged outside the tilted first solder balls, so that the corners of the substrate have blank areas where no solder balls are set, thereby preventing the chip from warping and causing solder joint failure.

[0023] In some embodiments, the substrate further has a third region disposed between the first region and the second region, and the third region is disposed around the outer periphery of the second region; a distance between an outer boundary line of the third region and an adjacent inner boundary line is L, L≥1mm.

[0024] By setting the third area between the first area and the second area, without setting solder balls on the third area, and with a large spacing between the outer boundary line of the third area and the adjacent inner boundary line, there is sufficient space on the PCB board corresponding to the third area to place electronic components with larger capacitance.

[0025] Another aspect of the present application is to provide a printed circuit board for connecting to the above-mentioned packaging structure, wherein the printed circuit board includes a board body, and the board body is provided with a plurality of solder pads and a plurality of through holes; the plurality of solder pads are respectively used to be connected to the first solder balls and the second solder balls on the packaging structure in a one-to-one correspondence; the leads of some of the solder pads are led out through the gap between two adjacent first solder balls on the surface layer of the board body; the plurality of through holes are arranged corresponding to another part of the solder pads, and the leads of the other part of the solder pads are led out through the corresponding through holes.

[0026] By optimizing the arrangement of the first solder ball and the second solder ball on the substrate, the number of leads led out through the surface of the board is increased, thereby reducing the number of layers required for the board, reducing the thickness of the board, and reducing the overall production cost of the printed circuit board.

[0027] In some embodiments, a plurality of first electronic components and a plurality of second electronic components are provided on the lower surface of the board body, wherein the plurality of first electronic components are distributed in an area on the board body corresponding to the second area of ​​the substrate, and the plurality of second electronic components are distributed in an area on the board body corresponding to the third area of ​​the substrate.

[0028] Since no solder balls are provided in the third area, the capacitance of the second electronic component can be greater than that of the first electronic component, thereby improving the low-frequency power performance of the board without sacrificing more solder balls or vias.

[0029] Compared with the prior art, the packaging structure and printed circuit board of the utility model embodiment have the following beneficial effects:

[0030] The packaging structure of the embodiment of the utility model includes a substrate, a plurality of first solder balls and a plurality of second solder balls. The first area of ​​the substrate is arranged around the outer peripheral side of the second area, the plurality of first solder balls are arranged in the first area, and the plurality of second solder balls are arranged in the second area. The second solder balls are arranged in a rectangular array in the second area to form a power supply solder ball area; the first solder balls are arranged in multiple rows and columns, and the first solder balls in two adjacent rows are arranged in a staggered manner. Compared with arranging the solder balls in a rectangular array as a whole, the present application arranges the first solder balls in a staggered manner, which can increase the ball spacing between the first solder balls in the same column and the same row, thereby increasing the number of leads that can be fanned out between adjacent first solder balls, so that more leads can be fanned out from the surface layer of the PCB board, thereby reducing the number of leads that need to be fanned out from the inner layer of the PCB board by punching, reducing the number of required inner layers of the PCB board, and thus reducing the thickness and cost of the PCB board.

[0031] Moreover, for substrates of the same size, the present application arranges the first solder balls in a staggered manner, which can increase the number of first solder balls arranged on the substrate, fully utilize the space on the substrate, and meet the needs of chip multi-signal arrangement and chip miniaturization development. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the arrangement of solder balls on a substrate in the prior art;

[0033] Figure 2 is a schematic diagram of the packaging structure described in the embodiment of the present application;

[0034] Figure 3 is a schematic diagram of the arrangement of the first solder ball and the second solder ball on the substrate in an embodiment of the present application;

[0035] Figure 4 yes Figure 3 A is an enlarged schematic diagram;

[0036] Figure 5 is a schematic diagram of the connection between the packaging structure and the printed circuit board described in the embodiment of the present application;

[0037] Figure 6 This is a diagram showing the corresponding relationship between the first electronic component, the second electronic component and the substrate in the embodiment of the present application.

[0038] Numbers in the figure:

[0039] 1. substrate; 11. first region; 12. second region; 13. third region;

[0040] 2. Solder ball; 3. First solder ball; 4. Second solder ball; 5. Lead; 6. Board; 61. Through hole; 7. First electronic component; 8. Second electronic component. DETAILED DESCRIPTION

[0041] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0042] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0043] The following is a further detailed description of the specific implementation of the present invention in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0044] See also Figure 2 - Figure 4 As shown, the embodiment of the utility model provides a packaging structure, including a substrate 1, a plurality of first solder balls 3 and a plurality of second solder balls 4, the substrate 1 has a first area 11 and a second area 12, the first area 11 is arranged around the outer peripheral side of the second area 12; the plurality of first solder balls 3 are arranged in the first area 11 and are arranged in multiple rows and columns in the first area 11, the first solder balls 3 in two adjacent rows are staggered, the spacing between the centers of two adjacent first solder balls 3 in the same column is a first spacing D1, the spacing between the centers of two adjacent first solder balls 3 in the same row is a second spacing D2, D1 and D2 satisfy: D1≥D pad +2W1+2W2+W3, and D2≥D pad +2W1+2W2+W3, where D pad is the pad diameter, W1 is the lead width; W2 represents the distance from the lead to the adjacent pad; W3 is the lead spacing; a plurality of second solder balls 4 are disposed in the second area 12 and arranged in a rectangular array in the second area 12 .

[0045] A plurality of second solder balls 4 are arranged in a rectangular array in the second area 12 to form a power solder ball area; the first solder balls 3 are arranged in multiple rows and columns, and the first solder balls 3 in two adjacent rows are arranged in a staggered manner. Compared with arranging the solder balls as a whole in a rectangular array, the present application arranges the first solder balls 3 in a staggered manner, which can increase the ball spacing between the first solder balls 3 in the same column and the same row. The first spacing between two adjacent first solder balls 3 in the same column and the second spacing between two adjacent first solder balls 3 in the same row are both sufficient to fan out at least two leads 5, thereby increasing the number of leads that can be fanned out between adjacent first solder balls 3, so that more leads can be fanned out from the surface layer of the PCB board, thereby reducing the number of leads that need to be fanned out from the inner layer of the PCB board by punching, reducing the number of required inner layers of the PCB board, and thus reducing the thickness and cost of the PCB board.

[0046] Moreover, for substrates 1 of the same size, the present application arranges the first solder balls 3 in a staggered manner, which can increase the number of first solder balls 3 arranged on the substrate 1, fully utilize the space on the substrate 1, and meet the needs of chip multi-signal arrangement and chip miniaturization development. Therefore, the present application can ensure high-density fan-out on the surface of the PCB board and achieve chip miniaturization by improving the arrangement of the first solder balls 3 on the substrate 1.

[0047] The substrate 1 in the present application is a BGA package substrate. The chip is packaged on the substrate 1, and the chip is a CPU chip, an MCU chip, a GPU chip, etc.

[0048] In some embodiments, a first distance D1 between the centers of two adjacent first solder balls 3 in the same column and a second distance D2 between the centers of two adjacent first solder balls 3 in the same row satisfy: D1≥D pad +3W1+2W2+2W3, and D2≥D pad +3W1+2W2+2W3, where D pad is the pad diameter, W1 is the lead width; W2 represents the distance from the lead to the adjacent pad; W3 is the lead spacing. This arrangement enables at least three leads to be fanned out between two adjacent first solder balls 3 in the same column, and at least three leads to be fanned out between two adjacent first solder balls 3 in the same row, further increasing the number of leads that can be fanned out from the surface layer of the PCB board, reducing the number of leads that need to be fanned out from the inner layer of the PCB board by punching, further reducing the number of inner layers of the PCB board, thereby reducing the thickness of the PCB board and meeting the miniaturization development requirements of the printed circuit board. In some embodiments, D1=D2. In other embodiments, D1 and D2 may also be unequal.

[0049] It should be noted that, in the present application, whether at least two leads 5 or at least three leads 5 can be led out between two adjacent first solder balls 3 in the same row or between two adjacent first solder balls 3 in the same column, these are the maximum number of leads that can be led out between two adjacent first solder balls 3. In actual use, one or more leads can be led out between two adjacent first solder balls 3 according to specific lead arrangement requirements. For example, when the first spacing D1 between the centers of two adjacent first solder balls 3 in the same column and the second spacing D2 between the centers of two adjacent first solder balls 3 in the same row can both meet the requirement of fanning out at least three leads, taking the first solder balls 3 in the outermost column as an example, in actual use, one lead, two leads, or three leads can be led out between the two adjacent first solder balls 3 in the outermost column.

[0050] See also Figure 3 and Figure 4As shown, in some embodiments, the spacing between the first solder ball 3 and the centers of the first solder balls 3 adjacent to the adjacent columns and adjacent rows is a third spacing D3, satisfying: D3<D1, and D3<D2. Compared with the solder balls arranged in a rectangular array, this arrangement can reduce the spacing between two first solder balls in adjacent rows and adjacent columns, thereby reducing the row spacing of adjacent rows and the column spacing of adjacent columns, making full use of the space on the substrate 1, and more solder balls can be arranged on the substrate 1 of the same size. Preferably, the third spacing D3 between the first solder ball 3 and the centers of the first solder balls 3 adjacent to the adjacent columns and adjacent rows satisfies: D3≥D pad +W1+2W2, where D pad is the pad diameter, W1 is the lead width; W2 represents the spacing from the lead to the adjacent pad. With this arrangement, at least one lead can be fanned out between the first solder ball 3 and its adjacent column and the adjacent first solder balls 3 in the adjacent row, which not only reduces the column spacing between adjacent columns and the row spacing between adjacent rows, but also does not interfere with the lead out of the corresponding first solder ball 3, thereby facilitating the fan out of the solder ball leads in the inner row of the first region 11.

[0051] In some embodiments, the lead width W1 and the distance W2 from the lead to the adjacent pad are both design specification values, W1 and W2 satisfy: W1 = W2, and W1 and W2 are both equal to the distance W4 between the pad and the through hole. In the present application, the distance between the first solder ball 3 and the through hole 61 is the fourth distance D4, and D4 satisfies: D4 ≥ W4. In this embodiment, D pad =350mm, W1=W2=W4=75mm, D3=630mm, D1=1020mm, D2=740mm.

[0052] It should be noted that the distance between the centers of two adjacent first solder balls 3 in the same row is the second distance D2 when D2≥D pad +2W1+2W2+W3, and D4≥W4, the number of fan-out leads can be set according to actual needs.

[0053] In some embodiments, the first solder balls 3 in the same row are arranged at equal intervals, and the first solder balls 3 in the same column are arranged at equal intervals, so that the first solder balls 3 in the same row and the first solder balls 3 in the same column are evenly arranged, which facilitates the manufacturing and forming of the first solder balls 3 on the substrate 1.

[0054] In some embodiments, the first solder ball 3 is arranged on the perpendicular bisector of the center line connecting the two adjacent first solder balls 3 in the adjacent row, so that the distance between the first solder ball 3 and the two adjacent first solder balls 3 in the adjacent row is equal, which facilitates the arrangement of the first solder ball 3 in the first area 11.

[0055] See also Figure 3As shown, in some embodiments, in the first region 11, the centers of the first solder balls 3 in the outermost circle are connected in sequence to form a polygonal contour line, and each inner angle of the polygonal contour line is an obtuse angle, so that each corner position on the substrate 1 has a blank area without a solder ball, so as to avoid chip warping and solder joint failure. The first solder balls at each corner position of the substrate 1 are arranged obliquely, and the centers of the first solder balls arranged obliquely at the same corner are located on the same straight line, forming the edge of the polygonal contour line. Figure 3 As shown, the centers of the first solder balls 3 in the outermost circle of the first region 11 are connected in sequence to form an octagonal outline, and each inner angle of the octagonal outline is an obtuse angle. Figure 3 The orientation shown is used as a reference for description. Two first solder balls 3 are arranged obliquely at the upper left corner and the upper right corner of the substrate 1, and the connecting lines of the solder ball centers form two sides of the octagonal outline. Three first solder balls 3 are arranged obliquely at the lower left corner and the lower right corner of the substrate 1, and the connecting lines of the solder ball centers form two sides of the octagonal outline. The connecting lines of the centers of the two rows of solder balls at the upper and lower sides of the substrate 1 form two sides of the octagonal outline. The connecting lines of the centers of the two rows of solder balls at the leftmost and the rightmost sides of the substrate 1 form two sides of the octagonal outline.

[0056] In some embodiments, the substrate 1 further has a third region 13, the third region 13 is disposed between the first region 11 and the second region 12, and the third region 13 is disposed around the outer periphery of the second region 12; the spacing between the outer boundary line of the third region 13 and its adjacent inner boundary line is L, and L ≥ 1 mm. The first region 11 and the second region 12 are spaced apart, the third region 13 is located between the first region 11 and the second region 12, no solder balls are disposed on the third region 13, and the spacing between the outer boundary line of the third region 13 and the adjacent inner boundary line is large, so that the position corresponding to the third region 13 on the PCB board has enough space to place electronic components with larger capacitance. Compared with the arrangement of the solder balls on the entire substrate 1 in a rectangular array, the total number of solder balls arranged in the first area 11 and the second area 12 of the present application increases. Even if a third area 13 without solder balls is reserved between the first area 11 and the second area 12, the distance between the first solder ball 3 in the first area 11 and the second solder ball 4 in the second area 12 is increased, and a capacitor with a larger capacitance can be placed in the third area 13. The large capacitor can improve the low-frequency power supply performance of the PCB board. For the arrangement of the solder balls on the entire substrate 1 in a rectangular array in the prior art, if a blank area without solder balls is reserved on the substrate, the number of solder balls on the substrate will be less. In order to meet the multi-signal arrangement requirements on the chip, it is necessary to increase the number of solder balls by increasing the size of the substrate, which will increase the chip manufacturing cost.

[0057] In some embodiments, the second solder balls 4 in the second area 12 are arranged in a square array, corresponding to various core module power supplies, such as VDD power supply, GPU power supply, etc. The second solder balls 4 in the same row are equally spaced, and the second solder balls 4 in the same column are equally spaced. The spacing between two adjacent second solder balls 4 in the same row is equal to the spacing between two adjacent second solder balls 4 in the same column, and both are smaller than the first spacing and the second spacing. A first electronic component 7 can be placed in the position area corresponding to the second area 12 on the PCB board, and a second electronic component 8 can be placed in the position area corresponding to the third area 13 on the PCB board. The first electronic component 7 and the second electronic component 8 are both capacitors. The capacitance value of the first electronic component 7 is smaller than the capacitance value of the second electronic component 8. For example, the first electronic component is a 0201 capacitor, and the second electronic component is a 0402 capacitor.

[0058] In some embodiments, the first region 11, the third region 13 and the second region 12 are sequentially arranged from outside to inside on the substrate 1. The first region 11 and the third region 13 are both rectangular ring-shaped, and the second region 12 is rectangular.

[0059] When making the package structure of the present application, first make it clear that the chip heat dissipation design power consumption is low power consumption. Then divide the area on the substrate 1, and divide the area on the substrate 1 into a first area 11, a second area 12 and a third area 13. Set the number of rows and columns of solder balls in the first area 11 and the second area 12 according to the type of signal and the number of solder balls in the module planning signal area, and adjust the spacing L between the outer boundary line of the third area 13 and its adjacent inner boundary line according to the required capacitor type. According to the number of leads that need to be fanned out on the surface of the PCB board, arrange the spacing of the first solder ball 3 and the spacing of the second solder ball 4, etc. It should be noted that the number of the first solder balls 3 can be adjusted according to the type, number, and type of signals in different projects, and VSS allocation can be performed to the first solder balls 3 according to signal requirements.

[0060] See also Figure 5 and Figure 6 As shown, the present application also provides a printed circuit board for connecting with the above-mentioned packaging structure, and the printed circuit board includes a board body 6, which is the above-mentioned PCB board. The board body 6 is provided with a plurality of pads (not shown in the figure) and a plurality of through holes 61; the plurality of pads are respectively used to be connected with the first solder balls 3 and the second solder balls 4 on the packaging structure in a one-to-one correspondence; the leads 5 of some pads are led out through the gap between two adjacent first solder balls 3 on the surface layer of the board body 6; the plurality of through holes 61 are arranged corresponding to another portion of pads, and the leads 5 of the other portion of pads are led out through the through holes 61 corresponding thereto.

[0061] By optimizing the arrangement of the first solder ball 3 and the second solder ball 4 on the substrate 1, the number of leads led out through the surface layer of the board body 6 is increased, and the number of leads led out through 61 is reduced, thereby reducing the number of layers required for the board body 6, reducing the thickness of the board body 6, and reducing the overall production cost of the printed circuit board.

[0062] In some embodiments, in the first area 11 on the substrate 1, the first solder ball 3 and the adjacent two first solder balls 3 in the adjacent row and adjacent column are arranged in a triangle, and the through hole 61 can be set at the center of the area corresponding to the triangular area on the board 6. One through hole 61 can correspond to one pad or multiple pads. The number of pads corresponding to one through hole 61 depends on the type of solder ball connected to the pad.

[0063] See also Figure 5 and Figure 6 As shown, the lower surface of the board body 6 is provided with a plurality of first electronic components 7 and a plurality of second electronic components 8. The plurality of first electronic components 7 are distributed in the area corresponding to the second area 12 of the substrate 1 on the board body 6, and the plurality of second electronic components 8 are distributed in the area corresponding to the third area 13 of the substrate 1 on the board body 6. The first electronic component 7 is arranged in an area corresponding to the second area 12 on the substrate 1, and the second electronic component 8 is arranged in the third area 13. Since the third area 13 is not provided with solder balls, the capacitance of the second electronic component 8 can be greater than the capacitance of the first electronic component 7, thereby improving the low-frequency power supply performance of the board body without sacrificing more solder balls or vias. The first electronic component 7 and the second electronic component 8 are both capacitors. The capacitance of the first electronic component 7 is less than the capacitance of the second electronic component 8. For example, the first electronic component is a 0201 capacitor, and the second electronic component is a 0402 capacitor. The plurality of first electronic components 7 are arranged in a rectangular array in the area corresponding to the second area 12. The plurality of second electronic components 8 are arranged at intervals along the circumference of the area corresponding to the third area 13.

[0064] In summary, the embodiment of the utility model provides a packaging structure and a printed circuit board, wherein the second solder balls 4 are arranged in a rectangular array in the second area 12 to form a power solder ball area; the first solder balls 3 are arranged in multiple rows and columns, and the first solder balls 3 in two adjacent rows are arranged in a staggered manner. Compared with arranging the solder balls as a whole in a rectangular array, the present application arranges the first solder balls 3 in a staggered manner, which can increase the ball spacing between the first solder balls 3 in the same column and the same row, thereby increasing the number of leads that can be fanned out between adjacent first solder balls 3, so that more leads can be fanned out from the surface layer of the PCB board, thereby reducing the number of leads that need to be fanned out from the inner layer of the PCB board by punching, reducing the number of inner layers of the PCB board required, thereby reducing the thickness and cost of the PCB board. In addition, for substrates of the same size, the present application arranges the first solder balls 3 in a staggered manner, which can increase the number of first solder balls 3 arranged on the substrate, make full use of the space on the substrate, and meet the needs of chip multi-signal arrangement and chip miniaturization development at the same time. Furthermore, two different types of electronic components can be arranged under the body 6 of the printed circuit board, so that electronic components with larger capacitance can be placed on the printed circuit board without occupying more solder balls in the power core area and sacrificing vias, thereby avoiding a reduction in the number of capacitors and vias, and solving the problem of capacitor filtering of small chips to a certain extent.

[0065] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and substitutions can be made without departing from the technical principle of the present invention. These improvements and substitutions should also be regarded as the protection scope of the present invention.

Claims

1. A packaging structure, characterized in that: include: A substrate (1), the substrate (1) comprising a first region (11) and a second region (12), the first region (11) being arranged around the outer periphery of the second region (12); A plurality of first solder balls (3) are provided in the first area (11) and arranged in a plurality of rows and columns in the first area (11); the first solder balls (3) in two adjacent rows are arranged in a staggered manner; the distance between the centers of two adjacent first solder balls (3) in the same column is a first distance D1; the distance between the centers of two adjacent first solder balls (3) in the same row is a second distance D2; D1 and D2 satisfy: D1≥D pad +2W1+2W2+W3, and D2≥D pad +2W1+2W2+W3, where D pad is the pad diameter, W1 is the lead width; W2 represents the distance from the lead to the adjacent pad; W3 is the lead spacing; as well as A plurality of second solder balls (4) are disposed in the second area (12) and are arranged in a rectangular array in the second area (12).

2. The packaging structure according to claim 1, characterized in that: The first distance D1 and the second distance D2 satisfy: D1 ≥ D pad +3W1+2W2+2W3, and D2≥D pad +3W1+2W2+2W3, where D pad is the pad diameter, W1 is the lead width; W2 represents the distance from the lead to the adjacent pad; W3 is the lead spacing.

3. The packaging structure according to claim 1 or 2, characterized in that: The distance between the first solder ball (3) and the centers of the first solder balls (3) adjacent to the first solder balls (3) in adjacent columns and adjacent rows is a third distance D3, satisfying: D3<D1, and D3<D2.

4. The packaging structure according to claim 3, characterized in that: The third distance D3 satisfies: D3 ≥ D pad +W1+2W2, where D pad is the pad diameter, W1 is the lead width; W2 is the distance from the lead to the adjacent pad.

5. The packaging structure according to claim 1, characterized in that: The first solder balls (3) in the same row are arranged at equal intervals, and the first solder balls (3) in the same column are arranged at equal intervals.

6. The packaging structure according to claim 5, characterized in that: The first solder ball (3) is arranged on the perpendicular midline of a line connecting the centers of two adjacent first solder balls (3) in an adjacent row.

7. The packaging structure according to claim 1, characterized in that: In the first area (11), the centers of the first solder balls (3) in the outermost circle are connected in sequence to form a polygonal contour line, and each inner angle of the polygonal contour line is an obtuse angle.

8. The packaging structure according to claim 1, characterized in that: The substrate (1) further comprises a third region (13) which is arranged between the first region (11) and the second region (12), and the third region (13) is arranged around the outer periphery of the second region (12); the spacing between the outer boundary line of the third region (13) and its adjacent inner boundary line is L, and L is ≥ 1 mm.

9. A printed circuit board, used for connecting to the packaging structure according to any one of claims 1 to 8, characterized in that: The printed circuit board comprises a board body (6), The board body (6) is provided with a plurality of solder pads and a plurality of through holes (61); the plurality of solder pads are respectively used for one-to-one connection with the first solder balls (3) and the second solder balls (4) on the packaging structure; the leads (5) of some of the solder pads are led out through the gap between two adjacent first solder balls (3) on the surface layer of the board body (6); the plurality of through holes (61) are arranged corresponding to another portion of the solder pads, and the leads (5) of the other portion of the solder pads are led out through the corresponding through holes (61).

10. The printed circuit board according to claim 9, characterized in that: A plurality of first electronic components (7) and a plurality of second electronic components (8) are provided on the lower surface of the plate body (6); the plurality of first electronic components (7) are distributed in an area on the plate body (6) corresponding to the second area (12) of the substrate (1); and the plurality of second electronic components (8) are distributed in an area on the plate body (6) corresponding to the third area (13) of the substrate (1).

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