Copper-clad ceramic substrate with novel bonding wire staggered layout
By adopting a new type of bond wire misalignment layout on the copper-clad ceramic substrate, the thermal stress increase caused by the excessive concentration of the connection points between the metal bond wire and the chip is solved, the effect of reducing current density and temperature is achieved, and the fatigue life of the power device is improved.
Patent Information
- Application Number
- CN202421605523.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-08
- Publication Date
- 2025-04-29
- Estimated Expiration
- 2034-07-08
AI Technical Summary
In the prior art, since the connection points between the metal bond wire and the chip are too concentrated, the thermal stress in the metal area on the upper layer of the chip increases, resulting in fatigue fracture and falling off at the connection points between the metal bond wire and the chip.
By adopting a new type of bonding wire misalignment layout, by distributing multiple metal bonding wires in the first direction and providing a layout with a preset angle in the second direction, the spacing between two adjacent first connection points is increased, and the density of the surface bonding points in the source metal region is reduced.
The current distribution density and chip temperature of the chip metal region are effectively reduced, the thermal stress in the metal bonding region on the upper layer of the chip is reduced, the first connection point is more stable, and the fatigue life of the power device is improved.
Smart Images
Figure CN222813594U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of semiconductor wire bonding, in particular to a copper-clad ceramic substrate with a novel bonding wire staggered layout. Background Art
[0002] Power devices generally use ultrasonic bonding to connect metal bonding wires to the upper metal area of the chip and the copper layer on the copper-clad ceramic substrate to complete the electrical connection. Power devices are usually tested for life according to the requirements of AQG 324. As the voltage level and power of power devices increase, the junction temperature of the chip inside them also gradually increases. The connection stability and reliability of the metal bonding wires and the upper metal area of the chip become the bottleneck for improving the fatigue life of power devices.
[0003] The prior art is to keep the metal bonding wires neatly arranged up and down, left and right, with consistent up and down spacing and consistent lengths of the metal bonding wires, such as Figure 1 As shown, or the required number of single metal wires are bonded to the chip surface in sequence, Figure 3 As shown. The advantages of doing so are: the programming of the bonding equipment is relatively simple, and the bonding wires are neat and uniform and more beautiful. However, such distribution of metal bonding wires will result in a small and dense distance between the connection points between the metal bonding wires and the chip, resulting in excessive concentration of current density on the surface of the upper metal area of the chip, causing the temperature of the upper metal area of the chip to rise, increasing the thermal stress of the upper metal bonding area of the chip, and causing fatigue fracture and falling off at the connection points between the metal bonding wires and the chip, which is not conducive to improving the fatigue life of the power device. Therefore, it is necessary to improve the layout of the bonding wires. Utility Model Content
[0004] The utility model provides a copper-clad ceramic substrate with a novel staggered bonding wire layout, which solves the problem in the above-mentioned background technology that the thermal stress of the upper metal bonding area of the chip is increased due to the excessive concentration of bonding points, thereby causing fatigue fracture and falling off at the connection points between the metal bonding wires and the chip.
[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:
[0006] A copper-clad ceramic substrate with a novel bonding wire staggered layout, comprising:
[0007] The substrate body is provided with a ceramic layer, and an upper copper layer is provided on the ceramic layer;
[0008] A chip is arranged on the upper copper layer, and a first source metal region is arranged on the surface of the chip;
[0009] At least one group of bonding wires, comprising a plurality of metal bonding wires spaced apart along a first direction, wherein the first ends of the plurality of metal bonding wires are connected to a first source metal region of the chip, the plurality of metal bonding wires and the source metal region form a plurality of first connection points, the second ends of the plurality of metal bonding wires are connected to another upper copper layer spaced apart, the plurality of metal bonding wires and the upper copper layer form a plurality of second connection points, wherein a first connection line between two adjacent first connection points is provided with a preset angle with the second direction, and the second direction is perpendicular to the first direction.
[0010] In some embodiments, the first connection points of any two spaced-apart metal bonding wires are on the same straight line, and the straight line is parallel to the second direction, so as to form a staggered distribution of the first connection points.
[0011] In some embodiments, the first connection points of the plurality of metal bonding wires are distributed close to two edges of the first source metal region in the first direction.
[0012] In some embodiments, a second source metal region is further included, wherein the second source metal region and the first source metal region are symmetrically arranged in a second direction, and a plurality of the metal bonding wires and the second source metal region are provided with a plurality of third connection points.
[0013] In some embodiments, the first connection points and the third connection points located on the same metal bonding line have the same first spacing in the first direction, so that the third connection points are staggered in the second source metal region.
[0014] In some embodiments, the second connection points and the third connection points located on the same metal bonding line have the same second spacing in the first direction, so that the second connection points are distributed at intervals on adjacent upper copper layers.
[0015] In some embodiments, a plurality of metal bonding wires in at least one group of bonding wires are arranged in parallel along a first direction.
[0016] In some embodiments, the distances between two adjacent metal bonding wires in the second direction are the same.
[0017] In some embodiments, when there are two bonding wire groups, the distribution structure of the first connection points formed between the two bonding wire groups and the source metal region is the same, the metal bonding wires of the first bonding wire group are located above the metal bonding wires of the second bonding wire group, and the two first connection points formed by the metal bonding wires corresponding to the first bonding wire group and the second bonding wire group and the first source metal region are arranged at a preset distance in the first direction.
[0018] In some embodiments, the two metal bonding wires corresponding to the first bonding wire group and the two metal bonding wires corresponding to the second bonding wire group are arranged with the same spacing.
[0019] Compared with the prior art, the beneficial effects brought by the utility model are:
[0020] The present application arranges multiple metal bonding wires of the bonding wire group and the source metal area of the chip in a staggered manner, mainly in that the multiple metal bonding wires are arranged at intervals along the first direction, and the first connection line between two adjacent first connection points is provided with a preset angle in the second direction, and the second direction is perpendicular to the first direction, thereby increasing the spacing between two adjacent first connection points and reducing the density of bonding points on the surface of the source metal area, thereby reducing the current distribution density and chip temperature of the chip metal area, which can effectively reduce the thermal stress of the upper metal bonding area of the chip and make the first connection point more stable.
[0021] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 A first wiring method of metal bonding wires in the prior art;
[0023] Figure 2 It is a first wiring method of a copper-clad ceramic substrate with a novel bonding wire staggered layout of the utility model;
[0024] Figure 3 A second wiring method of metal bonding wires in the prior art;
[0025] Figure 4 It is a second wiring method of a copper-clad ceramic substrate with a novel bonding wire staggered layout of the utility model;
[0026] Figure 5 It is a cross-sectional view of a copper-clad ceramic substrate with a novel staggered bonding wire layout in a first direction according to the utility model;
[0027] Figure 6 It is a schematic diagram of the first structural distribution of the source metal area of a copper-clad ceramic substrate with a novel bonding wire staggered layout according to the utility model;
[0028] Figure 7 This is a schematic diagram of the second structural distribution of the source metal area of a copper-clad ceramic substrate with a novel bonding wire staggered layout according to the utility model. DETAILED DESCRIPTION
[0029] The present application is further described in detail below in conjunction with specific drawings. In the description of this embodiment, unless otherwise specified, the terms "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the present application must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present application.
[0030] like Figure 2 and Figure 4 As shown, a copper-clad ceramic substrate with a novel bonding wire staggered layout provided by the utility model mainly includes a substrate body, a ceramic layer 4, an upper copper layer 3 is provided on the ceramic layer 4, and specifically, in this embodiment, the substrate body also includes a lower copper layer 5 arranged on the lower side of the ceramic layer 5, such as Figure 5 As shown. The chip 2 is fixed on the upper copper layer 3 by sintering, and a first source metal area 21 for electrical connection is provided on the chip 2, and at least one group of bonding wires includes a plurality of metal bonding wires 1 arranged at intervals along a first direction X, and the first ends of the plurality of metal bonding wires 1 are fixedly connected to the first source metal area 21 of the chip, and a plurality of first connection points 11 are formed on the first source metal area 21, and the second ends of the plurality of metal bonding wires 1 are fixedly connected to another upper copper layer 3 distributed at intervals to realize the transmission of electrical signals inside the chip 2, and the plurality of metal bonding wires 1 and the upper copper layer 3 form a plurality of second connection points 12, wherein the first connection line between two adjacent first connection points 11 and the straight line where the second direction Y is located are provided with a preset angle α, as shown in FIG. Figure 7 As shown, two adjacent first connection points 11 are arranged at a distance in the first direction X, so that the spacing between multiple first connection points 11 is maximized on the first source metal region 21 within a limited range, which can effectively avoid excessive current concentration causing higher temperature on the surface of the chip 2, avoid the generation of large thermal stress, protect the stability of the first connection point 11, and thus ensure the fatigue life of the power module.
[0031] In one embodiment, the first connection points 11 of any two spaced metal bonding wires 1 are on the same straight line, and the straight line is parallel to the straight line in the second direction Y, so that the first connection points 11 are staggered in the first source metal region 21. Specifically, from top to bottom in the second direction Y, the first connection points 11 of the first, third, fifth, etc. odd-numbered metal bonding wires are on a straight line, and the first connection points 11 of the second, fourth, sixth, etc. even-numbered metal bonding wires 1 are on a straight line, and the first, third, fifth, etc. odd-numbered first connection points 11 and the second, fourth, sixth, etc. even-numbered first connection points 11 have a certain distance in the second direction Y, that is, the spacing between two adjacent first connection points 11 is maximized on the first source metal region 21 of a limited area, thereby avoiding current concentration.
[0032] Furthermore, the first connection points 11 of the plurality of metal bonding wires 1 are distributed along two edges of the first source metal region 21 in the first direction X. Through such a layout, the distance between two adjacent first connection points 11 in the first direction X is maximized, thereby maximizing the distance between two adjacent first connection points 11.
[0033] In one embodiment, Figure 6 and Figure 7 As shown, it also includes a second source metal region 22, and the second source metal region 22 and the first source metal region 21 are symmetrically arranged in the second direction Y, that is, the symmetry axes of the second source metal region 22 and the first source metal region 21 are parallel to the straight line where the second direction Y is located. Multiple metal bonding wires 1 and the second source metal region 22 are provided with multiple third connection points 13. By arranging symmetrical first source metal regions 21 and second source metal regions 22 on the chip 2, it is possible to achieve uniform force on the connection layer between the chip 2 and the upper copper layer 3, thereby improving the stability of the chip 2 arranged on the upper copper layer 3 through the connection layer. Furthermore, in order to avoid dense distribution of multiple third connection points 13 on the second source metal region 22, the first connection points 11 and the third connection points 13 located on the same metal bonding wire 1 have the same first spacing 14 in the first direction X, so that the third connection points 13 are staggeredly distributed in the second source metal region 22. In this embodiment, reference Figure 7 As shown, the distribution structure of the third connection points 13 is the same as that of the first connection points 11, as mentioned above, and no further details are given here. Optionally, the second source metal region 22 and the first source metal region 21 can also be arranged as a whole.
[0034] In one embodiment, in order to ensure that the second connection points 12 are staggered and spaced on the upper copper layer 3, the second connection points 12 and the third connection points 13 on the same metal bonding wire 1 have the same second spacing 15 in the first direction X, so that the second connection points 12 are spaced and distributed on adjacent upper copper layers 3. The distribution method of the plurality of second connection points 12 is the same as the distribution method of the plurality of first connection points 11, and will not be described in detail here. As a variant implementation of this embodiment, if the distance between the third connection point 13 and the second connection point 12 in the first direction X is large, such as Figure 7 As shown in the direction, the first, third, fifth, etc. odd-numbered second connection points 12 counted from top to bottom in the second direction Y can also be arranged close to the right side, and the second, fourth, sixth, etc. even-numbered second connection points 12 can be arranged close to the left side.
[0035] In one embodiment, multiple metal bonding wires 1 of at least one bonding wire group are arranged in parallel along a first direction X to ensure the spacing between two adjacent metal bonding wires 1 and avoid the metal bonding wires 1 being too close to each other; further, multiple metal bonding wires 1 of at least one bonding wire group are spaced apart in a second direction Y, and the spacing between two adjacent metal bonding wires 1 is the same, so that the multiple metal bonding wires 1 are reasonably arranged in a limited space to avoid concentrated distribution of multiple first connection points 11, second connection points 12 and third connection points 13, and at the same time, multiple adjacent metal bonding wires 1 are provided with the same spacing in space.
[0036] In one embodiment, a second bonding wire group is further included. When there are two bonding wire groups, the distribution structure of the first connection points 11 formed between the two bonding wire groups and the first source metal region 21 is the same, the metal bonding wires 1 of the first bonding wire group are located above the metal bonding wires 1 of the second bonding wire group, and the metal bonding wires 1 corresponding to the first bonding wire group and the second bonding wire group are provided with a preset distance between the two first connection points 11 formed with the first source metal 21 region in the first direction X. Further, the two metal bonding wires 1 corresponding to the first bonding wire group and the second bonding wire group are provided with the same spacing, and the metal bonding wires 1 corresponding to the first bonding wire group and the second bonding wire group are overlapped in projection on the first source metal region 21.
[0037] The above is only a preferred embodiment of the present invention. It should be noted that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be considered as the protection scope of the present invention.
Claims
1. A copper-clad ceramic substrate with a novel bonding wire staggered layout, characterized in that: include: The substrate body is provided with a ceramic layer, and an upper copper layer is provided on the ceramic layer; A chip is arranged on the upper copper layer, and a first source metal region is arranged on the surface of the chip; At least one group of bonding wires, comprising a plurality of metal bonding wires spaced apart along a first direction, wherein the first ends of the plurality of metal bonding wires are connected to a first source metal region of the chip, the plurality of metal bonding wires and the source metal region form a plurality of first connection points, the second ends of the plurality of metal bonding wires are connected to another upper copper layer spaced apart, the plurality of metal bonding wires and the upper copper layer form a plurality of second connection points, wherein a first connection line between two adjacent first connection points is provided with a preset angle with the second direction, and the second direction is perpendicular to the first direction.
2. A copper-clad ceramic substrate with a novel bonding wire staggered layout according to claim 1, characterized in that: The first connection points of any two spaced-apart metal bonding wires are on the same straight line, and the straight line is parallel to the second direction, so as to form a staggered distribution of the first connection points.
3. A copper-clad ceramic substrate with a novel bonding wire staggered layout according to claim 2, characterized in that: The first connection points of the plurality of metal bonding wires are distributed close to two edges of the first source metal region in the first direction.
4. The copper-clad ceramic substrate with a novel bonding wire staggered layout according to claim 2, characterized in that: It also includes a second source metal region, which is symmetrically arranged with the first source metal region in the second direction, and a plurality of the metal bonding wires and the second source metal region are provided with a plurality of third connection points.
5. The copper-clad ceramic substrate with a novel bonding wire staggered layout according to claim 4, characterized in that: The first connection point and the third connection point located on the same metal bonding line have the same first spacing in the first direction, so that the third connection point is staggeredly distributed in the second source metal region.
6. The copper-clad ceramic substrate with a novel bonding wire staggered layout according to claim 4, characterized in that: The second connection points and the third connection points located on the same metal bonding line have the same second spacing in the first direction, so that the second connection points are distributed at intervals on adjacent upper copper layers.
7. A copper-clad ceramic substrate with a novel bonding wire staggered layout according to any one of claims 1 to 6, characterized in that: A plurality of metal bonding wires of at least one bonding wire group are arranged in parallel along a first direction.
8. The copper-clad ceramic substrate with a novel bonding wire staggered layout according to claim 7, characterized in that: The distance between two adjacent metal bonding wires in the second direction is the same.
9. The copper-clad ceramic substrate with a novel bonding wire staggered layout according to claim 1, characterized in that: When there are two bonding wire groups, the distribution structure of the first connection points formed between the two bonding wire groups and the source metal region is the same, the metal bonding wires of the first bonding wire group are located above the metal bonding wires of the second bonding wire group, and the two first connection points formed by the metal bonding wires corresponding to the first bonding wire group and the second bonding wire group and the first source metal region are set at a preset distance in the first direction.
10. The copper-clad ceramic substrate with a novel bonding wire staggered layout according to claim 2, characterized in that: The same spacing is set between two metal bonding wires corresponding to the first bonding wire group and the second bonding wire group.