Integrated circuit packaging device, lead frame and power management circuit

Abstract

The utility model provides an integrated circuit chip packaging device, a lead frame and a power management circuit. The integrated circuit chip packaging device comprises an integrated circuit chip which comprises two or three of the following items: one or more control chips, one or more switch tubes and one or more patch devices; the lead frame comprises three or more slide holders for carrying the integrated circuit chip, and at least two pins which are respectively coupled to one of the three or more slide holders; and the packaging body is used for packaging the integrated circuit chip and the lead frame, and at least two pins extend to the outside of the packaging body. Compared with a similar structure, the integrated circuit chip packaging device disclosed by the utility model has the advantages of higher integration level, smaller size, better heat dissipation performance, lower manufacturing cost and the like, so that the integrated circuit chip packaging device is suitable for design packaging, large-scale manufacturing and application of power management type integrated circuit chips.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and more particularly to an integrated circuit chip packaging device, a lead frame, and a power management circuit. Background Art

[0002] The manufacturing process of integrated circuit chips mainly includes the following stages: the design stage of integrated circuit chips, the production stage of integrated circuit chips, the packaging stage of integrated circuit chips, and the testing stage of integrated circuit chips. When the integrated circuit chip is manufactured, there are usually multiple pads on the integrated circuit chip. In the packaging stage of the integrated circuit chip, these pads on the integrated circuit chip are usually electrically connected to the corresponding lead frame. The integrated circuit chip is usually connected to the lead frame through adhesive (conductive or insulating) or solder paste, welding wire, or ball bonding, so that these pads of the integrated circuit chip are electrically connected to the contacts of the lead frame, thereby realizing the electrical connection inside the packaging structure of the integrated circuit chip.

[0003] As power integrated circuit chips are increasingly used, how to achieve miniaturized packaging of integrated circuit chips with high heat dissipation performance has become a common concern in the semiconductor industry. Summary of the invention

[0004] Embodiments of the present disclosure provide a novel integrated circuit chip package device, a lead frame used in the package device, and a power management circuit including the integrated circuit chip package device.

[0005] One aspect of the present disclosure provides an integrated circuit chip packaging device. The integrated circuit chip packaging device includes: an integrated circuit chip, including two or three of the following items: one or more control chips, one or more switch tubes, and one or more surface mount devices; a lead frame, including: three or more wafer carriers for carrying the integrated circuit chip, and at least two pins, each coupled to one of the three or more wafer carriers; and a package body, for packaging the integrated circuit chip and the lead frame, wherein at least two pins extend outside the package body.

[0006] Another aspect of the present disclosure provides a lead frame for an integrated circuit chip packaging device. The lead frame includes: three or more wafer carriers for carrying an integrated circuit chip, wherein the integrated circuit chip includes two or three of the following items: one or more control chips, one or more switch tubes, and one or more surface mount devices; and at least two pins, each coupled to one of the three or more wafer carriers.

[0007] Another aspect of the present disclosure provides a power management circuit using the above integrated circuit chip packaging device.

[0008] Compared with similar structures, the integrated circuit chip packaging device according to the present invention has the advantages of higher integration, smaller size, better heat dissipation performance, lower manufacturing cost, etc., and is therefore suitable for the design packaging, large-scale manufacturing and application of power management integrated circuit chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure may be better understood from the following description of specific embodiments thereof taken in conjunction with the accompanying drawings, in which like reference characters generally refer to the same parts throughout the different views.

[0010] Figure 1A A top view of an integrated circuit chip package device according to an embodiment of the present disclosure is shown.

[0011] Figure 1B Shows Figure 1A The integrated circuit chip packaging device shown in the figure is used Figure 2A The lead frame shown is a cross-sectional view along AA.

[0012] Figure 1C Shows Figure 1A The integrated circuit chip packaging device shown in the figure is used Figure 2A The lead frame shown is another cross-sectional view along AA.

[0013] Figure 2A It shows that it can be applied to Figure 1A A top view of an example lead frame for an integrated circuit chip package is shown.

[0014] Figure 2B Shows Figure 2A The example lead frame is shown in cross-section along BB.

[0015] Figure 2C Shows Figure 2A Another cross-sectional view of the example lead frame along line BB is shown.

[0016] Figure 3A Shown in Figure 2A An example arrangement of glue locking holes in an example lead frame.

[0017] Figure 3B Shown in Figure 2A An example arrangement of silver plated areas is provided in an example lead frame.

[0018] Figure 4A It shows that it can be applied to Figure 1A A top view of another example lead frame of an integrated circuit chip package is shown.

[0019] Figure 4B Shown in Figure 4AAn example arrangement of glue locking holes and / or silver plated areas in an example lead frame.

[0020] Figure 5A A top view of an example internal package structure of an integrated circuit chip package device according to an embodiment of the present disclosure is shown.

[0021] Figure 5B A top view of another example internal packaging structure of an integrated circuit chip package device according to an embodiment of the present disclosure is shown.

[0022] Figure 6 An exemplary circuit diagram of applying an integrated circuit chip packaging device according to an embodiment of the present disclosure to a power management circuit is shown. DETAILED DESCRIPTION

[0023] The features and exemplary embodiments of various aspects of the present disclosure will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present disclosure by illustrating the examples of the present disclosure. The present disclosure is by no means limited to any specific structure, element and configuration proposed below, but covers any modification, replacement and improvement of the structure, element and configuration without departing from the spirit of the present disclosure. In the accompanying drawings and the following description, known structures and technologies are not shown to avoid unnecessary ambiguity in the present disclosure.

[0024] As power integrated circuit chips are increasingly used, how to achieve miniaturized, highly integrated, and highly heat-dissipating integrated circuit chip packaging has become a common concern in the semiconductor industry. In view of this problem, the present disclosure provides a novel integrated circuit chip packaging device, a lead frame used in the packaging device, and a power management circuit including the integrated circuit chip packaging device.

[0025] Figure 1A A top view of an integrated circuit chip package apparatus 100 according to an embodiment of the present disclosure is shown.

[0026] refer to Figure 1A The integrated circuit chip packaging device 100 includes a package body 110, a lead frame 120, and an integrated circuit chip (packaged inside, not shown in the figure). The integrated circuit chip packaging device 100 is, for example, a patch structure. The patch structure is applicable to both the traditional reflow soldering process of assembly factories such as printed circuit board assembly (PCBA) and the wave soldering process traditionally used for plug-in structures. It can be applied to assembly patches in various large, medium and small assembly and processing factories, greatly reducing assembly costs.

[0027] The package body 110 is used to package the lead frame 120 and the integrated circuit chip.

[0028] The integrated circuit chip included in the integrated circuit chip packaging device 100 includes two or three of the following items: one or more control chips, one or more switch tubes, and one or more chip devices (for example, chip resistors, chip capacitors, chip inductors, etc.).

[0029] The lead frame 120 is used to carry the integrated circuit chip and form a conductive loop. The lead frame 120 includes three or more wafer carriers (also called "base islands") for carrying the integrated circuit chip, and at least two pins, each of which is coupled to one of the three or more wafer carriers. Since the lead frame 120 is encapsulated inside the integrated circuit chip packaging device 100 except for the portion where at least two pins extend outside the package body, Figure 1A The lead frame 120 is shown as a dotted frame except for a portion where at least two leads extend outside the package body.

[0030] The following will refer to Figure 2A , Figure 2B , Figure 2C , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5B Let's introduce the structure of the lead frame in detail.

[0031] Figure 2A It shows that it can be applied to Figure 1A A top view of an example lead frame 200 of the integrated circuit chip package device 100 is shown.

[0032] like Figure 2A As shown, the lead frame 200 includes at least three wafer stages, which are wafer stage 1, wafer stage 2 and wafer stage 3, and at least two pins, which are pin 1 and pin 2. Pin 1 is coupled to wafer stage 3, and pin 2 is coupled to wafer stage 1.

[0033] Each of the wafer carrier 1, wafer carrier 2 and wafer carrier 3 can be used to carry one or more control chips, switch tubes, or patch devices. By providing at least three wafer carriers, the integrated circuit chips carried thereon can be isolated (for example, withstand voltage isolation).

[0034] When a plurality of integrated circuit chips are carried on a wafer stage, the plurality of integrated circuit chips can be arranged horizontally or in a stacked arrangement. The stacked arrangement can significantly reduce the area of ​​the wafer stage, thereby reducing the area of ​​the entire integrated circuit chip packaging device.

[0035] In some embodiments, the size of the wafer carrier 1 can be made larger, for example, its area accounts for 10%-90% of the total area of ​​the package body of the integrated circuit chip packaging device, for example, more than 30%, so as to carry larger-sized high-power integrated circuit chips (such as switching tubes and other devices), and at the same time a larger area can be exposed to the outside of the package body to increase heat dissipation.

[0036] In order to improve the heat dissipation performance of the integrated circuit chip packaging device, at least a portion of at least one of the three or more wafer carriers in the lead frame of the integrated circuit chip packaging device may be exposed outside the package body.

[0037] In one embodiment, for example, Figure 2A In the embodiment, at least a portion of the wafer stage 1 carrying the high-power device is recessed, sunken or half-etched relative to other wafer stages.

[0038] Figure 1B Shows Figure 1A The integrated circuit chip packaging device 100 shown in FIG. Figure 2A The lead frame 200 is shown in cross-section along AA. Figure 2B Shows Figure 2A The exemplary lead frame 200 is shown in a cross-sectional view along the line BB. Figure 1B and Figure 2B It can be seen that at least a portion of the wafer carrier 1 is recessed or half-etched relative to the wafer carrier 2 or 3, so that the at least a portion that is recessed or the remaining portion of the at least a portion after half-etching is exposed to the outside of the integrated circuit chip packaging device (for example, exposed from the outer surface of the package body 110), serving as a channel for the integrated circuit chip packaging device 100 to dissipate heat to the external environment.

[0039] In addition, in order to facilitate the exposure of the back side of the wafer carrier 1 to the outside of the integrated circuit chip packaging device, the thickness of the integrated circuit chip packaging device can be reduced.

[0040] In another embodiment, for example, Figure 2A In the embodiment, the thickness of at least a portion of the wafer carrier 1 carrying the high-power device is designed to be greater than or equal to the thickness of other wafer carriers.

[0041] Figure 1C Shows Figure 1A The integrated circuit chip packaging device 100 shown in FIG. Figure 2A The lead frame 200 is shown in another cross-sectional view along AA. Figure 2C Shows Figure 2A Another cross-sectional view of the exemplary lead frame 200 along BB is shown. Figure 1C and Figure 2CIt can be seen that the thickness of at least a portion of the wafer carrier 1 is greater than or equal to the thickness of the wafer carrier 2 or 3, so that at least a portion of the wafer carrier 1 can be exposed to the outside of the integrated circuit chip packaging device (for example, exposed from the outer surface of the package body 110), serving as a channel for the integrated circuit chip packaging device 100 to dissipate heat to the external environment.

[0042] In other embodiments, Figure 2A At least a portion of the wafer stage 2 or 3 may be recessed, sunken, or half-etched relative to other wafer stages, or the thickness of at least a portion of the wafer stage 2 or 3 may be greater than or equal to the thickness of other wafer stages, so that at least a portion of the wafer stage 2 or 3 is exposed outside the package body 110. In other embodiments, at least a portion of more wafer stages may be recessed, sunken, or half-etched relative to other wafer stages, or the thickness of at least a portion of more wafer stages may be greater than or equal to the thickness of other wafer stages, so that at least a portion of more wafer stages is exposed outside the integrated circuit chip packaging device.

[0043] In order to further improve the heat dissipation performance of the integrated circuit chip packaging device, at least one of the at least two pins in the lead frame of the integrated circuit chip packaging device can be widened, and the widened pin can be connected to the carrier or formed into a whole with the carrier (for example, forming an integral widened pin), thereby further expanding the heat dissipation channel between the integrated circuit chip on the corresponding carrier and the external environment.

[0044] In one embodiment, for example, Figure 2A In the embodiment, the pin 2 is widened and connected to the wafer stage 1 or is formed as an integral part with the wafer stage 1.

[0045] In another embodiment, for example, Figure 2A In the embodiment, pin 1 is widened and connected to the wafer carrier 3 or is formed as an integral part with the wafer carrier 3.

[0046] In other embodiments, more pins may be widened and / or connected to the corresponding wafer stage or formed as an integral part with the corresponding wafer stage.

[0047] In the embodiments of the present disclosure, the surface of each wafer stage can be one or more of a fully or partially silver-plated surface, a bare copper surface, or a roughened surface. The silver-plated surface has good heat dissipation performance and bonding effect, the roughened surface can enhance the bonding force and bonding effect, and the bare copper surface has the advantage of low cost.

[0048] In some embodiments, at least one glue locking hole is provided on at least one of three or more wafer carriers in a lead frame of an integrated circuit chip packaging device. Figure 3A Shown in Figure 2AThe exemplary arrangement of the glue locking holes in the exemplary lead frame 200 is shown. In other examples, more or fewer glue locking holes may be provided as required. By providing the glue locking holes on the wafer stage, the bonding force between the package body (e.g., the plastic package body) and the frame can be increased, thereby improving the reliability of the product.

[0049] In some embodiments, at least one silver-plated area is disposed on at least one of three or more wafer carriers in a lead frame of an integrated circuit chip package device. Figure 3B Shown in Figure 2A The example arrangement of the silver-plated area in the example lead frame 200 is shown. In other examples, more or fewer silver-plated areas can be provided as needed. By providing a local silver-plated area on the wafer stage, the requirements for wire bonding can be met, and the bonding force between the package (e.g., plastic package) and the frame can be increased, thereby improving the reliability of the product.

[0050] Figure 4A It shows that it can be applied to Figure 1A A top view of another example lead frame 400 of the integrated circuit chip package device 100 is shown.

[0051] like Figure 4A As shown, the lead frame 400 includes at least four stages, which are stage 1, stage 2, stage 3 and stage 4, and at least three pins, which are pin 1, pin 2 and pin 3. Pin 1 is coupled to stage 3, pin 2 is coupled to stage 4, and pin 3 is coupled to stage 1.

[0052] Each of the wafer carrier 1, wafer carrier 2, wafer carrier 3 and wafer carrier 4 can be used to carry one or more control chips, switch tubes, or patch devices. By providing at least four wafer carriers, the integrated circuit chips carried thereon can be isolated (for example, withstand voltage isolation).

[0053] When a plurality of integrated circuit chips are carried on a wafer stage, the plurality of integrated circuit chips can be arranged horizontally or in a stacked arrangement. The stacked arrangement can significantly reduce the area of ​​the wafer stage, thereby reducing the area of ​​the entire integrated circuit chip packaging device.

[0054] In order to improve the heat dissipation performance of the integrated circuit chip packaging device, at least a portion of at least one wafer carrier in the lead frame 400 can be exposed outside the package body. The specific form is similar to that described above for the lead frame 200 shown in Figure 2 and will not be repeated here.

[0055] In order to further improve the heat dissipation performance of the integrated circuit chip packaging device, at least one pin in the lead frame 400 can be widened, and the widened pin can be connected to the corresponding wafer carrier or formed into a whole with the corresponding wafer carrier (for example, forming an integral widened pin). The specific form is similar to that described above for the lead frame 200 shown in Figure 2 and will not be repeated here.

[0056] Figure 4B Shown in Figure 4A An example arrangement of glue locking holes and / or silver-plated areas in an example lead frame 400. At least one glue locking hole and / or silver-plated area is provided on at least one wafer stage in the lead frame 400. By providing a glue locking hole on the wafer stage, the bonding force between the package body (e.g., a plastic package body) and the frame can be increased, thereby improving the reliability of the product. By providing a local silver-plated area on the wafer stage, the requirements for wire bonding can be met, and the bonding force between the package body (e.g., a plastic package body) and the frame can be increased, thereby improving the reliability of the product.

[0057] Figure 5A A top view of an example internal package structure of an integrated circuit chip package device according to an embodiment of the present disclosure is shown. Figure 5B A top view of another example internal packaging structure of an integrated circuit chip package device according to an embodiment of the present disclosure is shown.

[0058] Inside the integrated circuit chip packaging device, three or more wafer carriers, the integrated circuit chip, and the parts of at least two pins located inside the package body (referred to as: inner pins) are connected by one or more of the following methods: bonding (for example, by conductive glue, insulating glue, etc.), welding (for example, by solder paste or welding wire, etc.), wire bonding (for example, using metal wires), or bridging (for example, by bridges). The patch device is connected to the wafer carrier by at least one of the following methods: bonding, welding, or wire bonding. When connecting by wire bonding, metal wires of the same or different diameters with a diameter between 0.8 mils (mil) and 2 mils are used.

[0059] Figure 5A and Figure 5B The integrated circuit chip packaging device adopts Figure 2A The lead frame 200 is shown, and the wafer carriers 1 and 3 are respectively provided with silver-plated areas, and the wafer carriers 2 and 3 are respectively provided with glue locking holes.

[0060] exist Figure 5A and Figure 5BIn the embodiment, the area of ​​the wafer stage 1 is significantly larger than that of the wafer stage 2 or the wafer stage 3, and its area accounts for more than 30% of the total area of ​​the package body of the integrated circuit chip packaging device, thereby carrying a larger size of high-power integrated circuit chips. The wafer stage 1 is connected to or formed into one with the widened pins 2, so that the pins 2 become one of the heat dissipation channels between the integrated circuit chip carried on the wafer stage 1 and the external environment. In addition, at least a part of the wafer stage 1 can be exposed to the outside of the package body by sinking or increasing the thickness, forming another heat dissipation channel between the integrated circuit chip carried on the wafer stage 1 and the external environment.

[0061] like Figure 5A As shown, the wafer stage 1 is implemented with a larger size (which can be enlarged according to actual needs) to carry a larger power integrated circuit chip (for example, a switch tube), on which a smaller control integrated circuit chip (for example, a control chip) can be pasted, and the wafer stage 2 and the wafer stage 3 carry surface mount devices (for example, surface mount resistors, surface mount capacitors, surface mount inductors, etc.). The control chip is connected to the switch tube and each wafer stage by wire bonding (shown as black line segments of different thicknesses in the figure), and the wafer stage 2 and the wafer stage 3 are connected by surface mount devices.

[0062] like Figure 5B As shown, the switching tube is carried on the wafer stage 1, the surface mount devices are carried on the wafer stage 2 and the wafer stage 3, and the control chip is also carried on the wafer stage 3. The control chip is connected to the switching tube and each wafer stage by wire bonding (shown as black lines of different thicknesses in the figure), and the wafer stage 2 and the wafer stage 3 are connected by surface mount devices.

[0063] Although the above describes the pin arrangement of the integrated circuit chip packaging device according to the embodiment of the present disclosure by taking the packaging structure of two pins and three pins as examples, it should be understood that the integrated circuit chip packaging device according to the embodiment of the present disclosure is not limited to including two pins, but may include more pins. In addition, in order to make the integrated circuit chip packaging device according to the embodiment of the present disclosure more reliable for customer applications, the integrated circuit chip packaging device according to the embodiment of the present disclosure is limited to including and only including two pins.

[0064] In the case where the integrated circuit chip packaging device according to the embodiment of the present disclosure includes and only includes two pins, since the integrated circuit chip packaging device according to the embodiment of the present disclosure includes three or more wafer carriers, there is a problem of how to keep the three or more wafer carriers coplanar. In order to solve this problem, in the process of manufacturing the integrated circuit chip packaging device according to the embodiment of the present disclosure, it is necessary to keep the corresponding wafer carriers that are not connected to the pins in a series of integrated circuit chip packaging devices connected to the same external support rod, and when forming a single integrated circuit chip packaging device, the support rod is cut off.

[0065] In an integrated circuit chip packaging device according to an embodiment of the present disclosure, the thickness of each of three or more wafer carriers and at least two pins is greater than or equal to 0.125 mm and less than or equal to 0.45 mm, for example, 0.25 mm or 0.3 mm.

[0066] The overall thickness of the integrated circuit chip package device according to the embodiment of the present disclosure is greater than or equal to 1 mm and less than or equal to 2 mm, for example, 1.3 mm or 1.8 mm.

[0067] In the integrated circuit chip packaging device according to the embodiment of the present disclosure, the spacing between two of three or more wafer carriers is greater than or equal to 0.125 mm and less than or equal to 0.3 mm, for example, 0.18 mm or 0.25 mm.

[0068] In the integrated circuit chip packaging device according to the embodiment of the present disclosure, the length of at least two pins extending outside the package body is greater than or equal to 0.3 mm and less than or equal to 0.8 mm, for example, 0.5 mm or 0.6 mm, so that a common wave soldering or reflow soldering process can be selected during market assembly.

[0069] According to the embodiment of the present disclosure, the integrated circuit chip packaging device effectively realizes the voltage-resistant isolation between different integrated circuit chips by setting three or more wafer carriers, and enables the patch devices to be directly integrated therein, thereby reducing the overall size of the integrated circuit chip packaging device; by connecting the wafer carrier and the widened pins together or forming them into one, the widened pins become one of the heat dissipation channels between the integrated circuit chip carried on the wafer carrier and the external environment. In addition, by exposing at least a portion of the wafer carrier to the outside of the package body by means of denting, sinking or increasing the thickness, another heat dissipation channel between the integrated circuit chip carried on the wafer carrier and the external environment is formed, thereby improving the heat dissipation performance of the integrated circuit chip packaging device; by stacking and placing multiple integrated circuit chips on the wafer carrier, the overall size of the integrated circuit chip packaging device is further reduced.

[0070] Compared with similar structures, the integrated circuit chip packaging device according to the present invention has the advantages of higher integration, smaller size, better heat dissipation performance, and lower manufacturing cost. Therefore, it is suitable for the design packaging, large-scale manufacturing and application of miniaturized, highly integrated power integrated circuit chips with heat dissipation requirements (for example, power management integrated circuit chips).

[0071] Figure 6 An example circuit diagram of applying the integrated circuit chip packaging device according to an embodiment of the present disclosure to a power management circuit is shown. In this example, for example, pin 1 is a ground pin (GND pin), and pin 2 is a drain pin (D pin). This example circuit diagram can be applied to power management electronic product applications such as fast charging and PD fast charging, and has low power consumption and high efficiency power application value.

[0072] The integrated circuit chip packaging device according to the present disclosure is also applicable to other circuits, which are not listed here one by one.

[0073] The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the above description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, materials, etc. may be adopted. In other cases, known structures, materials or operations are not shown or described in detail to avoid blurring the main technical ideas of the present disclosure.

[0074] Those skilled in the art will appreciate that the above embodiments are exemplary and non-restrictive. Different technical features appearing in different embodiments may be combined to achieve beneficial effects. Those skilled in the art will be able to understand and implement other variations of the disclosed embodiments based on studying the drawings, the specification and the claims. The presence of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. An integrated circuit chip packaging device, characterized in that: include: Integrated circuit chips, including two or three of the following: one or more control chips, one or more switch tubes, and one or more surface mount devices; Lead frame, including: Three or more wafer carriers for carrying the integrated circuit chips, and at least two pins, each coupled to one of the three or more wafer stages; and A package body, used to package the integrated circuit chip and the lead frame, wherein the at least two pins extend outside the package body, At least one of the at least two pins is widened, and the at least one widened pin is respectively connected to one of the three or more wafer carriers or forms an integral part with one of the three or more wafer carriers.

2. The integrated circuit chip packaging device according to claim 1, wherein: At least a portion of at least one of the three or more wafer stages is exposed to the outside of the package.

3. The integrated circuit chip packaging device as claimed in claim 2, characterized in that: At least a portion of the wafer stage exposed outside the package is recessed or half-etched relative to at least one other wafer stage, and the recessed and sunken at least a portion or the remaining portion of the at least a portion after half-etching is exposed outside the package.

4. The integrated circuit chip packaging device according to claim 2, wherein: The thickness of the wafer stage exposed to the outside of the package is equal to or greater than that of at least one other wafer stage, so that the wafer stage is exposed to the outside of the package.

5. The integrated circuit chip packaging device according to claim 1, wherein: The surface of each of the three or more wafer carriers includes one or more of the following: a fully or partially silver-plated surface, a bare copper surface, or a roughened surface.

6. The integrated circuit chip packaging device according to claim 1, wherein: At least one of the three or more wafer carriers is provided with at least one glue locking hole.

7. The integrated circuit chip packaging device according to claim 1, wherein: At least one of the three or more wafer carriers is provided with at least one silver-plated area.

8. The integrated circuit chip packaging device according to claim 1, wherein: One or more integrated circuit chips are carried on each of the three or more wafer carriers, and when a plurality of integrated circuit chips are carried on each of the three or more wafer carriers, the plurality of integrated circuit chips are arranged horizontally or in a stacked arrangement.

9. The integrated circuit chip packaging device according to claim 1, wherein: The three or more wafer carriers, the integrated circuit chip, and the portions of the at least two pins located inside the package are connected by one or more of the following methods: bonding, welding, wire bonding, or bridging.

10. The integrated circuit chip packaging device according to claim 1, wherein: The SMD device is connected to the wafer carrier by at least one of the following methods: bonding, welding or wire bonding.

11. The integrated circuit chip packaging device according to claim 9 or 10, characterized in that: When making connections by wire bonding, use wires of the same or different diameters ranging from 0.8 mil to 2 mils.

12. The integrated circuit chip packaging device according to claim 1, wherein: The thickness of each of the three or more wafer carriers and the at least two pins is greater than or equal to 0.125 mm and less than or equal to 0.45 mm.

13. The integrated circuit chip packaging device according to claim 1, wherein: The thickness of the integrated circuit chip packaging device is greater than or equal to 1 mm and less than or equal to 2 mm.

14. The integrated circuit chip packaging device according to claim 1, wherein: The spacing between any two of the three or more wafer carriers is greater than or equal to 0.125 mm and less than or equal to 0.3 mm.

15. The integrated circuit chip packaging device according to claim 1, wherein: The length of the at least two pins extending to the outside of the package body is greater than or equal to 0.3 mm and less than or equal to 0.8 mm.

16. The integrated circuit chip packaging device according to claim 1, wherein: Includes two and only two pins.

17. A lead frame, characterized in that: include: Three or more wafer carriers for carrying integrated circuit chips, wherein the integrated circuit chips include two or three of the following items: one or more control chips, one or more switch tubes, and one or more surface mount devices; and at least two pins, each coupled to one of the three or more wafer stages, At least one of the at least two pins is widened, and the at least one widened pin is respectively connected to one of the three or more wafer carriers or forms an integral part with one of the three or more wafer carriers.

18. A power management circuit, characterized in that: An integrated circuit chip packaging device comprising the device described in any one of claims 1 to 16.

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