Fast-discharging delay starting circuit and communication main control board

Abstract

The utility model discloses a quick-discharge delay starting circuit and a communication main control board, and belongs to the technical field of electronic circuits. The circuit is characterized in that a cathode of a direct-current power supply is grounded, and an anode is connected to a main power switch of the circuit; the power supply pin of the 555 timer chip and the input end of the switching power supply are connected to the switch; when the switch is closed, the direct-current power supply supplies power to the chip, and the chip outputs a level signal to the enabling pin of the switching power supply; and when the switch is switched off, the triode is used for rapidly discharging the rapid discharge circuit, the transistor is used for rapidly discharging the switching power supply rapid discharge circuit, and the relay is used for rapidly discharging the load rapid discharge circuit. When the circuit is powered on, delayed starting is achieved through the 555 timer, when the circuit is powered off, residual electricity in the multiple sub-circuits is rapidly discharged through the triodes, the transistors and the relays, and the situation that when residual electricity exists in the circuit, the circuit is powered on again, and then the circuit is abnormal and cannot be normally started is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a fast-discharging delayed start circuit and a communication main control board. Background Art

[0002] Currently, when there are multiple loads in a circuit, a power-on and power-off sequence is usually required to enable the circuit to work normally.

[0003] In the related art, a delayed start method is usually used to ensure that each voltage of the load circuit is powered on according to the designed timing. However, in actual applications, it is found that after the circuit loses power, the capacitors in each level of the circuit release the energy too slowly. If the energy in the capacitor has not been completely released, the circuit will easily fail to start normally when it is powered on again.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Utility Model Content

[0005] The embodiment of the present application provides a fast-discharge delayed start circuit and a communication main control board, which realizes delayed start through a 555 timer when the circuit is powered on, and quickly discharges the residual power in multiple sub-circuits through triodes, transistors, and relays when the circuit is powered off, thereby reducing the situation where the circuit is powered on again when there is residual power, thereby causing the circuit to be abnormal and unable to start normally.

[0006] On the one hand, the embodiment of the present application provides a fast-discharge delayed start circuit, including: a DC power supply, a 555 timer chip, a switching power supply, a delayed start fast-discharge sub-circuit, a switching power supply fast-discharge sub-circuit, and a load fast-discharge sub-circuit;

[0007] The negative pole of the DC power supply is grounded; the positive pole of the DC power supply is connected to the main power switch of the fast discharge delay start circuit; the power supply pin of the 555 timer chip and the input end of the switching power supply are both connected to the main power switch;

[0008] When the main power switch is closed, the DC power supply supplies power to the 555 timer chip, and the 555 timer chip outputs a corresponding level signal to the enable pin of the switching power supply, and the level signal enables the output switch of the switching power supply;

[0009] The delayed start fast discharge sub-circuit includes a PNP triode; the switching power supply fast discharge sub-circuit includes a Pmos transistor; the load fast discharge sub-circuit includes a normally closed relay;

[0010] When the main power switch is turned off, the PNP transistor is used to quickly discharge the fast-discharge sub-circuit, the Pmos transistor is used to quickly discharge the switching power supply fast-discharge sub-circuit, and the normally closed relay is used to quickly discharge the load fast-discharge sub-circuit.

[0011] Optionally, the fast discharge delayed start circuit further includes: a first diode, a first resistor, a first voltage regulator tube, a second resistor and a third resistor;

[0012] The anode of the first diode is connected to the main power switch;

[0013] One end of the first resistor and the input end of the switching power supply are connected to the cathode of the first diode;

[0014] The power supply pin, reset pin and the negative electrode of the first voltage regulator of the 555 timer chip are connected to the other end of the first resistor;

[0015] The positive electrode of the first voltage regulator tube and one end of the second resistor are grounded;

[0016] The output pin of the 555 timer chip is connected to one end of the third resistor;

[0017] The other end of the second resistor and the other end of the third resistor are connected to an enable pin of the switching power supply.

[0018] Optionally, the delayed start fast discharge sub-circuit further includes: a first capacitor, a fourth resistor, a fifth resistor and a sixth resistor;

[0019] The emitter of the PNP transistor and the positive electrode of the first capacitor are connected to the other end of the first resistor;

[0020] The negative electrode of the first capacitor and one end of the fourth resistor are both connected to the trigger pin and the threshold pin of the 555 timer chip;

[0021] The collector of the PNP transistor is connected to one end of the fifth resistor;

[0022] The base of the PNP transistor and one end of the sixth resistor are connected to the main power switch;

[0023] The other end of the fourth resistor, the other end of the fifth resistor, and the other end of the sixth resistor are grounded.

[0024] Optionally, the fifth resistor is a discharge resistor.

[0025] Optionally, the switching power supply fast discharge sub-circuit further includes: a second capacitor, a third capacitor, and a seventh resistor;

[0026] The cathode of the first diode, one end of the second capacitor, one end of the third capacitor and the input end of the switching power supply are connected to one end of the seventh resistor;

[0027] The other end of the seventh resistor is connected to the source of the Pmos transistor;

[0028] The other end of the second capacitor, the other end of the third capacitor and the drain of the Pmos transistor are grounded;

[0029] The gate of the Pmos transistor and the anode of the first diode are connected to the main power switch.

[0030] Optionally, a fourth capacitor is provided between the gate of the Pmos transistor and the source of the Pmos transistor.

[0031] Optionally, the load fast discharge subcircuit further includes: a fifth capacitor, a sixth capacitor, an eighth resistor and a ninth resistor;

[0032] One end of the fifth capacitor, one end of the sixth capacitor and one end of the ninth resistor are connected to the output end of the switching power supply;

[0033] One end of the coil of the normally closed relay is connected to the main power switch;

[0034] The other end of the coil of the normally closed relay is grounded;

[0035] A group of normally closed contacts of the normally closed relay are respectively connected to the output end of the switching power supply and one end of the ninth resistor;

[0036] The other end of the fifth capacitor, the other end of the sixth capacitor, the other end of the eighth resistor and the other end of the ninth resistor are grounded.

[0037] Optionally, the ninth resistor is formed by connecting a plurality of discharge resistors in parallel.

[0038] Optionally, the DC power supply is a 24V DC power supply.

[0039] On the other hand, an embodiment of the present application provides a communication main control board, including: a fast discharge delayed start circuit as described in any one of the above.

[0040] The embodiment of the present application realizes delayed start-up through a 555 timer when the circuit is powered on, and quickly discharges the residual power in multiple sub-circuits through triodes, transistors, and relays when the circuit is powered off, thereby reducing the situation where the circuit is powered on again when there is residual power, thereby causing the circuit to be abnormal and unable to start normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a structural schematic diagram of a fast discharge delayed start circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0043] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0044] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0046] With the development of science and technology, communication motherboards have requirements for the power-on timing and voltage conversion rate of each electronic component. For example, when the load has multiple power supplies, it is necessary to pre-design the power-on and power-off sequence requirements.

[0047] In the related art, a delayed start circuit is usually designed at the front stage of the load. When the circuit is powered on again after power failure, a certain delay is made to allow the energy of the rear stage load circuit to be fully released. The front stage power supply can only be connected to the load again after the delay time is reached. However, in actual applications, it is found that since the input and output ends of the load circuit power supply usually need to be connected in parallel with multiple capacitors to achieve the purpose of filtering, after the power is turned off and the circuit is powered off, the capacitors in each stage of the circuit release the electric energy too slowly. If the electric energy in the capacitor has not been completely released, the circuit will easily fail to start normally when the circuit is powered on again.

[0048] In view of this, a fast-discharge delayed start circuit and a communication main control board are provided in the embodiments of the present application. When the circuit is powered on, a delayed start is achieved through a 555 timer. When the circuit is powered off, the residual power in multiple sub-circuits is quickly discharged through transistors, transistors, and relays, thereby reducing the situation where the circuit needs to be powered on again when there is residual power, which leads to circuit abnormalities and inability to start normally.

[0049] The specific implementation of the embodiment of the present application is described in detail below in conjunction with the accompanying drawings. First, a fast discharge delay start circuit provided in the embodiment of the present application is described in conjunction with the accompanying drawings.

[0050] Please refer to Figure 1 , Figure 1 A structural schematic diagram of a fast-discharge delay start circuit provided in an embodiment of the present application is shown, including: a DC power supply, a 555 timer chip U1, a switching power supply U2, a delayed-start fast-discharge sub-circuit, a switching power supply fast-discharge sub-circuit, and a load fast-discharge sub-circuit.

[0051] The negative pole of the DC power supply is grounded; the positive pole of the DC power supply is connected to the main power switch K1 of the fast discharge delay start circuit; the power supply pin 8 of the 555 timer chip U1 and the input terminal Vin of the switching power supply U2 are both connected to the main power switch K1.

[0052] When the main power switch K1 is closed, the DC power supply supplies power to the 555 timer chip U1, and the 555 timer chip U1 outputs a corresponding level signal to the enable pin EN of the switching power supply U2, and the level signal enables the output terminal Vout switch of the switching power supply U2.

[0053] The delayed start fast discharge sub-circuit includes a PNP transistor Q1; the switching power supply fast discharge sub-circuit includes a Pmos transistor Q2; and the load fast discharge sub-circuit includes a normally closed relay K2.

[0054] When the main power switch K1 is disconnected, the PNP transistor Q1 is used to quickly discharge the fast discharge sub-circuit, the Pmos transistor Q2 is used to quickly discharge the switching power supply fast discharge sub-circuit, and the normally closed relay K2 is used to quickly discharge the load fast discharge sub-circuit.

[0055] Specifically, a DC power supply is provided in the fast discharge delayed start circuit (hereinafter referred to as the "circuit", which will not be described in detail) as the power supply device of the entire circuit. The negative pole of the DC power supply is grounded, and the positive pole is connected to the main power switch K1 of the circuit. The main power switch K1 can be used to control the power-on status of the entire circuit. When the main power switch K1 is closed, the circuit will be powered on as a whole; when the main power switch K1 is disconnected, the circuit will be powered off as a whole.

[0056] Furthermore, the circuit is also provided with a 555 timer chip U1, a switching power supply U2, a delayed start fast discharge sub-circuit, a switching power supply fast discharge sub-circuit and a load fast discharge sub-circuit. Among them, the power supply pin 8 of the 555 timer chip U1 and the input terminal Vin of the switching power supply U2 are both connected to the main power switch K1. Therefore, when the main power switch K1 is closed, the DC power supply will supply power to the 555 timer chip U1, and the 555 timer chip U1 will output a corresponding level signal to the enable pin EN of the switching power supply U2, and enable the output terminal Vout switch of the switching power supply U2 through the level signal to realize delayed start.

[0057] In some embodiments, the 555 timer chip U1 can not only be used to meet the delay start requirements of the circuit, but also has the advantages of low power consumption, high reliability and low cost. The input terminal Vin of the switching power supply U2 is connected to the DC power supply through the main power switch K1, and the output terminal Vout can be connected to the load to achieve the function of converting voltage to meet the subsequent load voltage requirements.

[0058] Furthermore, a PNP transistor Q1 is provided in the delayed start fast discharge subcircuit, a Pmos transistor Q2 is provided in the switching power supply fast discharge subcircuit, and a normally closed relay K2 is provided in the load fast discharge subcircuit. When the main power switch K1 is disconnected, that is, the circuit is powered off, the PNP transistor Q1 can be used to quickly discharge the fast discharge subcircuit, the Pmos transistor Q2 can be used to quickly discharge the switching power supply fast discharge subcircuit, and the normally closed relay K2 can be used to quickly discharge the load fast discharge subcircuit, thereby realizing that during the power-off process of the circuit, the residual electricity in the three subcircuits is quickly discharged synchronously, which can effectively reduce the situation where the circuit is powered on again when there is residual electricity, thereby causing the circuit to be abnormal and unable to start normally.

[0059] For details, please refer to Figure 1 In a possible implementation, the fast discharge delayed start circuit further includes: a first diode D1, a first resistor R1, a first voltage regulator D2, a second resistor R2 and a third resistor R3;

[0060] The anode of the first diode D1 is connected to the main power switch K1;

[0061] One end of the first resistor R1 and the input terminal Vin of the switching power supply U2 are connected to the cathode of the first diode D1;

[0062] The power supply pin 8, reset pin 4 and the negative electrode of the first voltage regulator tube D2 of the 555 timer chip U1 are connected to the other end of the first resistor R1;

[0063] The positive electrode of the first voltage regulator tube D2 and one end of the second resistor R2 are grounded;

[0064] The output pin 3 of the 555 timer chip U1 is connected to one end of the third resistor R3;

[0065] The other end of the second resistor R2 and the other end of the third resistor R3 are connected to an enable pin of the switching power supply U2.

[0066] Specifically, a first diode D1, a first resistor R1, a first voltage regulator D2, a second resistor R2 and a third resistor R3 are also provided in the fast discharge delayed start circuit. The positive electrode of the first diode D1 is connected to the main power switch K1, and one end of the first resistor R1 is connected to the input end Vin of the switching power supply U2, and is connected to the negative electrode of the first diode D1.

[0067] The first diode D1 can play a role of both rectification and protection. When a reverse voltage appears in the circuit, it can protect the load or other components from being damaged.

[0068] Furthermore, the power supply pin 8, reset pin 4 and the cathode of the first voltage regulator D2 of the 555 timer chip U1 are connected to the other end of the first resistor R1, and the anode of the first voltage regulator D2 and one end of the second resistor R2 are grounded.

[0069] Among them, the first resistor R1 and the first voltage regulator D2 can be used to reduce the voltage provided by the DC power supply to the power supply pin 8 and the reset pin 4 of the 555 timer chip U1, and then output the corresponding level signal to the enable pin EN of the switching power supply U2 through the output pin 3 of the 555 timer chip U1. Therefore, even if the voltage provided by the DC power supply is high and may exceed the normal working voltage of the 555 timer chip U1, it can be reduced by the first resistor R1 and the first voltage regulator D2 to meet the working environment of the 555 timer chip U1. For example, the voltage can be reduced to 6.2V by the first resistor and the first voltage regulator.

[0070] It can be understood that the ground pin 1 of the 555 timer chip U1 is grounded, and the discharge pin 7 and the control pin 5 are connected to ground.

[0071] As an optional embodiment, by changing the parameters of the first voltage regulator tube and the first resistor, the on and off control of the switching power supply with different requirements for the enable voltage can be met, which can effectively broaden the application scope of the circuit.

[0072] Furthermore, the output pin 3 of the 555 timer chip U1 is connected to one end of the third resistor R3, and the other end of the second resistor R2 and the other end of the third resistor R3 are connected to the enable pin EN of the switching power supply U2. The second resistor R2 and the third resistor R3 can effectively ensure that the voltage in the circuit will not be overloaded.

[0073] For details, please refer to Figure 1 In a possible implementation, the delayed start fast discharge sub-circuit further includes: a first capacitor C1, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6;

[0074] The emitter of the PNP transistor Q1 and the positive electrode of the first capacitor C1 are connected to the other end of the first resistor R1;

[0075] The negative electrode of the first capacitor C1 and one end of the fourth resistor R4 are both connected to the trigger pin 2 and the threshold pin 6 of the 555 timer chip U1;

[0076] The collector of the PNP transistor Q1 is connected to one end of the fifth resistor R5;

[0077] The base of the PNP transistor Q1 and one end of the sixth resistor R6 are connected to the main power switch K1;

[0078] The other end of the fourth resistor R4 , the other end of the fifth resistor R5 , and the other end of the sixth resistor R6 are grounded.

[0079] Specifically, a first capacitor C1, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6 are further provided in the delayed start fast discharge sub-circuit. Among them, when the main power switch K1 is closed, the fast discharge delayed start circuit is powered on, and the first capacitor C1 starts to charge at this time, which can be regarded as a path, then the trigger pin 2 and the threshold pin 6 of the 555 timer chip U1 are both at a high level, then the output pin 3 of the 555 timer chip U1 outputs a low level signal at this time, and after the low level signal is input to the enable pin EN of the switching power supply U2, it will enable the switching power supply to be turned off, and the load in the circuit will not be powered on temporarily, and then during the charging process of the first capacitor C1, the voltage at the trigger pin 2 of the 555 timer chip U1 will gradually decrease, and because the control pin 5 of the 555 timer chip U1 is empty, when the voltage at the trigger pin 2 drops to less than 1 / 3 of the voltage at the power supply pin, the output pin 3 of the 555 timer chip U1 will output a high level signal at this time, and after the high level signal is input to the enable pin EN of the switching power supply U2, it will enable the switching power supply to be turned on, and the load in the circuit starts to power on, achieving the purpose of delayed start.

[0080] It should be noted that when the main power switch K1 is closed, since the base of the PNP transistor Q1 and one end of the sixth resistor R6 are connected to the main power switch K1, the voltage at the base of the PNP transistor Q1 is equal to the voltage provided by the DC power supply, and the voltage at the emitter of the PNP transistor Q1 is the voltage after being stepped down by the first resistor R1 and the first voltage regulator D2. In other words, the base voltage of the PNP transistor Q1 is greater than the emitter voltage of the PNP transistor Q1. Therefore, the emitter to collector of the PNP transistor Q1 is in a cut-off state, and the delayed start fast discharge sub-circuit will not be quickly discharged.

[0081] Further, when the main power switch K1 is disconnected, due to the unidirectional conduction characteristic of the first diode D1, the voltage across the sixth resistor R6 is zero, that is, the base voltage of the PNP transistor Q1 is zero, and since the first capacitor C1 stores electrical energy, the emitter voltage of the PNP transistor Q1 is equal to the voltage at the power supply pin 8 of the 555 timer chip U1, that is, the base voltage of the PNP transistor Q1 is less than the emitter voltage of the PNP transistor Q1, and the emitter and collector of the PNP transistor Q1 are conductive, and the electrical energy stored in the first capacitor C1 will be quickly discharged through the fifth resistor R5, thereby achieving the purpose of quickly powering off the delayed start fast discharge sub-circuit through the PNP transistor Q1 when the circuit is powered off.

[0082] As an optional embodiment, the fifth resistor R5 is a discharge resistor. Therefore, when the circuit is powered off, the electric energy of the first capacitor C1 flows to the collector through the emitter of the PNP transistor Q1, and finally converts the electric energy into heat energy through the fifth resistor R5, achieving the purpose of rapid discharge.

[0083] For details, please refer to Figure 1 In a possible implementation, the switching power supply fast discharge sub-circuit further includes: a second capacitor C2, a third capacitor C3, and a seventh resistor R7;

[0084] The cathode of the first diode D1, one end of the second capacitor C2, one end of the third capacitor C3 and the input terminal Vin of the switching power supply U2 are connected to one end of the seventh resistor R7;

[0085] The other end of the seventh resistor R7 is connected to the source of the Pmos transistor Q2;

[0086] The other end of the second capacitor C2, the other end of the third capacitor C3 and the drain of the Pmos transistor Q2 are grounded;

[0087] The gate of the Pmos transistor Q2 and the anode of the first diode D1 are connected to the main power switch K1 .

[0088] Specifically, a second capacitor C2, a third capacitor C3, and a seventh resistor R7 are provided in the switching power supply fast discharge sub-circuit, wherein the second capacitor C2 and the third capacitor C3 are filter capacitors. When the main power switch K1 is closed, that is, when the circuit starts to be powered on, the voltage drop caused by the first diode D1 can be ignored, so the gate voltage of the Pmos transistor Q2 is equal to the source voltage, and the source and drain of the Pmos transistor Q2 are in a cut-off state, and the switching power supply fast discharge sub-circuit will not be quickly discharged.

[0089] Further, when the main power switch K1 is disconnected, due to the unidirectional conduction characteristic of the first diode D1, the gate voltage of the Pmos transistor Q2 becomes zero, and the voltage between the seventh resistor R7 and the source of the Pmos transistor Q2 is the voltage of the second capacitor C2 and the third capacitor C3, which is much greater than zero, so the source and drain of the Pmos transistor Q2 are turned on, and the current will flow to the seventh resistor R7 through the second capacitor C2 and the third capacitor C3, and then flow to the power ground through the source and drain of the Pmos transistor Q2, thereby achieving the purpose of quickly powering off the switching power supply fast discharge sub-circuit through the Pmos transistor Q2 when the circuit is powered off.

[0090] As an optional embodiment, a fourth capacitor C4 is provided between the gate of the Pmos transistor Q2 and the source of the Pmos transistor Q2.

[0091] Specifically, Figure 1 As shown, a fourth capacitor C4 is provided between the gate of the Pmos transistor Q2 and the source of the Pmos transistor Q2. The fourth capacitor C4 can be used to stabilize the voltage between the gate and the source of the Pmos transistor Q2. The capacitance is PF level, and the stored electric energy can be ignored.

[0092] For details, please refer to Figure 1 In a possible implementation, the load fast discharge subcircuit further includes: a fifth capacitor C5, a sixth capacitor C6, an eighth resistor R8 and a ninth resistor R9;

[0093] One end of the fifth capacitor C5, one end of the sixth capacitor C6 and one end of the ninth resistor R9 are connected to the output terminal Vout of the switching power supply U2;

[0094] One end of the coil of the normally closed relay K2 is connected to the main power switch K1;

[0095] The other end of the coil of the normally closed relay K2 is grounded;

[0096] A group of normally closed contacts of the normally closed relay K2 are respectively connected to the output terminal Vout of the switching power supply U2 and one end of the ninth resistor R9;

[0097] The other end of the fifth capacitor C5, the other end of the sixth capacitor C6, the other end of the eighth resistor R8 and the other end of the ninth resistor R9 are grounded.

[0098] Specifically, one end of the coil of the normally closed relay K2 is connected to the main power switch K1, and the other end is grounded. Therefore, when the main power switch K1 is closed, the working power of the normally closed relay K2 comes from the DC power supply and is not affected by the delayed start. After the circuit is powered on, the coil of the normally closed relay K2 is energized, and a group of normally closed contacts of the normally closed relay K2 will change from a closed state to an open state. Then, the ninth resistor R9 at the load end will be disconnected from the fifth capacitor C5, the sixth capacitor C6 and the eighth resistor R8, and the load fast discharge sub-circuit will not be quickly discharged.

[0099] The fifth capacitor C5 is a filter capacitor, the sixth capacitor C6 is a load equivalent capacitor, and the eighth resistor R8 is a protection resistor.

[0100] Furthermore, when the main power switch K1 is disconnected, due to the unidirectional conductivity of the first diode D1, the coil of the normally closed relay K2 loses power, and a group of normally closed contacts of the normally closed relay K2 will resume a closed state, then the ninth resistor R9 at the load end will be connected to the fifth capacitor C5, the sixth capacitor C6 and the eighth resistor R8, and the electric energy stored in the fifth capacitor C5 and the sixth capacitor C6 will be quickly discharged through the ninth resistor R9, thereby achieving the purpose of quickly powering off the load fast discharge sub-circuit through the normally closed relay K2 when the circuit is powered off.

[0101] As an optional embodiment, the ninth resistor R9 is composed of a plurality of discharge resistors connected in parallel, which can effectively improve the residual power discharge efficiency.

[0102] Specifically, in a possible implementation, please refer to Figure 1 , the DC power supply is 24V DC power supply.

[0103] It is understandable that the positive pole of the DC power supply can be DC 24V and the negative pole can be DC 0V, which can meet the power requirements of the delayed start circuit for detecting rapid discharge and ensure the normal operation of each component in the delayed start circuit for rapid discharge.

[0104] Below, in combination with the specific application implementation process, the fast discharge delay start circuit provided in this application is described in detail and explained:

[0105] In an embodiment of the present application, a fast-discharging delayed start circuit is provided, which can be applied to a communication main control board scenario.

[0106] Specifically, when the main power switch of the fast discharge delayed start circuit is closed, the fast discharge delayed start circuit starts to power on, and the 24V power supply of the DC power supply is loaded on the input end of the switching power supply. Due to the presence of the first resistor and the first voltage regulator, the voltage of the power supply pin of the 555 timer chip is clamped at 6.2V, and due to the characteristics of the first capacitor, the initial voltage between the first capacitor and the fourth resistor is 6.2V. At this time, the output pin of the 555 timer chip outputs a low-level signal. As the first capacitor is slowly charged, the voltage between the first capacitor and the fourth resistor gradually decreases from 6.2V to 2.07V. Since the trigger pin of the 555 timer chip is less than 1 / 3 of the voltage at the power pin, the output pin of the 555 timer chip will output a high-level signal to the enable pin of the switching power supply, and enable the output end of the switching power supply to open, and output a 12V voltage to power the subsequent load, thereby achieving the purpose of delayed start.

[0107] It can be understood that, since the base voltage of the PNP transistor 24V is greater than the emitter voltage 6.2V, the emitter to collector of the PNP transistor is in the cut-off state, and the delayed start fast discharge sub-circuit does not work; since the gate voltage of the Pmos transistor is equal to the source voltage, the source and drain of the Pmos transistor are in the cut-off state, and the switching power supply fast discharge sub-circuit does not work; since the coil of the normally closed relay is energized, the normally closed contact becomes disconnected, and the load fast discharge sub-circuit does not work.

[0108] Further, when the main power switch of the fast-discharge delayed start circuit is disconnected, the fast-discharge delayed start circuit starts to power off. Due to the unidirectional conductivity of the first diode, the base voltage of the PNP transistor becomes zero, and since the first capacitor stores electrical energy, the emitter voltage of the PNP transistor is greater than the base voltage, the emitter and collector of the PNP transistor are turned on, and the electrical energy stored in the first capacitor is quickly discharged through the fifth resistor, so that the delayed start fast-discharge sub-circuit performs fast discharge; the gate voltage of the Pmos transistor becomes zero, and the voltage between the source of the Pmos transistor and the seventh resistor is 24V, which is much greater than zero, so the source and drain of the Pmos transistor are turned on, and the electrical energy stored between the second capacitor and the third capacitor is quickly discharged through the seventh resistor, so that the switching power supply fast-discharge sub-circuit performs fast discharge; since the coil of the normally closed relay loses power, the normally closed contact is restored from a disconnected state to a closed state, and the electrical energy stored in the fifth capacitor and the sixth capacitor at the output end of the switching power supply will be quickly discharged through the ninth resistor, so that the load fast-discharge sub-circuit performs fast discharge.

[0109] Therefore, when the fast-discharge delayed start circuit is powered off, the electric energy stored in the capacitors in the delayed-start fast-discharge sub-circuit, the switching power supply fast-discharge sub-circuit and the load fast-discharge sub-circuit will be discharged quickly at the same time, thereby increasing the overall residual power discharge speed of the fast-discharge delayed start circuit, and effectively reducing the situation in which the circuit is powered on again when there is residual power, thereby causing the circuit to abnormally fail to start normally.

[0110] Specifically, in a possible implementation, an embodiment of the present application further provides a communication main control board, and the communication main control board includes the above-mentioned fast discharge delayed start circuit.

[0111] It is understandable that the communication control board can be different types of communication control boards such as industrial communication control board, network communication control board, wireless communication control board, embedded communication control board, telecommunication communication control board, vehicle communication control board, etc. The selection can be made according to specific application requirements, environmental conditions and performance requirements.

[0112] The embodiment of the present application provides a fast-discharge delayed start circuit and a communication main control board, which realize delayed start through a 555 timer when the circuit is powered on, and quickly discharge the residual power in multiple sub-circuits through triodes, transistors, and relays when the circuit is powered off, thereby reducing the situation where the circuit is powered on again when there is residual power, thereby causing the circuit to be abnormal and unable to start normally.

[0113] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0114] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0115] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0116] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A fast discharge delayed start circuit, characterized in that: include: DC power supply, 555 timer chip, switching power supply, delayed start fast discharge electronic circuit, switching power supply fast discharge electronic circuit and load fast discharge electronic circuit; The negative electrode of the DC power supply is grounded; the positive electrode of the DC power supply is connected to the main power switch of the fast discharge delay start circuit; the power supply pin of the 555 timer chip and the input end of the switching power supply are both connected to the main power switch; When the main power switch is closed, the DC power supply supplies power to the 555 timer chip, and the 555 timer chip outputs a corresponding level signal to the enable pin of the switching power supply, and the level signal enables the output switch of the switching power supply; The delayed start fast discharge sub-circuit includes a PNP triode; the switching power supply fast discharge sub-circuit includes a Pmos transistor; the load fast discharge sub-circuit includes a normally closed relay; When the main power switch is disconnected, the PNP transistor is used to quickly discharge the fast discharge sub-circuit, the Pmos transistor is used to quickly discharge the switching power supply fast discharge sub-circuit, and the normally closed relay is used to quickly discharge the load fast discharge sub-circuit.

2. The fast discharge delayed start circuit according to claim 1, characterized in that: The fast discharge delayed start circuit also includes: a first diode, a first resistor, a first voltage regulator tube, a second resistor and a third resistor; The anode of the first diode is connected to the main power switch; One end of the first resistor and the input end of the switching power supply are connected to the cathode of the first diode; The power supply pin, reset pin and the negative electrode of the first voltage regulator of the 555 timer chip are connected to the other end of the first resistor; The positive electrode of the first voltage regulator tube and one end of the second resistor are grounded; The output pin of the 555 timer chip is connected to one end of the third resistor; The other end of the second resistor and the other end of the third resistor are connected to an enable pin of the switching power supply.

3. The fast discharge delayed start circuit according to claim 2, characterized in that: The delayed start fast discharge sub-circuit also includes: a first capacitor, a fourth resistor, a fifth resistor and a sixth resistor; The emitter of the PNP transistor and the positive electrode of the first capacitor are connected to the other end of the first resistor; The negative electrode of the first capacitor and one end of the fourth resistor are both connected to the trigger pin and the threshold pin of the 555 timer chip; The collector of the PNP transistor is connected to one end of the fifth resistor; The base of the PNP transistor and one end of the sixth resistor are connected to the main power switch; The other end of the fourth resistor, the other end of the fifth resistor, and the other end of the sixth resistor are grounded.

4. The fast discharge delayed start circuit according to claim 3, characterized in that: The fifth resistor is a discharge resistor.

5. The fast discharge delayed start circuit according to claim 2, characterized in that: The switching power supply fast discharge sub-circuit also includes: a second capacitor, a third capacitor, and a seventh resistor; The cathode of the first diode, one end of the second capacitor, one end of the third capacitor and the input end of the switching power supply are connected to one end of the seventh resistor; The other end of the seventh resistor is connected to the source of the Pmos transistor; The other end of the second capacitor, the other end of the third capacitor and the drain of the Pmos transistor are grounded; The gate of the Pmos transistor and the anode of the first diode are connected to the main power switch.

6. The fast discharge delayed start circuit according to claim 5, characterized in that: A fourth capacitor is provided between the gate of the Pmos transistor and the source of the Pmos transistor.

7. The fast discharge delayed start circuit according to claim 1, characterized in that: The load fast discharge subcircuit further includes: a fifth capacitor, a sixth capacitor, an eighth resistor and a ninth resistor; One end of the fifth capacitor, one end of the sixth capacitor and one end of the ninth resistor are connected to the output end of the switching power supply; One end of the coil of the normally closed relay is connected to the main power switch; The other end of the coil of the normally closed relay is grounded; A group of normally closed contacts of the normally closed relay are respectively connected to the output end of the switching power supply and one end of the ninth resistor; The other end of the fifth capacitor, the other end of the sixth capacitor, the other end of the eighth resistor and the other end of the ninth resistor are grounded.

8. The fast discharge delayed start circuit according to claim 7, characterized in that: The ninth resistor is formed by connecting a plurality of discharge resistors in parallel.

9. The fast discharge delayed start circuit according to claim 1, characterized in that: The DC power supply is a 24V DC power supply.

10. A communication main control board, characterized in that: include: A fast discharge delayed start circuit as described in any one of claims 1 to 9.

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