Multi-channel signal generating device, quantum calculation measurement and control system and quantum computer

Abstract

The utility model discloses a multichannel signal generating device, a quantum computing measurement and control system and a quantum computer, and the device comprises a clock source which is used for providing a 100 MHz reference clock signal; the power division amplification module is used for performing power division on a 100MHz reference clock signal provided by the clock source into multiple paths of first clock signals; the power division amplification module comprises a plurality of power dividers which are cascaded in sequence and a power amplification circuit which is electrically connected between any two adjacent power dividers, and the input end of the power divider located at the first stage is connected with the output end of a clock source; the input end of each signal processing module is connected with the output end of the corresponding power divider, and the signal processing modules are used for receiving one path of first clock signals in a one-to-one correspondence mode, processing the first clock signals and outputting multiple paths of first measurement and control signals used for controlling quantum bits. The device provided by the utility model can provide multiple paths of measurement and control signals, and can ensure the quality of each path of signal so as to ensure the accuracy of the measurement and control process.

Description

Technical Field

[0001] The utility model relates to the technical field of quantum computers, in particular to a multi-channel signal generating device, a quantum computing measurement and control system and a quantum computer. Background Art

[0002] A quantum computer is a physical device that follows the laws of quantum mechanics to perform high-speed mathematical and logical operations, store and process quantum information. It is mainly composed of a quantum measurement and control system, a quantum chip system, a quantum computing environment support system and a quantum computer operating system. The quantum measurement and control system includes a signal generator that is used to provide high-frequency measurement and control signals for each quantum bit in the quantum chip. Existing quantum computing directly uses purchased commercial signal sources as the signal generators required by the quantum measurement and control system. Commercial signal sources usually pursue single-channel performance and generally have very poor scalability. One commercial signal source provides one measurement and control signal. As the number of quantum bits integrated on the quantum chip increases, the number of commercial signal sources required increases.

[0003] Therefore, there is an urgent need for a signal generating device that can provide multiple measurement and control signals while ensuring the quality of each signal, or even improving the signal quality, to ensure the accuracy of the measurement and control process.

[0004] It should be noted that the information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Utility Model Content

[0005] The purpose of the utility model is to provide a multi-channel signal generating device, a quantum computing measurement and control system and a quantum computer, which can provide multi-channel measurement and control signals and at the same time ensure the quality of each signal to ensure the accuracy of the measurement and control process.

[0006] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0007] The first aspect of the utility model provides a multi-channel signal generating device, comprising:

[0008] Clock source, used to provide 100MHz reference clock signal;

[0009] A power division and amplification module, used for power-dividing a 100 MHz reference clock signal provided by the clock source into multiple first clock signals; the power division and amplification module comprises a plurality of power dividers cascaded in sequence and a power amplifier circuit electrically connected between any two adjacent power dividers, and the input end of the power divider at the first stage is connected to the output end of the clock source;

[0010] Multiple signal processing modules, each of which has an input end connected to an output end of the power divider, are used to receive one first clock signal in a one-to-one correspondence and output multiple first measurement and control signals for controlling quantum bits after processing.

[0011] The multi-channel signal generating device as described above further comprises a chassis, and a first PCB board arranged in the chassis;

[0012] The clock source, the power division amplifier module and the plurality of signal processing modules are integrated on the first PCB board, and the plurality of signal processing modules are arranged in parallel and at intervals.

[0013] The multi-channel signal generating device as described above, further, the signal processing module includes a frequency up-regulation circuit and a power regulation circuit which are electrically connected;

[0014] The frequency up-regulation circuit is used to output a second measurement and control signal with a frequency corresponding to the operating frequency of the quantum bit;

[0015] The power adjustment circuit is used to amplify the power of the second measurement and control signal to obtain the first measurement and control signal.

[0016] The multi-channel signal generating device as described above, further, the frequency up-regulation circuit comprises a frequency adjustment unit, a frequency mixing unit and a phase-locked loop system;

[0017] The frequency adjustment unit is used to generate a first reference signal and a second reference signal based on the first clock signal, and output them to the phase-locked loop system and the mixing unit respectively;

[0018] The frequency mixing unit is configured to perform at least one frequency mixing process based on the received second reference signal and the first feedback signal output by the phase-locked loop system to reduce the frequency of the first feedback signal to obtain a second feedback signal with the same frequency as the first reference signal, and output the second feedback signal to the phase-locked loop system, wherein the difference between the second reference signal and the first feedback signal is equal to the second feedback signal;

[0019] The phase-locked loop system is used to output the second measurement and control signal based on the received first reference signal and the second feedback signal.

[0020] The multi-channel signal generating device as described above, further, the frequency adjustment unit includes a first frequency up-adjusting unit and a second frequency up-adjusting unit;

[0021] A first frequency increasing unit, configured to generate a third reference signal with a higher frequency based on the first clock signal;

[0022] The second frequency up-adjusting unit is configured to generate the second reference signal with a higher frequency based on the third reference signal and output the second reference signal to the frequency mixing unit.

[0023] In the multi-channel signal generating device as described above, further, the first frequency increasing unit comprises:

[0024] A first frequency multiplying element, used for multiplying the frequency of the first clock signal;

[0025] A direct digital frequency synthesizer connected to the output end of the first frequency multiplication element, and used to generate an output signal with a lower frequency based on the signal after the frequency multiplication process;

[0026] A first mixer is electrically connected to the output end of the direct digital frequency synthesizer and the output end of the first frequency multiplication element, and is used for performing mixing processing based on the output signal of the direct digital frequency synthesizer and the output signal of the first frequency multiplication element to obtain the third reference signal and output it to the second frequency up-regulation unit;

[0027] The second frequency increasing unit includes:

[0028] A second frequency multiplication element, configured to perform frequency multiplication processing on the third reference signal output by the first frequency up-adjusting unit;

[0029] The first digitally controlled frequency divider is electrically connected to the output end of the second frequency multiplication element, and is used for performing frequency division processing on the power amplified and filtered signal to obtain the second reference signal and output it to the mixing unit.

[0030] The multi-channel signal generating device as described above, further, the first frequency up-regulation unit further includes a first amplifying and filtering element electrically connected between the first frequency multiplying element and the direct digital frequency synthesizer, for performing power amplification and filtering on the multiplied signal and outputting the signal to the direct digital frequency synthesizer;

[0031] And / or, the second frequency up-regulation unit further includes a second amplifying and filtering element electrically connected between the second frequency multiplying element and the first digitally controlled frequency divider, for performing power amplification and filtering on the frequency multiplied signal and outputting the signal to the first digitally controlled frequency divider;

[0032] And / or, the frequency adjustment unit further includes a third frequency down-adjustment unit, which is used to receive the third reference signal generated by the first frequency up-adjustment unit, perform frequency division processing to obtain the frequency-downregulated first reference signal, and output it to the phase-locked loop system.

[0033] The multi-channel signal generating device as described above, further, the power adjustment circuit includes a plurality of cascaded third amplifying and filtering elements, and a variable attenuation element electrically connected between any two adjacent third amplifying and filtering elements, the third amplifying and filtering element located at the first stage is electrically connected to the output end of the frequency up-regulation circuit, and the third amplifying and filtering element located at the last stage outputs the first measurement and control signal;

[0034] The third amplifying and filtering element is used to perform power amplification and filtering processing on the signal;

[0035] The variable attenuation element is used to adjustably attenuate the power of the signal.

[0036] The second aspect of the utility model provides a quantum computing measurement and control system, comprising the above-mentioned multi-channel signal generating device, wherein the multi-channel signal generating device is used to output a first measurement and control signal to a quantum chip.

[0037] The third aspect of the present invention provides a quantum computer, comprising the above-mentioned quantum computing measurement and control system and a quantum chip, wherein the quantum chip performs a quantum computing task according to a first measurement and control signal provided by the quantum computing measurement and control system. The beneficial effects of the present invention are:

[0038] The multi-channel signal generator of the present application divides the 100MHz reference clock signal provided by the same clock source into multiple first clock signals by setting a power division and amplification module, and then receives one first clock signal one by one through multiple signal processing modules and outputs multiple first measurement and control signals for controlling quantum bits after processing. This not only achieves the purpose of providing multiple first measurement and control signals at the same time, but also, because the first measurement and control signals are all obtained by processing based on the 100MHz reference clock signal output by the same clock source, while ensuring the integration, the stability of the phase difference of the final multiple first measurement and control signals is also guaranteed, mutual interference between signals is avoided, and the accuracy of measurement and control is improved; in addition, the power division and amplification module includes multiple power dividers cascaded in sequence and a power amplification circuit electrically connected between any two adjacent power dividers. While power division, the signal strength is also guaranteed, thereby ensuring the quality of each signal to ensure the accuracy of measurement and control.

[0039] The quantum computing measurement and control system and quantum computer provided by the utility model both include the above-mentioned multi-channel signal generator, and therefore have the same beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A circuit diagram of a multi-channel signal generating device provided by an embodiment of the utility model Figure 1 ;

[0041] Figure 2A circuit diagram of a multi-channel signal generating device provided by an embodiment of the utility model Figure 2 ;

[0042] Figure 3 A circuit diagram of a signal processing module provided by an embodiment of the utility model;

[0043] Figure 4 A schematic diagram of a frequency up-regulation circuit provided by an embodiment of the utility model Figure 1 ;

[0044] Figure 5 A schematic diagram of a frequency up-regulation circuit provided by an embodiment of the utility model Figure 2 ;

[0045] Figure 6 A schematic diagram of a frequency up-regulation circuit provided by an embodiment of the utility model Figure 3 ;

[0046] Figure 7 A schematic diagram of a power adjustment circuit provided by an embodiment of the utility model Figure 1 ;

[0047] Figure 8 A schematic diagram of a power adjustment circuit provided by an embodiment of the utility model Figure 2 ;

[0048] In the reference numerals:

[0049] 10. Clock source; 20. Power divider and amplifier module; 21. Power divider; 22. Power amplifier circuit;

[0050] 30. Signal processing module;

[0051] 31. Frequency up-regulation circuit;

[0052] 311, a first frequency up-regulation unit; 3111, a first frequency multiplication element; 3112, a direct digital frequency synthesizer; 3113, a first mixer; 3114, a first amplification and filtering element;

[0053] 312, second frequency up-regulation unit; 3121, second frequency multiplication element; 3122, second amplification and filtering element; 3123, first digital control frequency divider;

[0054] 313, a third frequency down-adjusting unit; 3131, a second digital control frequency divider;

[0055] 314, a frequency mixing unit; 3141, a second frequency mixer; 3142, a fourth amplifying and filtering element;

[0056] 315, phase detector; 316, voltage controlled oscillator; 317, loop filter; 318, third frequency divider;

[0057] 32. Power adjustment circuit; 321. Third amplifying and filtering element; 322. Variable attenuation element; 3221. First digitally controlled attenuator; 3222. Second digitally controlled attenuator; 3223. Voltage controlled attenuator. DETAILED DESCRIPTION

[0058] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limitations on the present application.

[0059] In the description of the present invention, it should be understood that the terms "center", "up", "down", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0060] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0061] Figure 1 A circuit diagram of a multi-channel signal generating device provided by an embodiment of the utility model Figure 1 ;like Figure 1As shown: The embodiment of the present application discloses a multi-channel signal generating device, including: a clock source 10, used to provide a 100 MHz reference clock signal; a power division and amplification module 20, used to power divide the 100 MHz reference clock signal provided by the clock source 10 into multiple first clock signals; the power division and amplification module 20 includes a plurality of power dividers 21 cascaded in sequence and a power amplifier circuit 22 electrically connected between any two adjacent power dividers 21, and the input end of the power divider 21 located at the first stage is connected to the output end of the clock source 10; a plurality of signal processing modules 30, each of the input ends of the signal processing modules 30 is connected to the output end of one of the power dividers 21, and is used to receive one first clock signal in a one-to-one correspondence and output multiple first measurement and control signals for controlling quantum bits after processing.

[0062] The multi-channel signal generator of this embodiment, by setting a power division and amplification module 20, divides the 100MHz reference clock signal provided by the same clock source 10 into multiple first clock signals, and then receives one first clock signal one by one through multiple signal processing modules 30 and outputs multiple first measurement and control signals for controlling quantum bits after processing, which not only achieves the purpose of providing multiple first measurement and control signals at the same time, but also, because the first measurement and control signals are all obtained by processing based on the 100MHz reference clock signal output by the same clock source 10, while ensuring the integration, the stability of the phase difference of the final multiple first measurement and control signals is also guaranteed, thereby avoiding mutual interference between signals and improving the accuracy of measurement and control; in addition, the power division and amplification module 20 includes multiple power dividers 21 cascaded in sequence and a power amplifier circuit 22 electrically connected between any two adjacent power dividers 21, which ensures the strength of the signal while dividing the power, thereby ensuring the quality of each signal to ensure the accuracy of measurement and control.

[0063] The clock source 10 in this embodiment may be a crystal oscillator source, which has the characteristics of high stability and low phase noise, thereby further reducing the phase noise of the final signal to improve the signal quality.

[0064] In this embodiment, the number of power dividers 21 in the power divider amplifier module 20 is not specifically limited, and can be 2, 3, 4 or more. The number of power amplifier circuits 22 is not specifically limited, and the number of power amplifier circuits 22 can be equal to the number of power dividers 21 or one less than the number of power dividers 21. Two specific examples are given below.

[0065] Example 1: Figure 1As shown, the power division and amplification module 20 contains 4 dividers and 4 power amplifier circuits 22. Specifically, the power division and amplification module 20 includes 4 dividers cascaded in sequence and a power amplifier circuit 22 electrically connected between any two adjacent dividers. The output port of the last-stage divider is also connected to a power amplifier circuit 22 to output the power-amplified signal to the next multi-channel signal generating device, which can simultaneously generate 4 first measurement and control signals.

[0066] Example 2: Figure 2 A circuit diagram of a multi-channel signal generating device provided by an embodiment of the utility model Figure 2 ;like Figure 2 As shown: the power division and amplification module 20 contains 4 dividers and 3 power amplifier circuits 22. Specifically, the power division and amplification module 20 includes 4 dividers cascaded in sequence and a power amplifier circuit 22 electrically connected between any two adjacent dividers. The two output ports of the last-stage divider are respectively connected to a signal processing module 30. The multi-channel signal generating device can simultaneously generate 5 first measurement and control signals.

[0067] In this embodiment, the specific type of the power amplifier circuit 22 is not limited, and may include one or more amplifiers.

[0068] In some implementations of this embodiment, the multi-channel signal generating device further includes a chassis, and a first PCB board arranged in the chassis; the clock source 10, the power division amplification module 20, and the plurality of signal processing modules 30 are integrated on the first PCB board, and the plurality of signal processing modules 30 are arranged in parallel and spaced apart. By integrating the clock source 10, the power division module, and the plurality of signal processing modules 30 on the first PCB board, the integration is improved, and by arranging the plurality of signal processing modules 30 in parallel and spaced apart, the electromagnetic interference and crosstalk between different signal processing modules 30 can be reduced, and the quality of each signal is guaranteed to ensure the accuracy of measurement and control.

[0069] Figure 3 A circuit diagram of a signal processing module 30 provided in an embodiment of the present utility model; Figure 3As shown: In some implementations of this embodiment, the signal processing module 30 includes an electrically connected frequency up-regulation circuit 31 and a power adjustment circuit 32; the frequency up-regulation circuit 31 is used to output a second measurement and control signal whose frequency corresponds to the working frequency of the quantum bit; the power adjustment circuit 32 is used to amplify the power of the second measurement and control signal to obtain the first measurement and control signal. The quality of the first measurement and control signal is guaranteed by the frequency up-regulation circuit 31 and the power adjustment circuit 32, so that its power and frequency meet the requirements. For example, when the multi-channel signal generating device of this embodiment is used as a signal source for the quantum chip when reading the signal, the frequency of the first measurement and control signal is adjusted to 12-16GHz by the frequency up-regulation circuit 31 and the power adjustment circuit 32, and the power is greater than 20dB to achieve precise measurement and control.

[0070] Figure 4 A schematic diagram of a frequency up-regulation circuit 31 provided in an embodiment of the present utility model Figure 1 ;like Figure 4 As shown, the frequency up-regulation circuit 31 includes a frequency adjustment unit, a frequency mixing unit 314 and a phase-locked loop system;

[0071] The frequency adjustment unit is used to generate a first reference signal and a second reference signal based on the first clock signal, and output them to the phase-locked loop system and the mixing unit 314 respectively;

[0072] The mixing unit 314 is configured to perform at least one mixing process based on the received second reference signal and the first feedback signal output by the phase-locked loop system to reduce the frequency of the first feedback signal to obtain a second feedback signal with the same frequency as the first reference signal, and output the second feedback signal to the phase-locked loop system, wherein the difference between the second reference signal and the first feedback signal is equal to the second feedback signal;

[0073] The phase-locked loop system is used to output the second measurement and control signal based on the received first reference signal and the second feedback signal.

[0074] The frequency up-regulation circuit 31 of this embodiment is provided with a mixing unit 314 to perform mixing processing on the first feedback signal output by the phase-locked loop system so as to adjust the frequency down to obtain a second feedback signal having the same frequency as the first reference signal and output it to the phase-locked loop system, thereby reducing the frequency division coefficient of the phase-locked loop system, reducing the phase noise of the signal, and generating a second measurement and control signal with low phase noise.

[0075] Specifically, continue as Figure 4As shown: In some implementations of this embodiment, the phase-locked loop system includes a phase detector 315, a loop filter 317, a voltage-controlled oscillator 316 and a third frequency divider 318; wherein the phase detector 317 is used to generate an error signal based on the phase difference between the received first reference signal and the second feedback signal and output it to the loop filter 317; the loop filter 317 is used to output a control voltage signal based on the error signal and output it to the voltage-controlled oscillator 316; the voltage-controlled oscillator 316 is used to output the second measurement and control signal to the quantum chip and the third frequency divider 318 based on the control voltage signal; the third frequency divider 318 is used to obtain the first feedback signal by dividing the second measurement and control signal. In the frequency up-regulation circuit 31 of the present embodiment, the frequency ratio of the second measurement and control signal to the first reference signal is a, the frequency division coefficient of the third divider 318 in the phase-locked loop system is the frequency ratio of the second measurement and control signal to the first feedback signal, denoted as N, and the frequency ratio of the first feedback signal to the second feedback signal is b; since the first reference signal and the second feedback signal can only be controlled to output the second measurement and control signal when the frequencies are the same, a=N*b. When a is determined, since the mixing unit 314 lowers the frequency of the first feedback signal to obtain the second feedback signal during the mixing process, b is greater than 1. Therefore, when the mixing unit 314 is set, N is reduced, that is, the frequency division coefficient of the phase-locked loop system is reduced, thereby reducing the phase noise level to improve the quality of the final signal.

[0076] The following is a detailed description of how the frequency up-regulation circuit 31 of this embodiment can reduce the frequency division coefficient of the phase-locked loop system through a specific example. By way of example, when the first reference signal is a low-frequency signal of about 100 MHz and the second measurement and control signal is 12 GHz, when the mixing unit 314 is not set, the frequency division coefficient of the phase-locked loop system is 12 GHz / 100 MHz, which is about 120; and when the frequency up-regulation circuit 31 of this embodiment is used and the mixing unit 314 is set, the frequency division coefficient satisfies the following relationship: a=N*b, a is the ratio of the frequency of the second measurement and control signal to the frequency of the first reference signal, so a is approximately equal to 120, and when b is larger, N is smaller; b is the ratio of the frequency of the first feedback signal to the second feedback signal, that is, the first feedback signal / 100 MHz. It can be seen that when the first feedback signal When the number is larger, b is larger and N is smaller; for example, when the first feedback signal is 12 GHz, N is 1; when the first feedback signal is 6 GHz, N is 2; when the first feedback signal is 4 GHz, N is 3, then, at this time, the mixing unit 314 needs to mix the first feedback signal of 12 GHz or 6 GHz or 4 GHz with the second reference signal to obtain a second feedback signal with a frequency of about 100 MHz. Therefore, by setting the mixing unit 314, the first feedback signal can be reduced to a second feedback signal with the same frequency as the first reference signal. Therefore, the division coefficient of the phase-locked loop system can be reduced to improve the quality of the final signal.

[0077] Continue as Figure 4 As shown: the frequency adjustment unit includes a first frequency up-adjustment unit 311 and a second frequency up-adjustment unit 312; the first frequency up-adjustment unit 311 is used to generate a third reference signal with a higher frequency based on the first clock signal; the second frequency up-adjustment unit 312 is used to generate the second reference signal with a higher frequency based on the third reference signal and output it to the mixing unit 314.

[0078] By setting the first frequency up-adjustment unit 311 and the second frequency up-adjustment unit 312, the 100MHz first clock signal is processed twice, so that the output frequency is increased step by step to obtain a second reference signal. Compared with directly multiplying the second reference signal, the frequency adjustment accuracy can be improved. At the same time, it is easy to reduce the stray signal and improve the quality of the second reference signal, thereby improving the quality of the final output signal to improve the accuracy of measurement and control.

[0079] Continue as Figure 4 As shown, the frequency adjustment unit also includes a third frequency down-adjustment unit 313, which is used to receive the third reference signal generated by the first frequency up-adjustment unit 311, perform frequency division processing to obtain a frequency-downregulated first reference signal, and output it to the phase detector 315.

[0080] It can be seen that the first reference signal of this embodiment is a 100MHz clock signal that is first processed by the first frequency up-regulation unit 311 to generate a third reference signal with a higher frequency, and then subjected to frequency division processing by the third frequency down-regulation unit 313 to obtain a frequency-downregulated first reference signal as the input signal of the phase detector 315. This not only improves the regulation accuracy of the signal frequency, but also the frequency division processing can optimize the phase noise, improve the final signal quality, and thus improve the accuracy of measurement and control of the quantum chip.

[0081] The specific structures of the first frequency up-adjusting unit 311, the second frequency up-adjusting unit 312, the third frequency down-adjusting unit 313 and the frequency mixing unit 314 in the frequency up-adjusting circuit 31 of this embodiment are not limited. Figure 5 and Figure 6 , two specific implementation methods are given as follows.

[0082] Figure 5 A schematic diagram of a frequency up-regulation circuit 31 provided in an embodiment of the present utility model Figure 2 ;like Figure 5 As shown, in some implementations of the present embodiment, the first frequency up-regulation unit 311 includes: a first frequency multiplication element 3111, used to perform frequency multiplication processing on the first clock signal of 100 MHz; a direct digital frequency synthesizer 3112, connected to the output end of the first frequency multiplication element 3111, used to generate an output signal with a lower frequency based on the signal after the frequency multiplication processing; a first mixer 3113, electrically connected to the output end of the direct digital frequency synthesizer 3112 and the output end of the first frequency multiplication element 3111, used to perform mixing processing based on the output signal of the direct digital frequency synthesizer 3112 and the output signal of the first frequency multiplication element 3111 to obtain the third reference signal and output it to the second frequency up-regulation unit 312.

[0083] The first frequency up-regulation unit 311 of this embodiment can accurately adjust the frequency and phase of the output signal to improve the signal quality by setting the first frequency multiplication element 3111, the direct digital frequency synthesizer 3112 and the first mixer 3113. In addition, by using the combination of DDS (direct digital frequency synthesizer 3112) + phase-locked loop system, a frequency step of <0.1KHz can be achieved.

[0084] Continue as Figure 5As shown: In some implementations of the present embodiment, the second frequency up-regulation unit 312 includes: a second frequency multiplication element 3121, used to perform frequency multiplication processing on the third reference signal output by the first frequency up-regulation unit 311; a first digital control divider 3123, electrically connected to the output end of the second frequency multiplication element 3121, used to perform frequency division processing on the signal after the frequency multiplication processing to obtain the second reference signal and output it to the mixing unit 314.

[0085] The second frequency up-regulation unit 312 of this embodiment can achieve precise control of the output signal frequency to improve signal quality by configuring the second frequency multiplication element 3121 and the first digital control frequency divider 3123 .

[0086] Continue as Figure 5 As shown: In some implementations of this embodiment, the third frequency down-adjustment unit 313 includes a second digitally controlled frequency divider 3131, through which the third reference signal can be accurately divided to obtain the first reference signal. In addition, the frequency division processing can optimize the phase noise and improve the final signal quality to improve the accuracy of the measurement and control of the quantum chip.

[0087] Continue as Figure 5 As shown: In some implementations of this embodiment, the frequency mixing unit 314 includes: a second frequency mixer 3141, which is used to perform frequency mixing based on the received second reference signal and the first feedback signal output by the third frequency divider 318 in the phase-locked loop system, so as to reduce the frequency of the first feedback signal to obtain a second feedback signal with the same frequency as the first reference signal, and output it to the phase detector 315 in the phase-locked loop system. At this time, the frequency mixing unit 314 performs a frequency mixing process through a second frequency mixer 3141 to obtain the desired signal. Of course, in actual applications, multiple frequency mixers can also be set in the frequency mixing unit 314 to obtain the desired signal through multiple frequency mixing processes.

[0088] Figure 6 A schematic diagram of a frequency up-regulation circuit 31 provided in an embodiment of the present utility model Figure 3 ;like Figure 6 As shown, in some other implementations of this embodiment, the first frequency increasing unit 311 Figure 5 On the basis of the first frequency up-regulation unit 311, it also includes a first amplifying and filtering element 3114 electrically connected between the first frequency multiplying element 3111 and the direct digital frequency synthesizer 3112, which is used to power amplify and filter the signal after multiplication processing and output it to the direct digital frequency synthesizer 3112.

[0089] By providing the first amplifying and filtering element 3114, the signal is amplified and filtered, thereby increasing the signal strength and reducing unnecessary phase noise, thereby effectively improving the signal quality.

[0090] Specifically, the first amplifying and filtering element 3114 includes a filter and an amplifier, and the specific number of the filter and the amplifier is determined according to specific needs. Exemplarily, the first amplifying and filtering element 3114 includes a filter and an amplifier connected in series, the output end of the amplifier is electrically connected to the direct digital frequency synthesizer 3112, and the input end of the filter is electrically connected to the first frequency multiplication element 3111. The specific type of the filter in this embodiment is not limited, and it can be a low-pass filter, which is specifically determined according to the parameters of the signal to be filtered. The specific type of the amplifier in this embodiment is not limited, and it can be a low phase noise amplifier.

[0091] Continue as Figure 6 As shown: In some other implementations of this embodiment, the second frequency increasing unit 312 Figure 5 On the basis of the second frequency up-regulation unit 312, it also includes a second amplifying and filtering element 3122 electrically connected between the second frequency multiplying element 3121 and the first digital control divider 3123, which is used to power amplify and filter the signal after multiplication processing and output it to the first digital control divider 3123.

[0092] By providing the second amplifying and filtering element 3122, the signal is amplified and filtered, thereby increasing the signal strength and reducing unnecessary phase noise, thereby effectively improving the signal quality.

[0093] Specifically, the second amplifying and filtering element 3122 includes a filter and an amplifier, and the specific number of the filter and the amplifier is determined according to specific needs. Exemplarily, the second amplifying and filtering element 3122 includes a filter and an amplifier connected in series, the output end of the amplifier is electrically connected to the first digital control divider 3123, and the input end of the filter is electrically connected to the second frequency multiplication element 3121. The specific type of the filter in this embodiment is not limited, and it can be a low-pass filter. The specific type of the amplifier in this embodiment is not limited, and it can be a low phase noise amplifier.

[0094] Continue as Figure 6As shown: In some other implementations of this embodiment, the frequency mixing unit 314 includes: a fourth amplifying and filtering element 3142, which is used to amplify and filter the first feedback signal output by the third frequency divider 318 in the phase-locked loop system; a second mixer 3141, which is used to perform frequency mixing based on the received second reference signal and the first feedback signal after amplification and filtering, so that the frequency of the first feedback signal is down-regulated to obtain a second feedback signal with the same frequency as the first reference signal, and output it to the phase detector 315 in the phase-locked loop system. By setting the fourth amplifying and filtering element 3142, the signal is amplified and filtered, and unnecessary phase noise is reduced while the signal strength is improved, so as to effectively improve the signal quality.

[0095] Specifically, the fourth amplifying and filtering element 3142 includes a filter and an amplifier, and the specific number of the filter and the amplifier is determined according to specific needs. Exemplarily, the fourth amplifying and filtering element 3142 includes a filter and an amplifier connected in series, the input end of the amplifier is electrically connected to the third frequency divider 318 in the phase-locked loop system, and the output end of the filter is electrically connected to the second mixer 3141. In this embodiment, the specific type of the filter is not limited, and it can be a low-pass filter. In this embodiment, the specific type of the amplifier is not limited, and it can be a low phase noise amplifier.

[0096] In this embodiment, Figure 5 and Figure 6 In the embodiment, the specific types of the first frequency multiplying element 3111 and the second frequency multiplying element 3121 are not limited and may be a comb spectrum generator or a frequency multiplier.

[0097] Combine the following Figure 6 The specific process of the signal generator of this embodiment generating the second measurement and control signal of about 12 GHz based on the clock signal of 100 MHz is given as follows:

[0098] The first clock signal of 100 MHz is frequency-multiplied to about 1 GHz by the first frequency multiplying element 3111, and then is processed by the first amplifying and filtering element 3114 and DDS to output a signal of several tens of MHz, for example, a 58.9 MHz signal; the first clock signal of 100 MHz is also frequency-multiplied to about 1.7 GHz by the first frequency multiplying element 3111, and then is input into the second mixer 3141 with the 58.9 MHz signal to obtain a third reference signal of about 1.6 GHz through mixing processing; the third reference signal of about 1.6 GHz can be divided into two paths by the power divider 21, one path is output to the second digital control divider 3131, and is divided into a signal of about 102 MHz as the first reference signal, and the other path is output to the second frequency multiplying element 3121, and is successively processed by the second frequency multiplying element After processing by the component 3121, the second amplifying and filtering element 3122, and the first digital control divider 3123, a second reference signal of about 6.1 GHz is obtained. The second reference signal of about 6.1 GHz and the first feedback signal of 6 GHz obtained after frequency division processing by the third divider 318 in the phase-locked loop system (the frequency division coefficient of the phase-locked loop system is 2 at this time) are mixed by the first mixer 3113 to output a second feedback signal of about 102 MHz to the phase detector 315; the phase detector 315 generates an error signal based on the phase difference between the first reference signal of about 102 MHz and the second feedback signal of about 102 MHz, and the error signal is output to the loop filter 317 to generate a control voltage signal, and the voltage controlled oscillator 316 outputs a second measurement and control signal of 12 GHz for controlling the quantum bit based on the control voltage signal.

[0099] Of course, the signal generator of this embodiment can also generate a second measurement and control signal of about 13.5 GHz based on a 100 MHz clock signal, and through simulation experiments, the phase noise is about -110 dBC / Hz; if a phase-locked loop system is directly used, a second measurement and control signal of about 13.5 GHz is generated based on a 100 MHz clock signal, and through simulation experiments, the phase noise is about -93 dBC / Hz. It can be seen that the signal generator of this embodiment reduces the phase noise and improves the signal quality compared with the phase-locked loop system.

[0100] Figure 7 A schematic diagram of a power adjustment circuit 32 provided in an embodiment of the present utility model Figure 1 ;like Figure 7As shown: In some implementations of this embodiment, the power adjustment circuit 32 includes a plurality of cascaded third amplifying and filtering elements 321, and a variable attenuation element 322 electrically connected between any two adjacent third amplifying and filtering elements 321, the third amplifying and filtering element 321 at the first stage is electrically connected to the output end of the frequency up-regulation circuit 31, and the third amplifying and filtering element 321 at the last stage outputs the first measurement and control signal; the third amplifying and filtering element 321 is used to perform power amplification and filtering processing on the signal; the variable attenuation element 322 is used to perform adjustable attenuation on the power of the signal. By setting a plurality of third amplifying and filtering elements 321, the power of the first measurement and control signal can be increased, and by setting a variable attenuation element 322, the power can be finely adjusted to achieve a large dynamic small step of the power of the first measurement and control signal, so as to improve the accuracy of the first measurement and control signal, thereby improving the measurement and control accuracy.

[0101] In this embodiment, the number of the third amplifying and filtering elements 321 in the power adjustment circuit 32 is not specifically limited, and can be 2, 3 or more; the third amplifying and filtering element 321 includes a filter and an amplifier, and the specific number of the filter and the amplifier is determined according to specific needs. For example, the third amplifying and filtering element 321 includes 1 filter and 1 amplifier connected in series. In this embodiment, the specific type of the filter is not limited, and can be a low-pass filter or a high-pass filter. In this embodiment, the specific type of the amplifier is not limited, and can be a low phase noise amplifier.

[0102] In this embodiment, the type of the variable attenuation element 322 is not specifically limited, and may include a digitally controlled attenuator and / or a voltage-controlled attenuator 3223 . The number of digitally controlled attenuators and voltage-controlled attenuators 3223 is not specifically limited.

[0103] Figure 8 A schematic diagram of a power adjustment circuit 32 provided in an embodiment of the present utility model Figure 2 ;like Figure 8 As shown, in some implementations of the present embodiment, the variable attenuation element 322 includes a first digitally controlled attenuator 3221, a second digitally controlled attenuator 3222 and a voltage-controlled attenuator 3223 connected in series in sequence to achieve fine-tuning of the power of the first measurement and control signal in steps of less than 0.1 dB, thereby improving the accuracy of the first measurement and control signal to improve the accuracy of the measurement and control.

[0104] Based on the same application concept, the embodiment of the present application also proposes a quantum computing measurement and control system, including the above-mentioned multi-channel signal generating device, and the multi-channel signal generating device is used to output a first measurement and control signal to the quantum chip. The quantum computing measurement and control system of the present application includes the above-mentioned multi-channel signal generating device, and therefore has the same beneficial effects as the above-mentioned multi-channel signal generating device, which will not be repeated here.

[0105] Based on the same application concept, the embodiment of the present application also proposes a quantum computer, a quantum computing measurement and control system, and a quantum chip, wherein the quantum chip performs a quantum computing task according to a first measurement and control signal provided by the quantum computing measurement and control system. The quantum computer of the present application includes the above-mentioned quantum computing measurement and control system, and therefore has the same beneficial effects as the above-mentioned quantum computing measurement and control system, which will not be repeated here.

[0106] In the description of this specification, the description with reference to the terms "some embodiments" or "examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0107] The above are only preferred embodiments of the present invention and do not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, may make any equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which shall be deemed as the content of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A multi-channel signal generating device, characterized in that: include: Clock source, used to provide 100MHz reference clock signal; A power division and amplification module, used for power-dividing a 100 MHz reference clock signal provided by the clock source into multiple first clock signals; the power division and amplification module comprises a plurality of power dividers cascaded in sequence and a power amplifier circuit electrically connected between any two adjacent power dividers, and the input end of the power divider at the first stage is connected to the output end of the clock source; Multiple signal processing modules, each of which has an input end connected to an output end of the power divider, are used to receive one first clock signal in a one-to-one correspondence and output multiple first measurement and control signals for controlling quantum bits after processing.

2. The multi-channel signal generating device according to claim 1, characterized in that: Also includes a chassis, and a first PCB board arranged in the chassis; The clock source, the power division amplifier module and the plurality of signal processing modules are integrated on the first PCB board, and the plurality of signal processing modules are arranged in parallel and at intervals.

3. The multi-channel signal generating device according to claim 1, characterized in that: The signal processing module includes a frequency up-regulation circuit and a power regulation circuit electrically connected; The frequency up-regulation circuit is used to output a second measurement and control signal with a frequency corresponding to the operating frequency of the quantum bit; The power adjustment circuit is used to amplify the power of the second measurement and control signal to obtain the first measurement and control signal.

4. The multi-channel signal generating device according to claim 3, characterized in that: The frequency up-regulation circuit comprises a frequency adjustment unit, a frequency mixing unit and a phase-locked loop system; The frequency adjustment unit is used to generate a first reference signal and a second reference signal based on the first clock signal, and output them to the phase-locked loop system and the mixing unit respectively; The frequency mixing unit is configured to perform at least one frequency mixing process based on the received second reference signal and the first feedback signal output by the phase-locked loop system to reduce the frequency of the first feedback signal to obtain a second feedback signal with the same frequency as the first reference signal, and output the second feedback signal to the phase-locked loop system, wherein the difference between the second reference signal and the first feedback signal is equal to the second feedback signal; The phase-locked loop system is used to output the second measurement and control signal based on the received first reference signal and the second feedback signal.

5. The multi-channel signal generating device according to claim 4, characterized in that: The frequency adjustment unit includes a first frequency up-adjustment unit and a second frequency up-adjustment unit; A first frequency increasing unit, configured to generate a third reference signal with a higher frequency based on the first clock signal; The second frequency up-adjusting unit is configured to generate the second reference signal with a higher frequency based on the third reference signal and output the second reference signal to the frequency mixing unit.

6. The multi-channel signal generating device according to claim 5, characterized in that: The first frequency increasing unit comprises: A first frequency multiplying element, used for multiplying the frequency of the first clock signal; A direct digital frequency synthesizer connected to the output end of the first frequency multiplication element, and used to generate an output signal with a lower frequency based on the signal after the frequency multiplication process; A first mixer is electrically connected to the output end of the direct digital frequency synthesizer and the output end of the first frequency multiplication element, and is used for performing mixing processing based on the output signal of the direct digital frequency synthesizer and the output signal of the first frequency multiplication element to obtain the third reference signal and output it to the second frequency up-regulation unit; The second frequency increasing unit includes: A second frequency multiplication element, configured to perform frequency multiplication processing on the third reference signal output by the first frequency up-adjusting unit; The first digitally controlled frequency divider is electrically connected to the output end of the second frequency multiplication element, and is used for performing frequency division processing on the signal after the frequency multiplication processing to obtain the second reference signal and output it to the mixing unit.

7. The multi-channel signal generating device according to claim 6, characterized in that: The first frequency up-regulation unit further comprises a first amplifying and filtering element electrically connected between the first frequency multiplying element and the direct digital frequency synthesizer, for performing power amplification and filtering processing on the multiplied signal and outputting the signal to the direct digital frequency synthesizer; And / or, the second frequency up-regulation unit further includes a second amplifying and filtering element electrically connected between the second frequency multiplying element and the first digitally controlled frequency divider, for performing power amplification and filtering on the frequency multiplied signal and outputting the signal to the first digitally controlled frequency divider; And / or, the frequency adjustment unit further includes a third frequency down-adjustment unit, which is used to receive the third reference signal generated by the first frequency up-adjustment unit, perform frequency division processing to obtain the frequency-downregulated first reference signal, and output it to the phase-locked loop system.

8. The multi-channel signal generating device according to claim 3, characterized in that: The power adjustment circuit includes a plurality of cascaded third amplifying and filtering elements, and a variable attenuation element electrically connected between any two adjacent third amplifying and filtering elements, the third amplifying and filtering element at the first stage is electrically connected to the output end of the frequency up-regulation circuit, and the third amplifying and filtering element at the last stage outputs the first measurement and control signal; The third amplifying and filtering element is used to perform power amplification and filtering processing on the signal; The variable attenuation element is used to adjustably attenuate the power of the signal.

9. A quantum computing measurement and control system, characterized in that: It comprises a multi-channel signal generating device as described in any one of claims 1 to 8, wherein the multi-channel signal generating device is used to output a first measurement and control signal to a quantum chip.

10. A quantum computer, characterized in that: It includes the quantum computing measurement and control system and quantum chip as described in claim 9, and the quantum chip performs quantum computing tasks according to the first measurement and control signal provided by the quantum computing measurement and control system.

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