Packaging module and packaging structure

Abstract

A package module includes an interposer, a plurality of semiconductor dies, and a molding material layer, the interposer including a dummy via formation region having a dummy via, in which an edge of one of the plurality of semiconductor dies is over the dummy via formation region, the molding material layer is on the interposer and encapsulates the plurality of semiconductor dies.

Description

Technical Field

[0001] The disclosed embodiments relate to a semiconductor manufacturing technology, and more particularly to a packaging module and a packaging structure. Background Art

[0002] A probing test is a test that involves using a probe to make electrical contact with a specific node on a semiconductor device. This type of test is usually performed to verify that the semiconductor device meets the required performance specifications before packaging and shipping to customers.

[0003] In a probing test, a probe is positioned over a specific contact pad on a semiconductor device. The probe is then lowered and pressed against the contact pad, establishing an electrical connection between the probe and the contact pad. This process is repeated for all contact pads on the device that need to be tested. Once the probe contacts the contact pad, various electrical tests can be performed to verify that the semiconductor device meets the required specifications. These tests can include measuring resistance, capacitance, or other electrical parameters at various test nodes. The results of the electrical tests can be analyzed to determine whether the semiconductor device meets the required specifications.

[0004] During these probing tests, the semiconductor device may deform, which may cause the interposer to crack. Such deformation may also occur during operation of the semiconductor device due to thermal expansion and differences between the coefficients of thermal expansion (CTE) of the different materials used to form the semiconductor device. In many cases, the top die and substrate of the semiconductor device may induce increased tensile stress on the interposer at the top-die / molding edge because the molding may have less rigidity to support the interposer. Utility Model Content

[0005] Some embodiments of the present disclosure provide a packaging module. The packaging module includes an interposer, which includes a dummy through-hole forming area having at least one dummy through-hole. The packaging module includes a plurality of semiconductor grains located on the interposer layer, wherein an edge of one of the plurality of semiconductor grains is located above the dummy through-hole forming area. The packaging module includes a molding material layer located on the interposer and encapsulating the plurality of semiconductor grains.

[0006] In some embodiments, the molding material layer contacts the edge of the semiconductor die at an interface, and the interface is located above the dummy via formation region.

[0007] In some embodiments, the edge of the semiconductor die is located above a center of the dummy via forming region or above a center of the at least one dummy via, and the dummy via forming region is located below a periphery of the semiconductor die.

[0008] In some embodiments, the interposer includes a semiconductor material layer, and the at least one dummy via is located at: an uppermost portion of the semiconductor material layer; or a lowermost portion of the semiconductor material layer.

[0009] In some embodiments, a thickness of the at least one dummy via is substantially equal to a total thickness of the interposer.

[0010] In some embodiments, the at least one dummy via includes a plurality of dummy vias, and the dummy vias have a dummy via pattern.

[0011] In some embodiments, the dummy vias include a plurality of rows of dummy vias substantially aligned in a direction perpendicular to the edge of the semiconductor die.

[0012] In some embodiments, the dummy vias include a row of dummy vias substantially aligned with the edge of the semiconductor die.

[0013] In some embodiments, the at least one dummy via includes a plurality of dummy vias, and an area ratio of a total area of ​​the dummy vias to an area of ​​the dummy via forming region is in a range of 0.1 to 0.99.

[0014] Some embodiments of the present disclosure provide a packaging structure. The packaging structure includes a packaging substrate and a packaging module located on the packaging substrate. The packaging module includes an interposer, which includes a dummy through-hole forming area having at least one dummy through-hole. The packaging module includes a plurality of semiconductor grains located on the interposer layer, wherein an edge of one of the plurality of semiconductor grains is located above the dummy through-hole forming area. The packaging module includes a molding material layer located on the interposer and encapsulating the plurality of semiconductor grains. The packaging structure also includes a reinforcement ring located on the packaging substrate and surrounding the packaging module. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The concepts of the disclosed embodiments are better understood with reference to the following detailed description and the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features in the drawings are not necessarily drawn to scale. In fact, the sizes of the various features may be arbitrarily enlarged or reduced to make the description clear.

[0016] Figure 1A is a vertical cross-sectional view of a package module according to one or more embodiments.

[0017] Figure 1Bis a plan view (eg, a top-down view) of a package module according to one or more embodiments.

[0018] Figure 1C is a detailed vertical cross-sectional view of a portion of a package module and a corresponding plan view of the portion according to one or more embodiments.

[0019] Figure 1D is a plan view (eg, a top-down view) of an interposer in a package module according to one or more embodiments.

[0020] Figure 2A is a vertical cross-sectional view of an intermediate structure including a semiconductor material layer according to one or more embodiments.

[0021] Figure 2B is a vertical cross-sectional view of an intermediate structure including a TSV and a dummy via in a semiconductor material layer according to one or more embodiments.

[0022] Figure 2C is a vertical cross-sectional view of an intermediate structure including a bonding layer and an upper bonding pad according to one or more embodiments.

[0023] Figure 2D is a vertical cross-sectional view of an intermediate structure including a first semiconductor die and a second semiconductor die according to one or more embodiments.

[0024] Figure 2E is a vertical cross-sectional view of an intermediate structure including a layer of molding material according to one or more embodiments.

[0025] Figure 2F is a vertical cross-sectional view of an intermediate structure after thinning of a semiconductor material layer according to one or more embodiments.

[0026] Figure 2G is a vertical cross-sectional view of an intermediate structure including a plurality of C4 bumps according to one or more embodiments.

[0027] Figure 3 is a flow chart illustrating a method of forming a package module according to one or more embodiments.

[0028] Figure 4A is a vertical cross-sectional view of a package structure including a package module according to one or more embodiments.

[0029] Figure 4B is a plan view (eg, a top-down view) of a package structure including a package module according to one or more embodiments.

[0030] Figure 5A is a vertical cross-sectional view of an intermediate structure including a package substrate having an upper package substrate bonding pad and a lower package substrate bonding pad according to one or more embodiments.

[0031] Figure 5B is a vertical cross-sectional view of an intermediate structure of a package substrate attached to a package substrate according to one or more embodiments.

[0032] Figure 5C is a vertical cross-sectional view of an intermediate structure in which a package underfill layer is formed on a package substrate according to one or more embodiments.

[0033] Figure 5D is a vertical cross-sectional view of an intermediate structure with an adhesive layer applied to a package substrate according to one or more embodiments.

[0034] Figure 5E is a vertical cross-sectional view of an intermediate structure with a stiffener ring attached to (eg, mounted on) a package substrate in accordance with one or more embodiments.

[0035] Fig. 5F is a vertical cross-sectional view of an intermediate structure in which a plurality of solder balls are formed on a package substrate according to one or more embodiments.

[0036] Figure 6 is a flow chart illustrating a method of forming a package module according to one or more embodiments.

[0037] Fig. 7A is a detailed vertical cross-sectional view of a first alternative design of an interposer in accordance with one or more embodiments.

[0038] Figure 7B is a detailed vertical cross-sectional view of a second alternative design of an interposer in accordance with one or more embodiments.

[0039] Fig. 8A is a detailed plan view of a first alternative design pattern for dummy vias in accordance with one or more embodiments.

[0040] Figure 8B is a detailed plan view of a second alternative design pattern for dummy vias in accordance with one or more embodiments.

[0041] Figure 8C is a detailed plan view of a third alternative design pattern for dummy vias in accordance with one or more embodiments.

[0042] Fig.8D is a detailed plan view of a fourth alternative design pattern for dummy vias in accordance with one or more embodiments.

[0043] Fig. 9 is a plan view (eg, a top-down view) of a fifth alternative design pattern of dummy vias in accordance with one or more embodiments.

[0044] Fig.10is a vertical cross-sectional view of an alternative design of a package module in accordance with one or more embodiments.

[0045] The reference numerals are described as follows:

[0046] 13: Bonding layer

[0047] 13a: Upper bonding pad

[0048] 100: Package structure

[0049] 110: Package substrate

[0050] 110a: Upper passivation layer / upper solder mask layer

[0051] 110b: Lower passivation layer / lower solder mask layer

[0052] 110c: Solder ball

[0053] 112: Core

[0054] 112a: Perforation

[0055] 114: Dielectric layer on package substrate

[0056] 114a: Bonding pad on package substrate

[0057] 114b: Metal Interconnect Structure

[0058] 116: Dielectric layer under the package substrate

[0059] 116a: Bonding pad under package substrate

[0060] 116b: Metal Interconnect Structure

[0061] 120: Encapsulation module

[0062] 121: C4 bump

[0063] 121a: Contact pad / metal pillar

[0064] 121b: Solder bump

[0065] 127: Molding material layer

[0066] 140: Semiconductor grains

[0067] 141: (First) Semiconductor Grain

[0068] 142: (Second) Semiconductor Grain

[0069] 153: Die bonding layer

[0070] 155: Die bonding pad

[0071] 200: Intermediary layer

[0072] 201: Through hole cavity

[0073] 202: Semiconductor material layer

[0074] 203: Insulation pad

[0075] 204: Silicon via

[0076] 204a: Bottom surface

[0077] 205: Lower insulation layer

[0078] 300: Carrier substrate

[0079] 310, 320, 330: Steps

[0080] 500: Dummy via

[0081] 500A, 500B, 500C, 500D: dummy via group

[0082] 500 CR : Corner dummy via

[0083] 510: Dummy via formation area

[0084] 610, 620, 630: Steps

[0085] 629: Package bottom fill layer

[0086] 650: Reinforcement ring

[0087] 650a: Inner edge

[0088] 650b: Outer edge

[0089] 660: Adhesive layer

[0090] 1150: Module reinforcement

[0091] 1160: Adhesive

[0092] S 141 : Sidewall

[0093] I 141 :(die / molding material) interface

[0094] D: Overlap distance

[0095] D B :spacing

[0096] D E :distance

[0097] D i :(Inside) distance

[0098] D M : Minimum distance

[0099] D o : Outer distance

[0100] D T : Total distance

[0101] L 141 :length

[0102] W 141 :width

[0103] O 204 : Open mouth

[0104] O 500 : Open mouth

[0105] T: Total thickness / combined thickness

[0106] T V :thickness

[0107] A-A', B-B', C-C': Line DETAILED DESCRIPTION

[0108] The following disclosure provides many different embodiments or examples to implement different features of the embodiments of the present disclosure. The following describes specific examples of components and configurations to simplify the description of the embodiments of the present disclosure. Of course, these specific examples are only for demonstration and are not intended to limit the embodiments of the present disclosure. For example, in the following description, it is mentioned that the first feature is formed on or above the second feature, which means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself limit the relationship between the various embodiments and / or configurations described.

[0109] Furthermore, spatially relative terms, such as "below," "below," "lower," "above," "higher," and the like, may be used herein to describe the relationship between one element or feature illustrated in the drawings and another element or features. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated in the drawings. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially relative terms used herein should be interpreted accordingly. Unless otherwise expressly stated, each element having the same reference symbol is assumed to have the same material composition and have a thickness within the same thickness range.

[0110] After a probing test (e.g., an electrical test (e-test)), a packaged module including one or more semiconductor dies on an interposer may experience various stresses that may cause the interposer to break (e.g., cracks in the interposer). There may be a variety of reasons for the interposer to break during the probing test. First, the probing test may involve applying mechanical pressure to the interposer using a probe, and if the applied force is too great, the interposer may be overloaded, resulting in breakage. Second, the interposer and the semiconductor dies may have different coefficients of thermal expansion (CTE), and during the probing test, the interposer may heat up due to the applied current, resulting in different thermal expansion between the interposer and the dies, which may cause cracks in the interposer. Third, the interposer may contain material defects, such as voids, inclusions, or weak points, which may cause the interposer to break if the packaged module is subjected to the mechanical stress of the probing test. Fourth, the design of the interposer may not fully consider the stresses that occur during the probing test. For example, the interposer may be too thin or lack the necessary reinforcements to withstand the mechanical stress of the probing test.

[0111] Interposer cracks may occur, for example, at the edge of the top die in a package module. Interposer cracks may be caused by flattening of the package module, which may have a certain degree of curved shape due to warping. That is, during the probing test, the package module may be flattened to be substantially flat, causing interposer cracks to occur. When the molding material may have lower rigidity to support the interposer, the top die and the package substrate may cause worse tensile stress on the interposer at the edge of the top die and the molding material (e.g., the top die / molding edge).

[0112] At least one embodiment of the present disclosure may include an enhanced interposer. The interposer may be included in a packaging module including, for example, an integrated wafer system. Specifically, the interposer may include a dummy via pattern in the interposer to enhance the structure of the packaging module and reduce the risk of interposer cracking.

[0113] In at least one embodiment, one or more dummy vias may be placed in a designated area of ​​the interposer. The designated area of ​​the interposer may be near the edge of one or more top dies in the package module. The dielectric layers of the interposer may have a combined thickness T. The thickness T of the dummy via V Can be given as 1μm <T V <T。

[0114] The overlapping distance D between the edge of the top die and the edge of the designated area can be given as D≤2 mm. The top die can have a width W and a length L. Therefore, the designated area for placing the dummy via can be represented by the formula 2D*(L+W)*2 or [4D*(L+W)]. The area of ​​a single dummy via can be given as C. The total area of ​​the dummy via pattern on the designated area can be given as ∑C. Therefore, the area ratio or ratio (∑C / [4D*(L+W)]) of the total area of ​​the dummy via pattern on the designated area to the designated area for placing the dummy via can be in the range of about 0.1 to about 0.99.

[0115] Figure 1A is a vertical cross-sectional view of a packaging module 120 according to one or more embodiments. Figure 1B is a plan view (eg, a top-down view) of a package module 120 according to one or more embodiments. Figure 1A The vertical section in the figure is along Figure 1B The line A-A' in is captured. Figure 1C is a detailed vertical cross-sectional view of a portion of a packaging module 120 and a corresponding plan view of the portion according to one or more embodiments.

[0116] Figure 1D is a plan view (eg, a top-down view) of interposer 200 in package module 120 according to one or more embodiments. Figure 1D The line B-B' in corresponds to Figure 1B The line A-A' in Figure 1A The vertical cross-section of the interposer 200 is taken along Figure 1D (taken from line B-B' in Fig.

[0117] like Figure 1A As shown in FIG. 1 , the package module 120 may include a first semiconductor die 141 and a second semiconductor die 142 (eg, a semiconductor wafer). Figure 1A The semiconductor crystal grains 141 and 142 are shown as having a specific arrangement, but the number of semiconductor crystal grains and the arrangement of semiconductor crystal grains are not limited to Figure 1A Specifically, the first semiconductor die 141 and the second semiconductor die 142 may constitute a semiconductor die group, and the package module 120 may include a plurality of semiconductor die groups. The first semiconductor die 141 and the second semiconductor die 142 may be collectively referred to as semiconductor die 140.

[0118] The packaging module 120 may also include an interposer 200, which may include an inorganic interposer. The interposer 200 may include a semiconductor material layer 202. In at least one embodiment, the semiconductor material layer 202 may include a silicon-based semiconductor material. The semiconductor material layer 202 may include single crystal silicon or polycrystalline silicon. The semiconductor material layer 202 may be doped or undoped with an electrical dopant, such as a p-type dopant or an n-type dopant.

[0119] The interposer 200 may include a plurality of through-hole cavities 201 in the semiconductor material layer 202. The through-hole cavities 201 may extend through the entire semiconductor material layer 202 along the x-direction. The lateral dimensions (e.g., diameter) of the through-hole cavities 201 may be in the range of 0.5 microns to 10 microns, such as 1 micron to 6 microns, but smaller or more lateral dimensions may also be used. In an embodiment, the pattern of the array of through-hole cavities 201 may have a two-dimensional periodicity on the interposer 200.

[0120] An insulating liner 203 may be formed on the outer peripheral portion of the through hole cavity 201 and the upper surface of the semiconductor material layer 202. The insulating liner 203 may include, for example, silicon oxide, silicon nitride, a low-k dielectric material such as carbon-doped oxide, an extremely low-k dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials. The thickness of the insulating liner 203 may be 1% to 20%, for example 2% to 5%, of the lateral dimension of the through hole cavity 201.

[0121] A plurality of through silicon vias (TSVs) 204 may be respectively located in the plurality of through hole cavities 201. The through silicon vias 204 may include at least one conductive material, such as at least one metal material, in the central portion of the through hole cavity 201. The through silicon vias 204 and the front side insulating liner 203 may substantially fill the through hole cavity 201. The through silicon vias 204 may include, for example, a combination of a metal barrier material (e.g., TiN, TaN, WN, MoN, TiC, TaC, WC, etc.) and a metal filling material (e.g., Cu, Co, Ru, Mo, W, etc.). Other suitable metal barrier materials and metal filling materials are also within the intended scope of the present disclosure.

[0122] The interposer 200 may further include a lower insulating layer 205 on the bottom surface of the semiconductor material layer 202. The lower insulating layer 205 may abut the insulating liner 203 in the via cavity 201. The lower insulating layer 205 may include a material that is the same as or similar to that of the insulating liner 203. The lower insulating layer 205 may include, for example, silicon oxide, silicon nitride, a low dielectric constant dielectric material such as carbon-doped oxide, an extremely low dielectric constant dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials.

[0123] like Figure 1A As shown in , a plurality of C4 bumps 121 may be respectively connected to the through silicon vias 204 on the board side surface of the interposer 200. The C4 bumps 121 may be at least partially located on the lower insulating layer 205. The lower insulating layer 205 may be used to electrically insulate the C4 bumps 121 from the semiconductor material layer 202. The C4 bumps 121 may include contact pads 121a (e.g., copper / nickel contact pads) respectively located on the through silicon vias 204 (e.g., in contact with the through silicon vias 204). The C4 bumps 121 may also include solder bumps 121b (e.g., SnAg solder bumps) located on the contact pads 121a. The package module 120 may be connected to a substrate such as a package substrate through the C4 bumps 121.

[0124] like Figure 1A As shown in , the packaging module 120 may further include a bonding layer 13 located on an upper surface (e.g., a wafer side surface) of the interposer 200. The bonding layer 13 may include a dielectric layer, such as silicon oxide, a low dielectric constant dielectric material such as carbon-doped oxide, an extremely low dielectric constant dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials.

[0125] like Figure 1C As shown in , one or more upper bonding pads 13a may be formed in the bonding layer 13 on the upper surface of the interposer 200. The bonding layer 13 may at least partially cover the upper bonding pads 13a. The upper bonding pads 13a may be connected (e.g., electrically coupled) to the silicon through-holes 204 in the interposer 200. The upper bonding pads 13a may include, for example, one or more layers, and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the intended scope of the present disclosure. In at least one embodiment, the material of the upper bonding pads 13a may be the same as the material of the silicon through-holes 204 in the interposer 200.

[0126] The first semiconductor grain 141 and the second semiconductor grain 142 can be attached to (e.g., mounted on) the upper surface of the interposer 200 through the bonding layer 13 and the upper bonding pad 13a. Specifically, the first semiconductor grain 141 and the second semiconductor grain 142 can be attached (e.g., flip-chip mounted) on the upper surface of the interposer 200. That is, the active region of the semiconductor grain 140 can face the interposer 200, and the bulk semiconductor region of the semiconductor grain 140 can be opposite to the active region. The upper surface of the semiconductor grain 140 (e.g., the upper surface of the bulk semiconductor region) can be substantially coplanar. Specifically, the upper surface of the semiconductor grain 140 can be located at the same height measured from the upper surface of the bonding layer 13.

[0127] The semiconductor grain 140 may include a grain bonding layer 153 located on the active region side of the semiconductor grain 140. The grain bonding layer 153 may include a material substantially the same as the material in the bonding layer 13. The grain bonding layer 153 may include a dielectric material, such as silicon oxide, a low dielectric constant dielectric material such as carbon-doped oxide, an extremely low dielectric constant dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials. The semiconductor grain 140 may also include one or more grain bonding pads 155 located in the grain bonding layer 153. The grain bonding pads 155 may be at least partially exposed through the grain bonding layer 153. The grain bonding pads 155 may have a size (e.g., area) substantially the same as the size of the upper bonding pad 13a in the bonding layer 13 in the xy plane.

[0128] The semiconductor die 140 can be bonded to the interposer 200 by hybrid bonding, which can also be referred to as direct bonding or wafer-to-wafer bonding. The hybrid bonding can include a metal portion and a dielectric portion. In at least one embodiment, the hybrid bonding can include a metal-metal bond and an oxide-oxide bond. Specifically, the hybrid bonding can include a bond between the die bonding pad 155 and the upper bonding pad 13a, and a bond between the die bonding layer 153 and the bonding layer 13 (e.g., an oxide layer) on the interposer 200. The hybrid bonding can achieve high-density interconnection and efficient signal transmission between the semiconductor die 140 and the interposer 200.

[0129] Each semiconductor die 140 may include, for example, a semiconductor die, a system on chip (SOC) die, or a system on integrated chips die, and may be implemented by a chip on wafer on substrate technology or an integrated fan-out on substrate technology. Specifically, each semiconductor die 140 may include, for example, semiconductor wafers or chiplets for high performance computing (HPC) applications, artificial intelligence (AI) applications, and 5G cellular network applications, logic wafers (e.g., mobile application processors, microcontrollers, etc.), memory wafers (e.g., high-bandwidth memory (HBM) wafers, hybrid memory cubes (HMC), dynamic random access memory (DRAM) wafers, wide I / O wafers, M-RAM wafers, R-RAM wafers, NAND wafers, static random access memory (SRAM), etc.), central processing unit (CPU) wafers, graphics processing unit (GPU) wafers, field-programmable gate array (FPGA) wafers, networking wafers, application-specific integrated circuits (ASIC) wafers, artificial intelligence / deep neural network (AI / NN) wafers, etc. network, AI / DNN) accelerator chips, etc., co-processors, accelerators, on-chip memory buffers, high data rate transceiver chips, I / O interface chips, IPD chips (e.g., integrated passive devices), power management chips (e.g., power management integrated circuits,The main products include PMIC chips, radio frequency (RF) chips, sensor chips, micro-electro-mechanical-system (MEMS) chips, signal processing chips (e.g., digital signal processing (DSP) chips), front-end chips (e.g., analog front-end (AFE) chips), monolithic 3D heterogeneous chiplet stacking chips, etc.

[0130] In at least one embodiment, the first semiconductor die 141 may include a main die, and the second semiconductor die 142 may include an auxiliary die. In at least one embodiment, the first semiconductor die 141 may include a SOC die, and the second semiconductor die 142 may include a memory die (e.g., a memory / SOC die, an HBM die, etc.).

[0131] The packaging module 120 may also include a molding material layer 127 on and around the semiconductor die 140 and above the interposer 200 between the semiconductor die 140 (e.g., on the bonding layer 13). The molding material layer 127 may be formed on (e.g., covering) and bonded to one or more sidewalls (e.g., all sidewalls) of the semiconductor die 140. In at least one embodiment, the semiconductor die 140 may be substantially encapsulated or "embedded" in the molding material layer 127. The molding material layer 127 may also be formed on and bonded to a surface of the bonding layer 13.

[0132] In at least one embodiment, the molding material layer 127 may contact the sidewall S of the first semiconductor grain 141. 141 , so that the sidewall S of the first semiconductor grain 141 141 At least a portion of the die / molding material interface may constitute 141 . Die / molding material interface I 141 The first semiconductor crystal grain 141 may be formed around the entire periphery of the first semiconductor crystal grain 141. Crystal grain / molding material interface I 141 The first semiconductor grain 141 may be laterally formed on one or more sidewalls S 141 That is, the grain / molding material interface I 141 The entire first semiconductor crystal grain 141 may be wrapped in the x-direction and the y-direction. 141 and the die / molding material interface I 141 The sidewall S may also extend across the entire first semiconductor grain 141 in the z direction. 141and the die / molding material interface I 141 The Z direction may extend from the bottom of the die bonding layer 153 , which may contact the bonding layer 13 on the interposer 200 , to the upper surface of the first semiconductor die 141 .

[0133] The upper surface of the molding material layer 127 may be substantially uniform (e.g., flat). The upper surface of the molding material layer 127 may also be substantially coplanar with the upper surface of the semiconductor die 140. The outer sidewall of the molding material layer 127 may be substantially aligned with the outer sidewall of the bonding layer 13 and the outer sidewall of the interposer 200. In at least one embodiment, the outer sidewall of the package module 120 may be at least partially composed of the outer sidewall of the molding material layer 127, at least partially composed of the outer sidewall of the bonding layer 13, and at least partially composed of the outer sidewall of the interposer 200.

[0134] In at least one embodiment, the molding material layer 127 can be formed of a curable material that can be cured to form a hard solid structure. The molding material layer 127 can include, for example, epoxy molding compound (EMC). In at least one embodiment, the molding material layer 127 can include a polymeric material, particularly an epoxy-based polymeric material. Other suitable molding materials can also be used.

[0135] In at least one embodiment, the molding material layer 127 may have a coefficient of thermal expansion (CTE) substantially similar to that of the interposer 200. In at least one embodiment, the molding material layer 127 may include an additive material (e.g., a filler material) for improving the properties (e.g., thermal conductivity, CTE, etc.) of the molding material layer 127. The additive material may include, for example, metal powder, metal oxide powder, etc. Other materials suitable for use in the molding material layer 127 are also within the intended scope of the present disclosure.

[0136] like Figure 1A As shown in FIG. 1 , the interposer 200 may include one or more dummy vias 500. The dummy vias 500 may be located in a dummy via forming region 510 (defined by Figure 1A ). The dummy via forming region 510 may be located in the semiconductor material layer 202 of the interposer 200. The dummy via forming region 510 may extend along the z direction, for example, from the bottom surface of the lower insulating layer 205 to the upper surface of the insulating liner 203. In at least one embodiment, the distance D between the dummy via forming region 510 and the outer side wall of the package module 120 (for example, the outer side wall of the molding material layer 127) is E It can be in the range of 0.5mm to 5mm.

[0137] like Figure 1AAs shown in , the dummy via 500 (e.g., a filler via, a non-functional via, etc.) can be located at the uppermost portion of the semiconductor material layer 202 and the upper surface of the interposer 200. Specifically, the upper surface of the dummy via 500 can be substantially coplanar with the upper surface of the insulating liner 203 between the bonding layer 13 and the semiconductor material layer 202. The dummy via 500 can be made of one or more layers of rigid material, such as metal, metal alloy, etc. Other suitable materials are also within the intended scope of the present disclosure. The dummy via 500 can be located at the sidewall S of the first semiconductor grain 141. 141 In at least one embodiment, at least a portion of the dummy through hole 500 may be located near the sidewall S of the first semiconductor grain 141. 141 In at least one embodiment, the dummy through hole 500 may be located at the side wall S 141 and the die / molding material interface I 141 Below.

[0138] The dummy vias 500 can reinforce the interposer 200. The dummy vias 500 can help suppress the formation of interposer cracks, such as at the edge of the first semiconductor die 141. Specifically, the dummy vias 500 can suppress the formation of interposer cracks caused by a probing test during which the package module 120 can be substantially flattened. In at least one embodiment, the dummy vias 500 can suppress the formation of interposer cracks at the die / molding material interface. 141 Interlayer cracks are formed.

[0139] The dummy via 500 can also help improve the overall performance and reliability of the packaging module 120. The dummy via 500 can be strategically placed, for example, between the silicon through-holes 204 (e.g., functional through-holes) to match the pitch on the interposer 200 (e.g., the pitch on the entire interposer 200). This can help reduce pitch variations and maintain a more consistent interconnection density, thereby improving production yield and signal integrity. The dummy via 500 can also be configured as a spacer element, which can increase the distance between adjacent silicon through-holes 204. This spacing can help reduce crosstalk (e.g., unwanted signal coupling between adjacent interconnects). Therefore, signal quality can be enhanced and noise can be reduced. The dummy via 500 can also help balance the thermal expansion mismatch between different components. Specifically, by more evenly distributing the difference in coefficient of thermal expansion (CTE), the mechanical stress on the interposer 200 can be reduced, thereby minimizing the risk of warping and other reliability issues.

[0140] like Figure 1B As shown in FIG. 1 , the upper surface of the semiconductor grain 40 may be exposed through the molding material layer 127. The second semiconductor grain 142 may be located on one side (in the x-direction) of the first semiconductor grain 141. The width W of the first semiconductor grain 141 in the x-direction is141 The length L of the first semiconductor grain 141 in the y direction may be greater than the width of the second semiconductor grain 142 in the x direction. 141 It may be smaller than the length of the second semiconductor grain 142 in the y direction.

[0141] For ease of understanding, the position of the dummy via formation region 510 in the underlying interposer 200 is Figure 1B is shown by shading and outlined by dotted lines. Figure 1B As shown in FIG. 1 , the dummy via forming region 510 may have a frame shape in a plan view. The first semiconductor grain 141 may overlap the dummy via forming region 510 by an overlap distance D. The overlap distance D may be less than or equal to 2 mm. The total distance D between the inner edge and the outer edge of the dummy via forming region 510 may be less than or equal to 2 mm. T It can be given as 2D. The total distance D between the inner edge and the outer edge of the dummy via forming area 510 is T Can be less than or equal to 4mm.

[0142] The center of the dummy through hole forming region 510 may be aligned with the side wall S 141 and the die / molding material interface I 141 In at least one embodiment, the center of the dummy via forming region 510 may be aligned with the side wall S 141 and a grain / molding material interface I around the entire periphery of the first semiconductor grain 141 141 In at least one embodiment, the total distance D of the dummy via formation area 510 is T The dummy via forming region 510 may be substantially uniform around the entire periphery of the first semiconductor die 141. In at least one embodiment, the dummy via forming region 510 may have a substantially box-shaped shape without a top and a bottom and having a wall thickness D T . 。

[0143] In a plan view, the area of ​​the dummy via forming region 510 may be given as (2×2D(L 141 ))+(2x2D(W 141 ))=4Dx(L 141 +W 141 In addition, a single dummy via 500 ( Figure 1B The area of ​​the dummy via 500 (e.g., dummy via pattern) in the dummy via formation region 510 is given as C, and the total area of ​​the dummy via 500 (e.g., dummy via pattern) in the dummy via formation region 510 in the area can be given as ∑C. Therefore, the ratio of the total area of ​​the dummy via 500 to the dummy via formation region 510 (also referred to as the area ratio) can be given by the formula ∑C / [4Dx(L 141 +W 141)] The area ratio may be in the range of about 0.1 to about 0.99. Therefore, the total area of ​​the dummy via 500 may account for 10% to 99% of the area of ​​the dummy via forming region 510.

[0144] Reference Figure 1C , Figure 1C The upper part is a detailed vertical cross-sectional view of the packaging module 120, and Figure 1C The lower part is a plan view of the packaging module 120. Figure 1C As shown in the upper part of , the dummy via 500 may have a substantially trapezoidal vertical cross-sectional shape. The horizontal cross-sectional shape may be circular, elliptical, hexagonal, or any polygonal shape. Other vertical and horizontal cross-sectional shapes of the dummy via 500 are also within the intended scope of the present disclosure. The dummy via 500 may have a thickness T V , and extends from the upper surface of the insulating liner 203 into the semiconductor material layer 202. The dummy via 500 may be separated (eg, electrically isolated) from the TSV 204 by the insulating liner 203 and the semiconductor material layer 202. Specifically, the minimum distance D between the dummy via 500 and the TSV 204 is m (e.g., the minimum lateral distance) may be at least 50 microns. Figure 1C The minimum distance D in m It is shown as being on the left side of the dummy through hole 500, but a person skilled in the art would understand that the minimum distance D m It may occur between the right side of the dummy via 500 and the corresponding through silicon via 204. The dummy via 500 may also be separated (e.g., electrically isolated) from other conductive structures (e.g., metal structures) in the interposer 200 and the upper bonding pad 13a in the bonding layer 13. In addition, the interposer 200 may have a total thickness T including the thickness of the insulating liner 203, the thickness of the semiconductor material layer 202, and the thickness of the lower insulating layer 205. The thickness T of the dummy via 500 is V The total thickness T of the interposer 200 may be greater than 1 μm and less than or equal to 1 μm (eg, 1 μm <T V ≤T).

[0145] like Figure 1C As shown in the lower portion of , the dummy via 500 may have a substantially circular shape in a plan view. Other plan view shapes of the dummy via 500 are also within the contemplated scope of the present disclosure. The center of the dummy via 500 may be substantially aligned with the center of the dummy via forming region 510. The maximum diameter of the dummy via 500 (e.g., the diameter of the upper surface of the dummy via 500) may be less than the total distance D between the inner edge and the outer edge of the dummy via forming region 510. T .

[0146] Refer again Figure 1D For ease of understanding, the outlines of the first semiconductor grain 141 and the second semiconductor grain 142 are shown in the plan view of the interposer 200. Figure 1D As shown in FIG. 1 , a plurality of dummy vias 500 may be formed on the sidewall S of the first semiconductor grain 141. 141 The center of the dummy through hole 500 may be aligned with the sidewall S surrounding the entire periphery of the first semiconductor grain 141. 141 and the die / molding material interface I 141 Therefore, in at least one embodiment where the first semiconductor die 141 has a rectangular shape, the dummy vias 500 may be arranged to have a substantially similar rectangular shape. The spacing D between the dummy vias 500 is B It may be smaller than the diameter of the dummy through hole 500. The spacing D between the dummy through holes 500 B The dummy via 500 may vary or be substantially uniform around the periphery of the first semiconductor die 141. The dummy via 500 may include a corner dummy via 500 formed under a corner of the first semiconductor die 141. CR .although Figure 1D The dummy vias 500 in FIG. 5 have substantially the same shape and size, but the dummy vias 500 may also have different shapes and sizes.

[0147] like Figure 1D As further shown in FIG. 1 , at the upper surface of the interposer 200, the dummy vias 500 may be separated from the TSVs 204 by the insulating liner 203. In at least one embodiment, the pitch of the TSVs 204 (e.g., in the x-direction and / or the y-direction) may be greater than the spacing D between the dummy vias 500. B .

[0148] FIG. 2A to FIG. 2E Various intermediate structures are shown that may be formed during various stages in a method of forming package module 120 in accordance with one or more embodiments. Figure 2A is a vertical cross-sectional view of an intermediate structure including a semiconductor material layer 202 of an interposer 200 according to one or more embodiments.

[0149] exist Figure 2A In the intermediate structure, the semiconductor material layer 202 may include, for example, a silicon wafer. The through hole cavity 201 may be formed in the upper portion of the silicon wafer. In one embodiment, the silicon wafer may be a commercially available silicon wafer with a diameter of 150 mm, 200 mm, 300 mm, or 450 mm.

[0150] The array of through hole cavities 201 can be formed in the upper portion of the semiconductor material layer 202, for example, by a photolithography process. The photolithography process can include, for example, forming an etch mask layer including a hard mask material (e.g., borosilicate glass) on the semiconductor material layer 202, patterning the etch mask layer into a pattern having an array of discrete openings, and transferring the pattern in the etch mask layer to the upper portion of the semiconductor material layer 202. The depth of the through hole cavities 201 in the intermediate structure can be in the range of 1 micron to 100 microns, but lesser or greater depths can also be used. In one embodiment, the pattern of the array of through hole cavities 201 can have a two-dimensional periodicity on the semiconductor material layer 202.

[0151] Then, an insulating liner 203 (e.g., silicon oxide) may be formed on the sidewalls of the through hole cavity 201 and on the top surface of the semiconductor material layer 202 (e.g., silicon wafer). The insulating liner 203 may be formed by depositing (e.g., by CVD, PVD, or other suitable deposition techniques) a layer of insulating material on the semiconductor material layer 202. The insulating material may be deposited to conformally form on the sidewalls of the through hole cavity 201, so that an opening bounded by the insulating liner 203 on the sidewalls of the through hole cavity 201 may be formed in the through hole cavity 201. 204 .

[0152] Another photolithography process may be performed to form one or more openings in the insulating liner 203 and the semiconductor material layer 202. 500 . Opening O 500 The opening O may be located in the dummy through-hole forming region 510. 500 The position of the dummy via 500 may correspond to the position of the dummy via 500 (see Figure 1D ). Therefore, the opening O 500 The precise arrangement of the opening O can be determined based on the expected position of the first semiconductor die 141 on the interposer 200. 500 The arrangement may be based on the sidewall S of the first semiconductor grain 141 141 is determined by the expected position.

[0153] Opening O 500 The depth of the dummy via 500 may be substantially equal to the thickness T V The photolithography process may include, for example, forming an etch mask layer including a hard mask material (eg, borosilicate glass) on the insulating liner 203 , patterning the etch mask layer to have discrete openings, and transferring the pattern of the etch mask layer to the upper portion of the insulating liner 203 and the semiconductor material layer 202 .

[0154] Figure 2BFIG. 2 is a vertical cross-sectional view of an intermediate structure including a through silicon via 204 and a dummy via 500 in a semiconductor material layer 202 according to one or more embodiments. 204 One or more layers of conductive materials (e.g., metal barrier materials (TiN, TaN, WN, MoN, TiC, TaC, WC, etc.) and metal filling materials (Cu, Co, Ru, Mo, W, etc.) are deposited in the opening O in the through hole cavity 201. 204 Through-silicon vias 204 are formed in the opening O 500 By depositing one or more layers of conductive material in the dummy via 500, the dummy via 500 may be formed at the same time (e.g., using the same deposition process) as the TSV 204. In such an embodiment, the TSV 204 and the dummy via 500 may be formed of substantially the same material. Alternatively, the dummy via 500 may be formed before or after the TSV 204 is formed using a different deposition process.

[0155] The one or more layers of conductive material may be deposited, for example, by CVD, PVD, or other suitable deposition techniques. A planarization process (e.g., a chemical mechanical polishing (CMP) process and / or a recess etching process) may then be performed to remove any excess conductive material from above the horizontal plane including the top surface of the horizontally extending portion of the insulating liner 203. Thus, the upper surface of the TSV 204 may be substantially coplanar with the upper surface of the insulating liner 203.

[0156] It should be noted that the opening O 500 It may also be formed in semiconductor material layer 202 before or while forming via cavity 201. In this case, the upper surface of dummy via 500 may be planarized (eg, by CMP, etc.) to be substantially coplanar with the upper surface of semiconductor material layer 202.

[0157] Figure 2Cis a vertical cross-sectional view of an intermediate structure including a bonding layer 13 and an upper bonding pad 13a according to one or more embodiments. The upper bonding pad 13a can be formed by depositing (e.g., by CVD, PVD or other suitable deposition techniques) one or more metal layers on the interposer 200, the metal layers including metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Specifically, the one or more metal layers can be deposited on the upper surface of the insulating liner 203 and the upper surface of the silicon via 204. Then, the metal layer can be patterned by a photolithography process to form an upper bonding pad 13a in contact with the silicon via 204 in the interposer 200. The photolithography process can include forming a patterned photoresist mask (not shown) on the metal material, and etching (e.g., wet etching, dry etching, etc.) the exposed upper surface of the metal material through the opening in the photoresist mask. The photoresist mask may subsequently be removed by ashing, dissolving the photoresist mask, or by consuming the photoresist mask during an etching process.

[0158] In at least one embodiment, the upper bonding pad 13a may include an underbump metallurgy (UBM) layer stack. The order of the material layers within the UBM layer stack may be selected so that the welding material portion may be subsequently bonded to the portion of the UBM layer stack. The layer stacks that can be used for the UBM layer stack include, but are not limited to, stacks of Cr / Cr-Cu / Cu / Au, Cr / Cr-Cu / Cu, TiW / Cr / Cu, Ti / Ni / Au, and Cr / Cu / Au. Other suitable materials are also within the intended scope of the present disclosure. The thickness of the UBM layer stack may be in the range of 5 microns to 60 microns, for example, 10 microns to 30 microns, but a smaller or larger thickness may also be used. A photoresist layer may be applied over the UBM layer stack and may be lithographically patterned to form an array of discrete patterned photoresist material portions. An etching process may be performed to remove the unmasked portion of the UBM layer stack. The etching process may be an isotropic etching process or an anisotropic etching process. The remainder of the UBM layer stack may form the upper bonding pad 13a. In at least one embodiment, the upper bonding pads 13 a may be arranged in a two-dimensional array, which may be a two-dimensional periodic array (eg, a rectangular periodic array).

[0159] Then, a bonding layer 13 may be formed on the interposer 200 above the upper bonding pad 13a. The bonding layer 13 may be formed by depositing (e.g., by CVD, PVD, or other suitable deposition techniques) one or more layers of dielectric material, such as silicon oxide, a low dielectric constant dielectric material such as carbon-doped oxide, an extremely low dielectric constant dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable material. The dielectric material may then be planarized (e.g., by wet etching, dry etching, etc.) until the upper bonding pad 13a is exposed. Thus, the bonding layer 13 may be formed to have an upper surface that is substantially coplanar with the upper surface of the upper bonding pad 13a.

[0160] Figure 2D 1 is a vertical cross-sectional view of an intermediate structure including a first semiconductor die 141 and a second semiconductor die 142 according to one or more embodiments. The first semiconductor die 141 and the second semiconductor die 142 may be placed on the bonding layer 13, for example, by using an electromechanical pick-and-place (PNP) machine. Figure 2D As shown in FIG. 1 , the first semiconductor grain 141 may be positioned on the bonding layer 13 so that the sidewall S of the first semiconductor grain 141 141 Substantially aligned with the dummy via 500 (eg, the center of the dummy via 500 ).

[0161] A hybrid bonding process may be performed to bond the first semiconductor die 141 and the second semiconductor die 142 to the interposer 200. The hybrid bonding process may form, for example, a metal-metal bond / bond between the die bonding pad 155 and the upper bonding pad 13a. The hybrid bonding process may also form, for example, an oxide-oxide bond / bond between the die bonding layer 153 and the bonding layer 13. It should be noted that the hybrid bonding process may utilize less than all of the die bonding pads 155, less than all of the upper bonding pads 13a, less than all of the bonding layer 13, and less than all of the die bonding layer 153.

[0162] The hybrid bonding process may optionally include, for example, a surface preparation step in which the surface of the semiconductor die 140 and the surface of the bonding layer 13 are prepared by cleaning and removing any contaminants or oxides that may interfere with bonding. The surface preparation step can help achieve optimal bonding quality. An alignment step may be performed in which the semiconductor die 140 is more accurately aligned with the interposer 200 to help ensure accurate positioning of the interconnect. The alignment step may be performed, for example, using alignment marks or an optical alignment system. Once aligned, the semiconductor die 140 may be brought into close contact with the interposer 200. Depending on the specific bonding technology used, the bonding process may be performed at room temperature (room temperature bonding) or at an elevated temperature (thermal bonding).

[0163] In the bonding process, the grain bonding layer 153 and the bonding layer 13 can be activated to form a chemical bond / bond (e.g., an oxide-oxide bond / bond) at the atomic level. In at least one embodiment, the grain bonding layer 153 and the oxide layer in the bonding layer 13 can contact each other, thereby allowing oxygen atoms to migrate therebetween and form covalent bonds. In at least one embodiment, elevated temperature and pressure can be applied to form an oxide-oxide bond / bond. While forming the oxide-oxide bond / bond, a metal-metal bond / bond can be formed between the grain bonding pad 155 and the metal layer of the upper bonding pad 13a. In at least one embodiment, elevated temperature and pressure can be applied to form a metal-metal bond / bond by diffusion or solid-state reactions.

[0164] Figure 2E 1 is a vertical cross-sectional view of an intermediate structure including a molding material layer 127 according to one or more embodiments. Liquid molding material (e.g., epoxy molding compound) may be dispensed into the molded product using a suitable dispensing tool. Figure 2D The molding material layer 127 is formed on the intermediate structure of the semiconductor die 140. The molding material layer 127 may be dispensed on the intermediate structure to have a height higher than that of the upper surface of the semiconductor die 140.

[0165] In at least one embodiment, the distribution of the molding material can be automated. Specifically, various aspects of the distribution process can be computer controlled by a control system (e.g., an electronic control system; a central processing unit (CPU)). In at least one embodiment, the start of the distribution of the molding material, the flow rate of the distribution of the molding material, and the stop of the distribution of the molding material can be controlled by the control system. The control system can be programmed to distribute a predetermined amount of molding material, for example, based on various input parameters. The input parameters can include, for example, the volume of the space around the bonding layer 13, the size of the semiconductor grain 140, etc.

[0166] In at least one embodiment, the molding material of the molding material layer 127 may include a capillary material (e.g., a capillary underfill type material). The molding material may have a low viscosity. Specifically, the viscosity may be less than 5,000 cP at 10 rpm. In at least one embodiment, the molding material may include a low viscosity suspension of a thermally conductive material (e.g., a metal, a metal oxide) in a prepolymer. The low viscosity may help facilitate the transport of the molding material around the semiconductor die 140. The low viscosity may also help avoid the formation of voids in the molding material layer 127. In at least one embodiment, the molding material layer 127 may be substantially free of voids.

[0167] After the molding material layer 127 is sufficiently cured, the molding material layer 127 may be planarized to make the upper surface of the molding material layer 127 substantially coplanar with the upper surface of the semiconductor die 140. The molding material layer 127 may be planarized, for example, by grinding, chemical mechanical polishing (CMP), or other suitable planarization techniques.

[0168] Figure 2F 2 is a vertical cross-sectional view of an intermediate structure after the semiconductor material layer 202 is thinned according to one or more embodiments. After planarizing the molding material layer 127, a carrier substrate 300 (eg, a carrier wafer) may be attached to Figure 2E The upper surface of the intermediate structure. The carrier substrate 300 may include, for example, a circular wafer or a rectangular wafer. The lateral dimension of the carrier substrate 300 (for example, the diameter of a circular wafer or the side length of a rectangular wafer) may be in the range of 100 mm to 500 mm, for example, 200 mm to 400 mm, but smaller or larger lateral dimensions may also be used. The carrier substrate 300 may include a semiconductor substrate, an insulating substrate, or a conductor substrate. The carrier substrate 300 may be transparent or opaque. The thickness of the carrier substrate 300 may be sufficient to provide mechanical support for the interposer array to be formed thereon. For example, the thickness of the carrier substrate 300 may be in the range of 60 microns to 1 mm, but smaller or larger thicknesses may also be used.

[0169] An adhesive layer (not shown) may be applied to the top surface of the carrier substrate 300. In one embodiment, the carrier substrate 300 may include an optically transparent material, such as glass or sapphire. In this embodiment, the adhesive layer may include a light-to-heat conversion (LTHC) layer. The LTHC layer is a solvent-based coating applied using a spin coating method. The LTHC layer may be a layer that converts ultraviolet light into heat, causing the LTHC layer to lose adhesion. Alternatively, the adhesive layer may include a thermally decomposable adhesive material. For example, the adhesive layer may include an acrylic pressure-sensitive adhesive that decomposes at an elevated temperature. The debonding temperature of the thermally decomposable adhesive material may be in the range of 150°C to 400°C. Other suitable thermally decomposable adhesive materials that decompose at other temperatures are also within the intended scope of the present disclosure.

[0170] After attaching the carrier substrate 300 to the upper surface of the intermediate structure, the intermediate structure may be flipped (e.g., inverted). Then, the backside surface of the semiconductor material layer 202 (e.g., silicon wafer) may be thinned by performing a polishing process. In at least one embodiment, the semiconductor material layer 202 may be thinned by performing a CMP process. The polishing process may be performed until the bottom surface 204a of the through silicon via 204 is exposed.

[0171] The backside surface of the semiconductor material layer 202 may then be vertically recessed, for example by performing an isotropic etching process that selectively removes silicon relative to the insulating liner 203 and the through silicon via 204. In an illustrative example, a wet etching process using potassium hydroxide may be performed to vertically recess the backside surface of the semiconductor material layer 202 by a vertical recess distance. The vertical recess distance may be in the range of 100 nm to 500 nm, although smaller or larger vertical recess distances may also be used.

[0172] Then, a lower insulating layer 205 may be formed on the back side surface of the recess of the semiconductor material layer 202. The lower insulating layer 205 may be formed, for example, by depositing an insulating material such as silicon oxide on the back side surface of the recess of the semiconductor material layer 202. The thickness of the lower insulating layer 205 may be approximately equal to or greater than the vertical recess distance of the back side silicon surface of the semiconductor material layer 202. Then, a planarization process (e.g., a polishing process) may be performed to remove a portion of the lower insulating layer 205 and make the surface of the lower insulating layer 205 coplanar with the bottom surface 204a of the through silicon via 204.

[0173] Figure 2G is a vertical cross-sectional view of an intermediate structure including a plurality of C4 bumps 121 according to one or more embodiments. The plurality of C4 bumps 121 may be formed to contact the bottom surface 204a of the through silicon via 204. The C4 bumps 121 may be formed, for example, by forming a metal pillar 121a (e.g., a copper pillar) on the bottom surface 204a through an electroplating process. Solder bumps 121b may then be formed on the metal pillars 121a through a suitable process (e.g., deposition, electroplating, etc.).

[0174] In at least one embodiment, a bonding pad (not shown) may be formed on the bottom surface 204a of the TSV 204, and the C4 bump 121 may be formed on the bonding pad. In at least one embodiment, one or more under-bump metallization (UBM) layers (not shown) may be formed on the bottom surface 204a of the TSV 204 (or on the bonding pad, if present), and the metal pillar 121a may be formed on the UBM layer. That is, the C4 bump 121 may be formed to contact the TSV 204 through the UBM layer and / or the bonding pad.

[0175] After forming the C4 bumps 121, the carrier substrate 300 may be detached from the intermediate structure. In some embodiments, the carrier substrate 300 and the adhesive layer (not shown) may be removed by backside grinding. Alternatively, if the carrier substrate 300 includes an optically transparent material and the adhesive layer includes a light-to-heat conversion material, the carrier substrate 300 may be detached using irradiation through the carrier substrate 300. If the adhesive layer includes a thermally decomposable adhesive material, the carrier substrate 300 may be detached using an annealing process or laser irradiation. A suitable cleaning process may be performed to remove the remaining portion of the adhesive layer.

[0176] In at least one embodiment, a plurality of package modules 120 may be formed simultaneously in a wafer-level process. In this case, after forming the C4 bumps 121, a singulation process may be performed to singulate the package modules 120. For example, the singulation process may be performed by sawing the interposer 200 (e.g., and the molding material layer 127 formed thereon) along a cutting line using a dicing saw. The cutting line may be located around the entire periphery of the semiconductor die 140. In at least one embodiment, the cutting line may be positioned so that there is a sufficient distance D between the dummy via formation area 510 and the outer sidewall of the package module 120 (e.g., the outer sidewall of the molding material layer 127). E In at least one embodiment, the distance D between the dummy via forming area 510 and the outer side wall of the packaging module 120 is E It can be in the range of 0.5mm to 5mm.

[0177] Figure 3 is a flow chart illustrating a method of forming a package module according to one or more embodiments. Figure 2A , Figure 2B and Figure 3 , step 310 includes forming an interposer 200 including a region having a dummy via 500. Figure 2D and Figure 3 Step 320 includes attaching a plurality of semiconductor dies 140 to the interposer 200 , wherein an edge of a semiconductor die 141 among the plurality of semiconductor dies 140 is located above a region having the dummy via 500 . Figure 2E and Figure 3 , step 330 includes forming a molding material layer 127 on the interposer around the plurality of semiconductor dies 140 .

[0178] FIG. 4A to FIG. 4B A package structure 100 including a package module 120 is shown in accordance with one or more embodiments. Figure 4A is a vertical cross-sectional view of a package structure 100 including a package module 120 according to one or more embodiments. Figure 4B is a plan view (eg, a top-down view) of a package structure 100 including a package module 120 according to one or more embodiments. Figure 4A The vertical section in the figure is along Figure 4B The line C-C' in the figure is taken.

[0179] Generally speaking, the package structure 100 may include a package substrate 110, a package module 120 located on the package substrate 110, and a stiffening ring 650 adjacent to the package module 120 and attached and / or fixed to the package substrate 110. The stiffening ring 650 may include an inner edge 650a and an outer edge 650b.

[0180] The package substrate 110 may include, for example, a core 112, a package substrate upper dielectric layer 114 formed on the core 112 (e.g., a first side or wafer side of the package substrate 110), and a package substrate lower dielectric layer 116 formed on the core 112 (e.g., a second side or board side of the package substrate 110). Specifically, the package substrate 110 may include a build-up film substrate, such as an Ajinomoto build-up film (ABF) substrate. That is, in at least one embodiment, each of the package substrate upper dielectric layer 114 and the package substrate lower dielectric layer 116 may be described as an ABF layer.

[0181] The core 112 can help provide rigidity to the package substrate 110. The core 112 can include, for example, an epoxy resin, such as bismaleimide triazine epoxy (BT epoxy) and / or a glass fiber laminate. The core 112 can alternatively or additionally include an organic material, such as a polymer material. Specifically, the core 112 can include a dielectric polymer material, such as polyimide (PI), benzocyclo-butene (BCB) or polybenzobisoxazole (PBO). Other suitable dielectric materials are also within the intended scope of the present disclosure.

[0182] The core 112 may include one or more through vias 112a. The through vias 112a may extend from the lower surface of the core 112 to the upper surface of the core 112. The through vias 112a may allow electrical connection between the upper dielectric layer 114 of the package substrate and the lower dielectric layer 116 of the package substrate. The through vias 112a may include one or more layers and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the intended scope of the present disclosure.

[0183] The dielectric layer 114 on the package substrate may be formed on the upper surface of the core 112. The dielectric layer 114 on the package substrate may include a plurality of layers, and specifically, may include an Ajinomoto build-up film (ABF). The dielectric layer 114 on the package substrate may also include an organic material, such as a polymer material. Specifically, the dielectric layer 114 on the package substrate may include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB) or polybenzobisoxazole (PBO). Other suitable dielectric materials are also within the intended scope of the present disclosure.

[0184] The dielectric layer 114 on the package substrate may include one or more package substrate bonding pads 114a on the wafer side surface of the dielectric layer 114 on the package substrate. Specifically, the bonding pad 114a on the package substrate may be exposed on the wafer side surface of the dielectric layer 114 on the package substrate. The dielectric layer 114 on the package substrate may also include one or more metal interconnect structures 114b. The metal interconnect structure 114b may be connected to the bonding pad 114a on the package substrate and the through hole 112a in the core 112. The metal interconnect structure 114b may include a metal layer (e.g., a copper trace) and a metal through hole connecting the metal layer. The bonding pad 114a on the package substrate and the metal interconnect structure 114b may include, for example, one or more layers, and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the expected scope of the present disclosure.

[0185] The upper passivation layer 110a may be formed on the wafer side surface of the upper dielectric layer 114 of the package substrate. The upper passivation layer 110a may partially cover the upper bonding pad 114a of the package substrate. The upper passivation layer 110a may include silicon oxide, silicon nitride, a low dielectric constant dielectric material such as carbon-doped oxide, an extremely low dielectric constant dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials.

[0186] The lower dielectric layer 116 of the package substrate may be formed on the lower surface of the core 112. The lower dielectric layer 116 of the package substrate may include a plurality of layers, and specifically, may include an Ajinomoto build-up film (ABF). The lower dielectric layer 116 of the package substrate may also include an organic material, such as a polymer material. Specifically, the lower dielectric layer 116 of the package substrate may include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB) or polybenzobisoxazole (PBO). Other suitable dielectric materials are also within the intended scope of the present disclosure.

[0187] The lower dielectric layer 116 of the package substrate may include one or more lower bonding pads 116a of the package substrate located on the side surface of the board of the lower dielectric layer 116 of the package substrate. Specifically, the lower bonding pad 116a of the package substrate may be exposed on the side surface of the board of the lower dielectric layer 116 of the package substrate. The lower dielectric layer 116 of the package substrate may also include one or more metal interconnect structures 116b. The metal interconnect structure 116b may be connected to the lower bonding pad 116a of the package substrate and the through hole 112a in the core 112. The metal interconnect structure 116b may include a metal layer (e.g., a copper trace) and a metal through hole connecting the metal layer. The lower bonding pad 116a of the package substrate and the metal interconnect structure 116b may include, for example, one or more layers, and may include metals, metal alloys and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are also within the expected scope of the present disclosure.

[0188] The lower passivation layer 110b may be formed on the board side surface of the package substrate lower dielectric layer 116. The lower passivation layer 110b may partially cover the package substrate lower bonding pad 116a. The lower passivation layer 110b may include silicon oxide, silicon nitride, a low dielectric constant dielectric material such as carbon-doped oxide, an extremely low dielectric constant dielectric material such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials.

[0189] In at least one embodiment, the lower dielectric layer 116 of the package substrate may further include one or more dummy through holes (not shown) of the package substrate. The dummy through holes of the package substrate may be formed in the board side surface of the lower dielectric layer 116 of the package substrate, and may or may not be exposed on the board side surface of the lower dielectric layer 116 of the package substrate. The dummy through holes of the package substrate may be substantially aligned with the edge of the reinforcement ring 650. Specifically, the center line of the dummy through hole of the package substrate in the x direction may be substantially aligned with the inner edge 650a of the reinforcement ring 650. The lowermost surface of the dummy through hole of the package substrate may be substantially coplanar with the lowermost surface of the bonding pad 116a under the package substrate and the board side surface of the lower dielectric layer 116 of the package substrate. The dummy through hole of the package substrate may be exposed on the board side surface of the lower dielectric layer 116 of the package substrate, or may be covered by another layer of the package substrate 110 (e.g., the lower passivation layer 110b). The dummy through hole of the package substrate may provide rigidity for the package substrate 110.

[0190] A ball grid array (BGA) including a plurality of solder balls 110c can be formed on the board side surface of the dielectric layer 116 under the package substrate. The solder balls 110c can allow the package structure 100 to be firmly mounted on a substrate such as a printed circuit board (PCB) and electrically coupled to the PCB substrate. The solder balls 110c can contact the bonding pads 116a under the package substrate respectively. Therefore, the solder balls 110c can be electrically connected to the bonding pads 114a on the package substrate through the metal interconnect structure 116b, the perforations 112a and the metal interconnect structure 114b. The solder balls 110c of the BGA can be located below the reinforcement ring 650 and below the package module 120.

[0191] The package module 120 may be attached to the package substrate bonding pad 114a in the package substrate 110 via the C4 bump 121. Specifically, the solder bump portion of the C4 bump 121 may collapse so that the column portion of the C4 bump 121 is bonded to the package substrate bonding pad 114a. A package bottom fill layer 629 may be formed on the package substrate 110, under and around the package module 120, and around the C4 bump 121. The package bottom fill layer 629 may help securely fix the package module 120 to the package substrate 110. The package bottom fill layer 629 may be formed of an epoxy-based polymer material.

[0192] The reinforcement ring 650 may be attached to the package substrate 110 around the package module 120. The reinforcement ring 650 may be securely fixed to the package substrate 110 by an adhesive 660 (e.g., a silicone adhesive or an epoxy adhesive). The reinforcement ring 650 may be formed of a metal such as copper or an aluminum alloy with a nickel coating. The reinforcement ring 650 may provide rigidity to the package substrate 110.

[0193] Refer again Figure 4B , showing the position of the reinforcement ring 650 relative to the package module 120. The reinforcement ring 650 can be located around the entire periphery of the package module 120. The inner edge 650a of the reinforcement ring 650 can be separated from the outer side wall of the package module 120 (e.g., the outer side wall of the molding material layer 127 and / or the outer side wall of the interposer 200) by an inner distance D i In at least one embodiment, the inner distance D i The distance D between the dummy via forming region 510 and the outer side wall of the package module 120 may be less than E In at least one embodiment, the inner distance D i It can be in the range of 0.1mm to 4mm. Figure 4B As shown in i In the longitudinal direction of the package module 120 (eg, Figure 4BThe inner distance D may be greater in the x direction (in the x direction) than in the direction perpendicular to the longitudinal direction of the package module 120. Alternatively, the inner distance D i It may be substantially uniform around the periphery of the package module 120 .

[0194] The outer edge 650b of the reinforcement ring 650 may be separated from the edge of the package substrate 110 by an outer distance D o In at least one embodiment, the outer distance D o The inner distance D between the inner edge 650a of the reinforcement ring 650 and the outer sidewall of the package module 120 (eg, the outer sidewall of the molding material layer 127 and / or the outer sidewall of the interposer 200) may be less than the inner side distance D between the inner edge 650a of the reinforcement ring 650 and the outer sidewall of the package module 120 (eg, the outer sidewall of the molding material layer 127 and / or the outer i In at least one embodiment, the outer distance D o It can be in the range of 0.05 mm to 2 mm. In at least one embodiment, the outer distance D o It may be substantially uniform around the periphery of the reinforcement ring 650 .

[0195] FIG. 5A to FIG. 5F Various intermediate structures are shown in a method of forming package structure 100 according to one or more embodiments. Figure 5A 1 is a vertical cross-sectional view of an intermediate structure including a package substrate 110 having an upper package substrate bonding pad 114a and a lower package substrate bonding pad 116a according to one or more embodiments. A package substrate 110 including a core 112, an upper package substrate dielectric layer 114, and a lower package substrate dielectric layer 116 may be provided.

[0196] The bonding pad 114a on the package substrate can be formed on, for example, the uppermost dielectric layer of the dielectric layer 114 on the package substrate. The bonding pad 114a on the package substrate can be formed to contact the metal interconnect structure 114b. The bonding pad 114a on the package substrate can be formed by depositing a metal layer (e.g., copper, aluminum, or other suitable conductive materials) on the upper surface of the dielectric layer 114 on the package substrate. The metal layer can then be patterned by etching (e.g., by wet etching, dry etching, etc.) to form the bonding pad 114a on the package substrate. Other suitable metal layer materials and etching processes are also within the intended scope of the present disclosure.

[0197] The package substrate lower bonding pad 116a may be formed, for example, on the lowermost dielectric layer of the package substrate lower dielectric layer 116. The package substrate lower bonding pad 116a may be formed to contact the metal interconnect structure 116b. The package substrate lower bonding pad 116a may be formed in a manner similar to forming the package substrate upper bonding pad 114a (e.g., depositing a metal layer, patterning the metal layer by etching, etc.).

[0198] After formation, the upper bonding pad 114a of the package substrate and the lower bonding pad 116a of the package substrate can be selectively subjected to surface roughening treatment (e.g., copper zarazara (CZ) treatment). In the surface roughening treatment, the surface (e.g., copper surface) of the upper bonding pad 114a of the package substrate and the surface (e.g., copper surface) of the lower bonding pad 116a of the package substrate can be etched by an organic acid-based micro-etching solution to produce an ultra-rough surface (e.g., copper surface). The uniquely roughened copper surface morphology of the upper bonding pad 114a of the package substrate and the lower bonding pad 116a of the package substrate can help achieve high copper-resin adhesion.

[0199] Then, a passivation layer 110a on the package substrate and a passivation layer 110b on the package substrate can be formed on the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a, respectively. In at least one embodiment, the passivation layer 110a on the package substrate may include a solder resist layer (e.g., a polymer material), also referred to as a solder mask. The passivation layer 110a on the package substrate may also be referred to as an upper solder resist layer 110a, and the passivation layer 110b on the package substrate may also be referred to as a lower solder resist layer 110b.

[0200] The passivation layer 110a on the packaging substrate and the passivation layer 110b under the packaging substrate can be applied simultaneously. The passivation layer 110a on the packaging substrate and the passivation layer 110b under the packaging substrate can be applied, for example, as a liquid photo-imageable film. For example, the liquid photo-imageable film can be applied by silk-screening or spraying the liquid photo-imageable film on the surface of the packaging substrate 110. The liquid photo-imageable film can be applied on the bonding pad 114a on the packaging substrate and the bonding pad 116a under the packaging substrate. Alternatively, the passivation layer 110a on the packaging substrate and the passivation layer 110b under the packaging substrate can be applied as a dry film photo-imageable film, which can be vacuum laminated to the surface of the packaging substrate 110 and on the bonding pad 114a on the packaging substrate and the bonding pad 116a under the packaging substrate, respectively. The package substrate upper passivation layer 110 a and the package substrate lower passivation layer 110 b may alternatively or additionally be formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, lamination or other suitable deposition techniques.

[0201] like Figure 5AAs shown in , the passivation layer 110a on the package substrate and the passivation layer 110b under the package substrate can be applied to have upper surfaces that are substantially coplanar with the upper surfaces of the bonding pads 114a on the package substrate and the bonding pads 116a under the package substrate, respectively. Alternatively, the passivation layer 110a on the package substrate and the passivation layer 110b under the package substrate can be applied to have a thickness greater than the thickness of the bonding pads 114a on the package substrate and the bonding pads 116a under the package substrate, respectively. In this case, an opening (not shown) can be formed in the passivation layer 110a on the package substrate and the passivation layer 110b under the package substrate (for example, by an etching process (for example, wet etching, dry etching, etc.) in a photolithography process) to expose the bonding pads 114a on the package substrate and the bonding pads 116a under the package substrate, respectively.

[0202] Figure 5B A vertical cross-sectional view of an intermediate structure of a package module 120 attached to a package substrate 110 according to one or more embodiments is shown. The package module 120 can be attached to the package substrate 110, for example, by a flip chip bonding (FCB) process. In the FCB process, the package module 120 can be positioned on the package substrate 110, for example, by an electromechanical pick-and-place (PNP) machine. The C4 bumps 121 on the package module 120 can be lowered onto the package substrate bonding pads 114a of the package substrate 110 and heated to collapse the C4 bumps 121 and bond the C4 bumps 121 to the package substrate bonding pads 114a.

[0203] Figure 5C FIG. 1 is a vertical cross-sectional view of an intermediate structure in which a package bottom filling layer 629 is formed on a package substrate 110 according to one or more embodiments. Figure 5C As shown in , a package underfill layer 629 (e.g., an epoxy-based polymer material) may be dispensed (e.g., injected) onto the package substrate 110, under and around the package module 120, and around the C4 bumps 121. The package underfill layer 629 may then be cured, for example, in a box oven at a temperature in the range of 120° C. to 180° C. for a duration in the range of about 60 minutes to 120 minutes to provide the package underfill layer 629 with sufficient hardness and mechanical strength.

[0204] Figure 5DA vertical cross-sectional view of an intermediate structure of an adhesive layer 660 applied to a packaging substrate 110 according to one or more embodiments is shown. The adhesive layer 660 can be dispensed onto the packaging substrate 110 using a dispensing tool (e.g., an automated dispensing tool). The dispensing tool can dispense the adhesive layer 660 into a frame shape surrounding the packaging module 120. When applied, the adhesive layer 660 can be sufficiently rigid to form a semi-solid bead on the surface of the packaging substrate 110. In at least one embodiment, the viscosity of each adhesive layer 660 when applied can be 50,000 centipoise (cp) or greater. Partly due to the viscosity of the adhesive layer 660, the shape of the semi-solid bead can remain substantially unchanged between the time of application by the dispensing tool and the time when the reinforcement ring 650 is subsequently attached. The position of the frame shape of the adhesive layer 660 can correspond to the position of the reinforcement ring 650 (e.g., see Figure 4B ). Pressing the reinforcement ring 650 onto the adhesive layer 660 may deform the adhesive layer 660.

[0205] Figure 5E A vertical cross-sectional view of an intermediate structure showing a reinforcement ring 650 attached to (e.g., mounted on) a packaging substrate 110 according to one or more embodiments. In at least one embodiment, the packaging substrate 110 with the packaging module 120 can be placed on a flat surface. The reinforcement ring 650 can then be positioned on the packaging substrate 110, for example, by an electromechanical pick-and-place (PNP) machine. The reinforcement ring 650 can then be lowered onto the packaging substrate 110 around the packaging module 120. The reinforcement ring 650 can then be aligned with an adhesive layer 660 formed on the packaging substrate 110. The reinforcement ring 650 can then be pressed down onto the packaging substrate 110 so that the reinforcement ring 650 can be attached to the packaging substrate 110 through the adhesive layer 660.

[0206] The reinforcement ring 650 may be clamped to the package substrate 110 for a period of time to allow the adhesive layer 660 to cure and form a secure bond between the package substrate 110 and the reinforcement ring 650. For example, clamping the reinforcement ring 650 to the package substrate 110 may be performed by using a thermal clamp module. The thermal clamp module may apply a uniform force on the upper surface of the reinforcement ring 650. In one or more embodiments, the thermal clamp module may apply pressure to the reinforcement ring 650 and provide an elevated temperature to promote the curing of the adhesive layer 660.

[0207] Fig. 5FA vertical cross-sectional view of an intermediate structure in which a plurality of solder balls 110c are formed on a package substrate 110 according to one or more embodiments is shown. A plurality of solder balls 110c may be formed on an exposed surface of a bonding pad 116a under the package substrate (e.g., through an opening (not shown) in a passivation layer 110b under the package substrate). The solder balls 110c may be formed, for example, by an electroplating process. The solder balls 110c may be formed, for example, to be located below the reinforcement ring 650, below the package module 120, and between them. A plurality of solder balls 110c may constitute a ball grid array (BGA), which may allow the package structure 100 to be securely mounted (e.g., by surface mount technology (SMT)) on a substrate such as a printed circuit board and electrically coupled to the substrate. The formation of the solder balls 110c may complete the formation of the package structure 100.

[0208] Figure 6 6 is a flow chart illustrating a method of forming a package module according to one or more embodiments. Step 610 includes forming a package module including an interposer, a plurality of dies on the interposer, and a molding material layer on the interposer surrounding the plurality of dies, the interposer including an area having a dummy via, wherein an edge of one of the plurality of dies is located above the area having the dummy via. Step 620 includes attaching the package module to a package substrate. Step 630 includes attaching a reinforcement ring around the package module to the package substrate.

[0209] FIG. 7A to FIG. 7B is a detailed vertical cross-sectional view of an alternative design of interposer 200 in accordance with one or more embodiments. Fig. 7A is a detailed vertical cross-sectional view of a first alternative design of the location of dummy vias 500 formed in interposer 200 according to one or more embodiments. Fig. 7A As shown in FIG. 1 , in a first alternative design, the dummy via 500 may be located at the lowest portion of the semiconductor material layer 202 . The thickness T of the dummy via 500 is V It may be smaller than the thickness T of the interposer 200. Fig. 7A As shown in FIG. 5 , the dummy via 500 may be formed in the dummy via forming region 510, but unlike Figures 1A to 2E as well as FIG. 4A to FIG. 5F Compared with the embodiment shown in , the dummy through hole 500 is formed at the lower part of the dummy through hole forming area. The thickness T of the dummy through hole 500 is V As well as vertical and horizontal cross-sectional area shapes can be Figures 1A to 2E as well as FIG. 4A to FIG. 5F The embodiment shown in is the same.

[0210] Figure 7B FIG. 2 is a detailed vertical cross-sectional view of a second alternative design of interposer 200 according to one or more embodiments. Figure 7BAs shown in FIG. 1 , in a second alternative design, the dummy via 500 may extend in the z direction through the entire thickness of the semiconductor material layer 202 and through the entire thickness of the interposer 200. The center of the dummy via 500 in the z direction may be substantially aligned with the center of the semiconductor material layer 202 in the z direction. The thickness T of the dummy via 500 may be substantially aligned with the center of the semiconductor material layer 202 in the z direction. V can be substantially the same as the total thickness T of the interposer 200 (eg, T V =T; see Figure 1D ).like Figure 7B As shown in FIG. 5 , the dummy via 500 may remain within the dummy via forming region 510, but may have Figures 1A to 2E , FIG. 4A to FIG. 5F as well as Fig. 7A In the embodiment of the much larger thickness T V The vertical and horizontal cross-sectional shapes of the dummy through hole 500 may be Figures 1A to 2E , FIG. 4A to FIG. 5F as well as Fig. 7A The embodiment shown in is the same as that shown in Figure 7B The embodiment shown in shows the dummy via 500 extending through the entire thickness of the interposer 200 , but the dummy via 500 in the second alternative design may be formed to be less than the entire thickness of the interposer 200 .

[0211] FIG. 8A to FIG. 8D is a detailed plan view of an alternative design pattern for dummy vias 500 in accordance with one or more embodiments. Fig. 8A FIG. 5 is a detailed plan view of a first alternative design pattern of dummy vias 500 according to one or more embodiments. Fig. 8A As shown in FIG. 1 , in a first alternative design pattern, the dummy vias 500 may be arranged in an array having multiple columns (along the x-direction) and multiple rows (along the y-direction). The array-shaped dummy vias 500 may be continuously formed around the entire periphery of the first semiconductor die 141 to form a frame-shaped array. Fig. 8A Three rows of dummy vias 500 are shown, but greater or fewer rows of dummy vias 500 are within the contemplated scope of the present disclosure.

[0212] Figure 8B FIG. 5 is a detailed plan view of a second alternative design pattern of dummy vias 500 according to one or more embodiments. Figure 8B As shown in FIG. 1 , in the second alternative design pattern, the dummy via 500 may have a polygonal shape in a plan view. Figure 8B The polygonal shape in is a hexagon, but the polygonal shape is not limited to a hexagon, and may also include a pentagon, an octagon, etc. In addition, the polygonal shape may be regular or irregular. The dummy through hole 500 may also be continuously formed around the entire periphery of the first semiconductor grain 141 to form a frame shape. It should be noted that although Figure 8B One row of dummy vias 500 is shown, but more rows of dummy vias 500 (eg, having a smaller width in the x-direction) are also within the contemplated scope of the present disclosure.

[0213] Figure 8C is a detailed plan view of a third alternative design pattern of dummy vias 500 according to one or more embodiments. Figure 8C As shown in FIG. 1 , in the third alternative design pattern, the dummy via 500 may have a rectangular shape. Specifically, the longitudinal direction of the dummy via 500 may be perpendicular to the sidewall S of the first semiconductor grain 141. 141 In at least one embodiment, the longitudinal direction of the dummy through hole 500 may be perpendicular to the sidewall S of the first semiconductor grain 141. 141 The dummy through hole 500 may also be formed continuously around the entire periphery of the first semiconductor grain 141 to form a frame shape. Figure 8C One row of dummy vias 500 is shown, but more rows of dummy vias 500 (eg, having a smaller length in the x-direction) are also within the contemplated scope of the present disclosure.

[0214] Fig.8D is a detailed plan view of a fourth alternative design pattern of dummy vias 500 according to one or more embodiments. Fig.8D As shown in , in the fourth alternative design pattern, the dummy vias 500 located in the dummy via forming area 510 can have a variety of shapes. These horizontal cross-sectional shapes can include hexagonal, circular, rectangular. In addition, the dummy vias 500 can be arranged in a plurality of offset columns. Fig.8D In the embodiment of FIG. 5 , the dummy via 500 may be located within the dummy via forming region 510 but offset by some distance from the center of the dummy via forming region 510. The dummy via 500 may also be continuously formed around the entire periphery of the first semiconductor die 141 to form a frame shape.

[0215] Fig. 9 is a plan view (eg, a top-down view) of interposer 200 having a fifth alternative design pattern of dummy vias 500 according to one or more embodiments. Fig. 9 As shown in FIG. , in a fifth alternative design pattern, the pattern of dummy vias 500 may include a plurality of separate dummy via groups 500A, 500B, 500C, and 500D. Dummy via groups 500A to 500D (similar to individual dummy vias 500) may be located in a portion of a dummy via formation region 510 that is determined to require structural support. Dummy via groups 500A to 500D may have a regular or irregular arrangement. Although Fig. 9The dummy via groups 500A to 500D in the embodiment have the same number, substantially the same arrangement, and substantially the same shape and size of the dummy vias 500, but the dummy via groups 500A to 500D may also have the dummy vias 500 with different numbers, different arrangements, and different cross-sectional shapes and sizes.

[0216] Fig.10 is a vertical cross-sectional view of an alternative design of a package module 120 according to one or more embodiments. Fig.10 In an alternative design of the present invention, the package module 120 may include a module stiffener 1150 (e.g., an embedded module stiffener). The module stiffener 1150 may be located in the molding material layer 127 adjacent to the semiconductor die 140. In at least one embodiment, the module stiffener 1150 may have an annular shape (e.g., a frame shape) and laterally (in the x-direction and the y-direction) surround the semiconductor die 140. The module stiffener 1150 may be attached to the interposer 200 by an adhesive 1160 (e.g., a silicone adhesive or an epoxy adhesive), which may be substantially similar to the adhesive 660 (e.g., see Figure 4A ). The module reinforcement member 1150 may be formed by connecting with the reinforcement ring 650 (see, for example, Figure 4A and Figure 4B ) are formed of substantially the same material. Specifically, the material of the module reinforcement 1150 may include any kind of metal, alloy, polymer, semiconductor, or any combination of these materials (eg, composite material).

[0217] The shape (e.g., structure) of the module reinforcement 1150 can be any shape. The thickness (e.g., in the z direction) of the module reinforcement 1150 can be in the range of about 0.1 mm to about 5.0 mm. In at least one embodiment, the minimum thickness of the module reinforcement 1150 can be about 0.5 mm. In at least one embodiment, the thickness of the module reinforcement 1150 can be less than the thickness of the semiconductor die 140 in the packaging module 120. The module reinforcement 1150 may or may not be exposed on the upper surface of the molding material layer 127 in which the module reinforcement 1150 is embedded. The module reinforcement 1150 may not have the function of an active or passive device.

[0218] The module reinforcement 1150 can help control the overall warpage in the package module 120. Specifically, the module reinforcement 1150 can reduce the warpage of the package module 120 at low or high temperatures. In at least one embodiment, the material of the module reinforcement 1150 can be selected to provide the module reinforcement 1150 with an appropriate coefficient of thermal expansion (CTE), thereby reducing the warpage of the package module 120. By helping to reduce the warpage of the package module 120 (e.g., reducing the bending (e.g., crying face shape) of the package module 120), the module reinforcement 1150 can help reduce the bending of the interposer 200 during the probing test, thereby reducing the risk of the interposer 200 being broken by the probing test.

[0219] Now refer to Figures 1A to 10 A packaging module 120 may include an interposer 200 including a dummy via forming region 510 having at least one dummy via 500, a plurality of semiconductor grains 140 located on the interposer 200, wherein an edge of a semiconductor grain 141 among the plurality of semiconductor grains 140 may be located above the dummy via forming region 510, and a molding material layer 127 located on the interposer 200 and encapsulating the plurality of semiconductor grains 140.

[0220] In one embodiment, the molding material layer 127 is formed at an interface I 141 The interface I 141 The dummy via formation region 510 may be located above the dummy via formation region 510. In one embodiment, the edge of the semiconductor grain 141 may be located above the center of the dummy via formation region 510. In one embodiment, the edge of the semiconductor grain 141 may be located above the center of at least one dummy via 500. In one embodiment, the dummy via formation region 510 may be located below the periphery of the semiconductor grain 141. In one embodiment, the interposer 200 includes a semiconductor material layer 202, and the at least one dummy via 500 may be located at the uppermost portion of the semiconductor material layer 202 or the lowermost portion of the semiconductor material layer 202. In one embodiment, the thickness T of the at least one dummy via 500 is V The thickness T of the at least one dummy via 500 may be equal to the total thickness T of the interposer 200. In one embodiment, the at least one dummy via 500 may include a plurality of dummy vias 500, and the plurality of dummy vias 500 have a dummy via pattern. In one embodiment, the plurality of dummy vias 500 may include a plurality of columns of dummy vias 500 substantially aligned in a direction perpendicular to the edge of the semiconductor die 141. In one embodiment, the plurality of dummy vias 500 may include a row of dummy vias 500 substantially aligned with the edge of the semiconductor die 141. In one embodiment, the plurality of semiconductor die 140 may be connected to the interposer 200 by hybrid bonding. In one embodiment, the thickness T of the at least one dummy via 500 is VThe thickness T of the interposer 200 may be greater than 1 μm and less than or equal to the total thickness T of the interposer 200. In one embodiment, the overlap distance between the edge of the semiconductor grain 141 and the edge of the dummy via formation region 510 may be less than or equal to 2 mm. In one embodiment, the at least one dummy via 500 may include a plurality of dummy vias 500, and an area ratio of a total area of ​​the plurality of dummy vias 500 to an area of ​​the dummy via formation region 510 may be in a range of 0.1 to 0.99.

[0221] Refer again Figures 1A to 10 A method of manufacturing a package module 120 may include forming an interposer 200 including a dummy via forming region 510 having at least one dummy via 500, attaching a plurality of semiconductor dies 140 to the interposer 200, wherein an edge of a semiconductor die 141 among the plurality of semiconductor dies 140 may be located above the dummy via forming region 510, and forming a molding material layer 127 on the interposer 200 to encapsulate the plurality of semiconductor dies 140. In one embodiment, forming the molding material layer 127 may include forming the molding material layer 127 to form a molded portion 127 at an interface I 141 The edge of the semiconductor grain 141 is contacted at the interface I 141 may be located above the dummy via formation region 510 . In one embodiment, attaching the plurality of semiconductor dies 140 may include attaching the plurality of semiconductor dies 140 such that an edge of the semiconductor die 141 may be located above a center of the dummy via formation region 510 .

[0222] Refer again Figures 1A to 10 , a packaging structure 100 may include a packaging substrate 110 and a packaging module 120 located on the packaging substrate 110. The packaging module 120 may include an interposer 200, which includes a dummy via forming region 510 having at least one dummy via 500, a plurality of semiconductor dies 140 located on the interposer layer 200, wherein an edge of a semiconductor dies 141 among the plurality of semiconductor dies 140 may be located above the dummy via forming region 510, and a molding material layer 127 located on the interposer 200 and encapsulating the plurality of semiconductor dies 140. The packaging structure 100 further includes a reinforcement ring 650 located on the packaging substrate 110 and surrounding the packaging module 120. In one embodiment, a distance D between the dummy via forming region 510 and an outer side wall of the interposer 200 is E The distance D between the outer sidewall of the interposer 200 and the inner edge 650a of the reinforcement ring 650 may be greater than the distance D between the outer sidewall of the interposer 200 and the inner edge 650a of the reinforcement ring 650. i .

[0223] In various embodiments disclosed herein, the interposer 200 may include a dummy via 500 formed in a dummy via forming region 510. The dummy via 500 may be formed in various cross-sectional shapes and sizes. The dummy via 500 may enhance the structure of a package module in which the dummy via 500 is formed as a part of the interposer 200 and mitigate the risk of interposer cracking. Various embodiments disclosed herein may reduce interposer cracking by more than 95% during a probing test.

[0224] The features of many embodiments are summarized above so that those with ordinary knowledge in the technical field to which the present disclosure belongs can better understand the various embodiments of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that other processes and structures can be easily designed or changed based on the embodiments of the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that these equivalent structures do not deviate from the spirit and scope of the present disclosure. Various changes, substitutions and modifications may be made to the embodiments of the present disclosure without departing from the spirit and scope of the appended claims.

Claims

1. A packaging module, characterized in that: include: An interposer layer includes a dummy via forming region, wherein the dummy via forming region has at least one dummy via; A plurality of semiconductor grains are located on the interposer, wherein an edge of a semiconductor grain among the plurality of semiconductor grains is located above the dummy via formation region; and A molding material layer is located on the interposer and encapsulates the plurality of semiconductor dies.

2. The packaging module according to claim 1, characterized in that The molding material layer contacts the edge of the semiconductor grain at an interface, and the interface is located above the dummy through hole forming area.

3. The packaging module according to claim 1, characterized in that The edge of the semiconductor crystal grain is located on a center of the dummy through hole forming region or on a center of the at least one dummy through hole, and the dummy through hole forming region is located below a periphery of the semiconductor crystal grain.

4. The packaging module according to claim 1, characterized in that The interposer includes a semiconductor material layer, and the at least one dummy through hole is located at: an uppermost portion of the layer of semiconductor material; or A lowermost portion of the semiconductor material layer.

5. The packaging module according to claim 1, characterized in that: A thickness of the at least one dummy via is substantially equal to a total thickness of the interposer.

6. The packaging module according to claim 1, characterized in that The at least one dummy through hole includes a plurality of dummy through holes, and the plurality of dummy through holes have a dummy through hole pattern.

7. The packaging module according to claim 6, characterized in that The plurality of dummy vias include a plurality of columns of dummy vias substantially aligned in a direction perpendicular to the edge of the semiconductor die.

8. The packaging module according to claim 6, characterized in that: The plurality of dummy vias includes a row of dummy vias substantially aligned with the edge of the semiconductor die.

9. The packaging module according to claim 1, characterized in that: The at least one dummy through hole includes a plurality of dummy through holes, and an area ratio of a total area of ​​the plurality of dummy through holes to an area of ​​the dummy through hole forming region is in a range of 0.1 to 0.

99.

10. A packaging structure, characterized in that: include: a packaging substrate; A packaging module is located on the packaging substrate, and the packaging module includes: An interposer layer includes a dummy via forming region, wherein the dummy via forming region has at least one dummy via; A plurality of semiconductor grains are located on the interposer, wherein an edge of a semiconductor grain among the plurality of semiconductor grains is located above the dummy via formation region; and a molding material layer disposed on the interposer and encapsulating the plurality of semiconductor dies; and A reinforcement ring is located on the packaging substrate and surrounds the packaging module.

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