Test circuitry for integrated circuits

Abstract

The utility model relates to a test circuit system for an integrated circuit. The test circuitry includes a scan compressor that receives n scan input bits from n input pins and compresses those bits to distribute between z scan chains, where z is less than n. The scan decompressor receives the test response data from the scan link and decompresses the test response data, thereby reconstructing n scan output bits. The OCC generates a test clock based on clock bits received from the clock chain, the test clock operating the scan chain and the clock chain. The clock chain receives m clock chain input bits from m of the input pins, m being less than n, and provides the clock bits to the OCC to generate a test clock. The test circuitry performs a test on the IC. Each test is associated with a test clock generated by the OCC based on a given set of clock bits. A test associated with a test clock generated by the OCC based on the same given set of clock bits is performed after a single loading of the same given set of clock bits.

Description

Technical Field

[0001] The present disclosure is directed to the field of scan compression in integrated circuit testing, and in particular to a modified architecture and loading technique for clock chain data that reduces or eliminates the use of dedicated input pins for clock chain data, thereby allowing these input pins to be recycled to increase the number of inputs to the scan data compressor. Background Art

[0002] In the field of integrated circuit (IC) chip production, testing is performed to help identify potential manufacturing defects or functional problems that may affect the performance and reliability of the IC chip. Two common testing techniques used for this purpose are automatic test pattern generation (ATPG) and logic built-in self-test (LBIST).

[0003] Reference now Figure 1 A test circuit system 10 within an IC chip is described. During testing, the core logic of the chip is temporarily reconfigured to incorporate a scan chain 22, which is used to facilitate efficient testing of the chip. This reconfiguration effectively converts the sequential and combinational logic of the core logic into a shift register-like structure. In this reconfigured state, the flip-flops within the scan chain 22 are interconnected with the combinational logic elements within the core logic. This allows the chip to be efficiently tested by facilitating the conversion of test modes and capturing response patterns for ATPG and LBIST techniques.

[0004] The test clock TSTCLK is used to synchronize the operation of the scan chain 22 with the core logic of the chip during testing. This test clock TSTCLK is generated by the on-chip clock controller (OCC) 11 based on the automatic test equipment clock (ATECLK) and the phase-locked loop clock (PLLCLK). The logic components of the OCC 11 are configured to generate different patterns as test clocks TSTCLK for test purposes based on the clock bits CKBITS received from the clock chain 13. During the entire test process, these clock bits CKBITS are changed in response to the m clock chain input bits OCC[1], ..., OCC[m] received from the m pins to generate the appropriate test clock signal TSTCLK pattern for each test stage. This dynamic reconfiguration allows the OCC 11 to generate the desired test clock signal TSTCLK pattern, which is then used to control the operation of the scan chain 22 and the core logic of the chip.

[0005] It is observed that there are z scan chains 22 clocked by the test clock TSTCLK, receiving input from the scan decompressor 21 and providing output to the scan compressor 23. The scan decompressor 21 obtains n scan input bits SCAN_IN[1], ..., SCAN_IN[n] from n pins, decompresses the test data, and distributes the decompressed data among the z scan chains 22, where z is greater than n. This makes the test data loading and unloading process more efficient. The scan compressor 23 receives test response data from the output of the z scan chains 22, compresses the data, and reconstructs n scan output bits SCAN_OUT[1], ..., SCAN_OUT[n], thereby allowing analysis of the test results of the chip.

[0006] The efficiency of the test process in an IC chip is affected by the number of input pins available to the scan decompressor 21. More input pins allow the scan decompressor 21 to handle a larger amount of test data, thereby enabling more scan chains to be loaded in parallel during a given cycle, which in turn speeds up the test process. However, increasing the number of pins on an IC chip can be a challenging and costly endeavor because it involves expanding the footprint of the chip or changing the layout of the chip.

[0007] In view of these challenges, it would be advantageous if existing pins already used for other purposes could be used to provide additional scan input bits to the scan decompressor 21. By reusing or sharing these existing pins, the efficiency of the test process can be improved without modifying the design of the IC chip. Therefore, further development is needed in this area. Utility Model Content

[0008] The purpose of the utility model is to provide an improved test circuit system for integrated circuits.

[0009] A test circuit system for an integrated circuit is disclosed herein. The test circuit system includes a scan decompressor that receives n scan input bits from n input pins and decompresses the n scan input bits so as to be distributed as test data between z scan chains, where z is greater than n. The test circuit system also includes a scan compressor that receives test response data from z scan chains and compresses the test response data to reconstruct n scan output bits. An on-chip clock controller (OCC) generates a test clock signal based on the clock bit received from the clock link, and the test clock signal operates the z scan chains and the clock chain. The clock chain is configured to receive m clock chain input bits from m input pins of the n input pins, where m is less than n, and provide the clock bit to the OCC to generate a test clock signal. The control circuit system controls the test circuit system to perform multiple tests on the integrated circuit, each test being associated with a test clock signal that has been generated by the OCC based on a given set of clock bits. Multiple tests associated with a test clock signal that has been generated by the OCC based on the same given set of clock bits are performed after a single load of the same given set of clock bits.

[0010] Preferably, the test circuit further comprises a clock control logic configured to pass the test clock signal to the clock chain in response to assertion of the load enable signal, and pass the test clock signal to the z scan chains in response to de-assertion of the load enable signal.

[0011] Preferably, the test circuit further comprises a first enable buffer configured to pass the test clock signal to the clock chain in response to assertion of the load enable signal; and a second enable buffer configured to pass the test clock signal to the z scan chains in response to deassertion of the load enable signal.

[0012] Preferably, the load enable signal is received via a load enable pin.

[0013] Preferably, the test circuit further comprises a mode counter coupled to the n input pins and configured to count a number of tests performed on the integrated circuit and assert the load enable signal based on the count.

[0014] Preferably, the pattern counter is further configured to count a total number of clock chain input bits received by the clock chain during execution of the plurality of tests, and to de-assert the load enable signal when the total number of clock chain input bits becomes equal to a predetermined value.

[0015] A test circuit system for an integrated circuit is also disclosed herein. This test circuit system includes an on-chip clock controller (OCC), which is configured to generate a test clock signal based on a clock bit received from a clock link, wherein the test clock signal operates a clock chain. The clock chain is configured to receive m clock chain input bits from m input pins of n input pins, where m is less than n, and provide the clock bits to the OCC to generate a test clock signal. The control circuit system controls the test circuit system to perform multiple tests on the integrated circuit, wherein each test is associated with a test clock signal generated by the OCC based on a given set of clock bits. Multiple tests associated with the test clock signal generated by the OCC based on the same given set of clock bits are performed after a single load of the same given set of clock bits.

[0016] Preferably, the test circuit further comprises clock control logic configured to pass a test clock signal to the clock chain in response to assertion of the load enable signal.

[0017] Preferably, the test circuit further comprises a first enable buffer configured to pass the test clock signal to the clock chain in response to assertion of the load enable signal.

[0018] Preferably, the load enable signal is received via a load enable pin.

[0019] Preferably, the test circuit further comprises a mode counter coupled to the n input pins and configured to count a number of tests performed on the integrated circuit and assert the load enable signal based on the count.

[0020] Preferably, the pattern counter is further configured to count a total number of clock chain input bits received by the clock chain during execution of the plurality of tests, and to de-assert the load enable signal when the total number of clock chain input bits becomes equal to a predetermined value. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a block diagram of conventional test circuitry implemented in an integrated circuit.

[0022] Figure 2 is a block diagram of the improved test circuitry described herein implemented in an integrated circuit.

[0023] Figure 3 is a diagram of a set of prior art test clock patterns.

[0024] Figure 4 is an illustration of a set of test clock patterns for a grouping as described herein.

[0025] Figure 5is a block diagram of an alternative embodiment of the test circuitry described herein implemented in an integrated circuit with the load enable pin removed. DETAILED DESCRIPTION

[0026] The following disclosure enables those skilled in the art to make and use the subject matter described herein. Without departing from the spirit and scope of the present disclosure, the general principles outlined in the present disclosure may be applied to embodiments and applications other than those described in detail above. It is not intended to limit the present disclosure to the embodiments shown, but rather to give it the widest scope consistent with the principles and features disclosed or suggested herein.

[0027] Now consider Figure 2 A test circuit system 10' is provided, which is controlled by a control circuit 35 to perform test operations. The test circuit system 10' includes z scan chains 22 clocked by a test clock TSTCLK, the z scan chains 22 receiving inputs from a scan decompressor 21 and providing outputs to a scan compressor 23. The scan decompressor 21 obtains n scan input bits SCAN_IN[1], ..., SCAN_IN[n] from n input pins IN[1], ..., IN[n], decompresses test data, and distributes the compressed data among the z scan chains 22, where z is greater than n. This makes the test data loading and unloading process more efficient. The scan compressor 23 receives test response data from the outputs of the z scan chains 22, compresses the data, and reconstructs n scan output bits SCAN_OUT[1], ..., SCAN_OUT[n], thereby allowing the test results of the chip to be analyzed.

[0028] The test clock TSTCLK is generated by an on-chip clock controller (OCC) 11 based on the automatic test equipment clock (ATECLK) and the phase-locked loop clock (PLLCLK). The logic components of the OCC 11 are configured to generate different patterns as the test clock TSTCLK for test purposes based on the clock bits CKBITS received from the clock chain 13 composed of a series of flip-flops. During the entire test process, these clock bits CKBITS are changed in response to the m clock chain input bits OCC[1], ..., OCC[m] received from the m IN[1], ..., IN[m] of the n input pins IN[1], ..., IN[n] to generate the appropriate test clock signal TSTCLK mode for each test stage. It should be self-evident that m is less than n.

[0029] It is observed here that, contrary to the prior art, m of the n pins are not dedicated to the scan decompressor 21 and the m scan input terminals SCAN_IN[1], ..., SCAN_IN[m] or the clock chain 13 and the m clock chain input bits OCC[1], ..., OCC[m]. Instead, m of the n input pins IN[1], ..., IN[n] are shared by the scan decompressor 21 and the clock chain 13.

[0030] It is also worth noting here that, contrary to the prior art, the enable logic 31 passes the test clock TSTCLK to the clock input of the clock chain 13 in response to the assertion of the load enable signal LOAD_EN at the corresponding pin, while the enable logic 32 passes the test clock TSTCLK to the clock input of the scan chain 22 in response to the deassertion of the load enable signal LOAD_EN.

[0031] The setting of these clock bits CKBITS will now be described. Recall that in the context of ATPG and LBIST test techniques, different sets of clock bits CKBITS are used to generate various test clock TSTCLK patterns for different test phases. These test clock TSTCLK patterns are used to control the operation of the scan chain 22 and the core logic of the IC chip during testing. Conventionally, the clock bits CKBITS are reloaded at each step of the test by changing the clock chain input bits OCC[1], ..., OCC[m] received from m input pins IN[1], ..., IN[m] to generate the desired test clock signal TSTCLK pattern for the current test phase.

[0032] However, this constant reloading of the clock bits CKBITS for each test phase results in increased test time and complexity. Figure 2 The disclosed test circuit system 10' shown in FIG. 1 employs an optimization technique that involves rearranging and grouping together patterns having the same clock chain input bit values. By doing so, the test patterns can be reordered in a manner that involves less frequent reloading of the clock bits CKBITS because the same clock bit values ​​are used across multiple consecutive test phases. This optimization reduces the time spent reloading clock-data required to switch between different clock modes during testing.

[0033] Note that to achieve this optimization, the tests themselves will also be reordered to correspond with the reordered clock bits CKBITS. This helps ensure that the test process still meets the expected functional and performance requirements of the chip while taking advantage of the reduced clock bit reload. The reordered tests will still follow the specific ATPG and LBIST technology being used and its requirements in order to meet the test goals and obtain accurate results.

[0034] Now consider Figure 3 , ten test clock TSTCLK patterns are shown, which are generated in sequence, labeled as patterns 1 to 10. These patterns correspond to the ten test steps to be performed. Observe that for each test clock TSTCLK pattern, the appropriate configuration of the clock bits CKBITS must be loaded by applying the corresponding clock chain input bits OCC[1], ..., OCC[m].

[0035] Each different configuration (e.g., value) of the clock chain input bits OCC[1], ..., OCC[m] is referred to as a different value of OCC_config. It can be observed that, although ten test clock TSTCLK patterns are to be generated, only three different configurations of the clock chain input bits are to be loaded, represented here as OCC_config1, OCC_config2, and OCC_config3. Specifically: Mode 1, Mode 6, and Mode 7 are generated by providing the clock chain input bits OCC[1], ..., OCC[m] corresponding to the configuration OCC_config1 to the clock chain 13; Mode 2, Mode 5, Mode 9, and Mode 10 are generated by providing the clock chain input bits OCC[1], ..., OCC[m] corresponding to the configuration OCC_config2 to the clock chain 13; and Mode 3, Mode 4, and Mode 8 are generated by providing the clock chain input bits OCC[1], ..., OCC[m] corresponding to the configuration OCC_config3 to the clock chain 13.

[0036] In order to optimize the test process, the order of the tests can be rearranged so that the tests using the test clock TSTCLK mode generated by the same value of OCC_config are grouped. Therefore, it is only necessary to load different sets of clock bits CKBITS from the appropriate clock chain input bits OCC[1], ..., OCC[m] before executing each group of tests.

[0037] For example, Figure 4 As shown in , test clock TSTCLK modes 1, 6, and 7 generated by OCC_config1 can be grouped into a first group, test clock TSTCLK modes 2, 5, 9, and 10 generated by OCC_config2 can be grouped into a second group, and test clock TSTCLK modes 3, 4, and 8 generated by OCC_config3 can be grouped into a third group. Therefore, instead of requiring ten separate loads of the clock bit CKBITS to perform ten tests using ten test clock TSTCLK modes, ten tests can be performed using only three loads of the clock bit CKBITS. This optimization reduces test time and complexity while maintaining the necessary test requirements.

[0038] Since the tests are reordered and grouped based on their corresponding OCC_config values, the operation of the load enable signal LOAD_EN becomes more efficient in the grouped test method. Remember that when LOAD_EN is asserted, the enable buffer 31 is responsible for passing the test clock TSTCLK to the clock input of the clock chain 13, and when LOAD_EN is deasserted, the enable buffer 32 passes the test clock TSTCLK to the clock input of the scan chain 22.

[0039] To begin executing a series of tests, LOAD_EN is asserted, which allows the enable buffer 31 to pass the test clock TSTCLK to the clock input of the clock chain 13, thereby loading the appropriate clock bits CKBITS corresponding to the first OCC_config value from the corresponding clock chain input bits OCC[1], ..., OCC[m]. Next, LOAD_EN is deasserted, allowing the enable buffer 32 to pass the test clock TSTCLK to the clock input of the scan chain 22. During this stage, the first group of tests using the same OCC_config value is executed, while the OCC data remains the same (frozen), thereby eliminating the need to reload the clock bits between tests within the same group.

[0040] When it is time to load the next OCC_config value, LOAD_EN is asserted again, allowing the enable buffer 31 to pass the test clock TSTCLK to the clock input of the clock chain 13 to load the new OCC_config value from the corresponding clock chain input bits OCC[1], ..., OCC[m]. At the same time, the scan chains 22 retain their data (frozen). Once the new OCC_config value is loaded, LOAD_EN is de-asserted, and the enable buffer 32 passes the test clock TSTCLK to the clock input of the scan chain 22, enabling the execution of the second set of tests corresponding to the newly loaded OCC_config value.

[0041] Repeating this process for all sets of OCC patterns significantly reduces the frequency of toggling the LOAD_EN signal and minimizes the need to change the clock chain input bits OCC[1], ..., OCC[m] during testing. This therefore results in a more efficient testing process and reduces test time.

[0042] Reference now Figure 5 , describes another embodiment in which the pin for the load enable signal LOAD_EN is eliminated. In this embodiment, the dedicated LOAD_EN pin is removed and a mode counter 33 is introduced.

[0043] The pattern counter 33 is a digital circuit coupled to the n input pins IN[1], ..., IN[n]. It keeps track of the number of test patterns executed during the test process and generates a load enable signal LOAD_EN based on its count.

[0044] In more detail, the pattern counter 33 determines when to change the OCC_config value for the next set of tests. It receives signals from the n input pins IN[1], ..., IN[n] during the capture phase. Each time a test pattern is executed, the pattern counter 33 increments its count, thereby monitoring the current position in the test sequence.

[0045] When the mode counter 33 reaches a predetermined value, it triggers a change in the OCC_config value, thereby initiating the process of loading new OCC data for the next set of tests. This approach eliminates the need for a dedicated LOAD_EN pin. During the test process, the LOAD_EN signal generated by the mode counter 33 is asserted or de-asserted based on the current position in the test sequence. When the mode counter value indicates that a new OCC_config value needs to be loaded, the LOAD_EN signal is asserted, allowing the enable buffer 31 to pass the test clock TSTCLK to the clock input of the clock chain 13.

[0046] Conversely, when the appropriate OCC_config value is loaded and the test corresponding to that value is to be performed, the LOAD_EN signal is deasserted, thereby enabling the enable buffer 32 to pass the test clock TSTCLK to the clock input of the scan chain 22. This can be performed by a pattern counter 33, which includes an end-counter circuit system that counts the number of bits of the OCC data that have been loaded. Once this count reaches a pre-specified stop value (equal to the known total number of bits of the OCC data), the LOAD_EN signal is deasserted.

[0047] In summary, the test circuit system described herein provides multiple advantages over conventional test circuit systems in integrated circuits. By sharing m input pins between the scan compressor and the clock chain, the test circuit system reduces the number of dedicated input pins required, thereby saving valuable resources. In addition, by reordering and grouping test patterns based on their corresponding OCC_config values, frequent changes of clock bits during the test process are minimized, thereby achieving a more efficient test process and reducing test time.

[0048] Furthermore, in an alternative embodiment where the load enable pin is eliminated, a pattern counter is introduced to generate a LOAD_EN signal based on its count. This approach not only eliminates the need for a dedicated LOAD_EN pin, but also makes the testing process more efficient by tracking the current position in the test sequence and automatically triggering a change in the OCC_config value when appropriate.

[0049] Overall, the disclosed test circuitry optimization techniques enable efficient testing of integrated circuits to meet the functional and performance requirements of the chip while reducing test time, complexity, and resource usage.

[0050] One embodiment of the utility model provides a test circuit system for an integrated circuit, comprising a scan decompressor, configured to receive n scan input bits from n input pins and decompress the n scan input bits so as to distribute them as test data among z scan chains, wherein z is greater than n; a scan compressor, configured to receive test response data from the z scan chains and compress the test response data to reconstruct n scan output bits; an on-chip clock controller OCC, configured to generate a test clock signal based on the clock bits received from the clock link, the test clock signal being configured to operate the z scan chains and the clock chain; wherein the clock chain is configured to receive m clock chain input bits from m input pins out of the n input pins, wherein m is less than n, and the clock bits are provided to the OCC to generate the test clock signal; a control circuit system, configured to control the test circuit system to perform multiple tests on the integrated circuit, each test being associated with a test clock signal that has been generated by the OCC based on a given set of clock bits; and wherein after a single loading of the same given set of clock bits, a test among the multiple tests associated with the test clock signal that has been generated by the OCC based on the same given set of clock bits is performed.

[0051] Preferably, the test circuit further comprises a clock control logic configured to pass the test clock signal to the clock chain in response to assertion of the load enable signal, and pass the test clock signal to the z scan chains in response to de-assertion of the load enable signal.

[0052] Preferably, the test circuit further comprises a first enable buffer configured to pass the test clock signal to the clock chain in response to assertion of the load enable signal; and a second enable buffer configured to pass the test clock signal to the z scan chains in response to deassertion of the load enable signal.

[0053] Preferably, the load enable signal is received via a load enable pin.

[0054] Preferably, the test circuit further comprises a mode counter coupled to the n input pins and configured to count a number of tests performed on the integrated circuit and assert the load enable signal based on the count.

[0055] Preferably, the pattern counter is further configured to count a total number of clock chain input bits received by the clock chain during execution of the plurality of tests, and to de-assert the load enable signal when the total number of clock chain input bits becomes equal to a predetermined value.

[0056] One embodiment of the utility model provides a method for optimizing a test circuit system in an integrated circuit, comprising grouping tests performed by the test circuit system on the integrated circuit into multiple groups, and performing the grouping according to the following: for each test which clock mode will be applied as a test clock to a scan chain in the integrated circuit so that each test using the same clock mode is in the same group; performing each group of tests by: loading a set of clock bits into a clock controller, which clock bits configure the clock controller to generate a test clock having a clock mode utilized by the group of tests; and performing each test in the group of tests using the test clock without reconfiguring the clock controller using different sets of clock bits between different tests in the group of tests.

[0057] Preferably, there are z scan chains; the method further comprises receiving n scan input bits to be loaded into the scan chains at n input pins; and compressing the n scan input bits to generate input data for the z scan chains, wherein z is greater than n; and wherein each set of clock bits is received at m input pins of the n input pins, wherein m is less than n.

[0058] Preferably, the method also includes deasserting a load enable signal before loading a set of clock bits associated with a set of tests to be performed into a clock controller to allow a test clock to be passed to a clock chain that provides the set of clock bits to the clock controller; and asserting a load enable signal to a scan chain after loading a set of clock bits associated with a set of tests to be performed into the clock controller.

[0059] Preferably, the method further comprises counting the number of sets of clock bits that have been loaded in the clock controller, and wherein the load enable signal is asserted or de-asserted based on the count.

[0060] Preferably, the load enable signal is received via a load enable pin.

[0061] Preferably, the method further comprises counting a number of tests executed on the integrated circuit and asserting a load enable signal based on the count.

[0062] Preferably, the method further comprises counting a total number of clock bits received during execution of the test and de-asserting the load enable signal when the total number of those clock bits becomes equal to a predetermined value.

[0063] One embodiment of the utility model provides a test circuit system for an integrated circuit, comprising an on-chip clock controller OCC, configured to generate a test clock signal based on clock bits received from a clock link, the test clock signal being configured to operate a clock chain; wherein the clock chain is configured to receive m clock chain input bits from m input pins out of n input pins, wherein m is less than n, and provide the clock bits to the OCC to generate the test clock signal; a control circuit system, configured to control the test circuit system to perform multiple tests on the integrated circuit, wherein each test is associated with a test clock signal that has been generated by the OCC based on a given set of clock bits; and wherein after a single loading of the same given set of clock bits, a test among the multiple tests associated with the test clock signal that has been generated by the OCC based on the same given set of clock bits is performed.

[0064] Preferably, the test circuit further comprises clock control logic configured to pass a test clock signal to the clock chain in response to assertion of the load enable signal.

[0065] Preferably, the test circuit further comprises a first enable buffer configured to pass the test clock signal to the clock chain in response to assertion of the load enable signal.

[0066] Preferably, the load enable signal is received via a load enable pin.

[0067] Preferably, the test circuit further comprises a mode counter coupled to the n input pins and configured to count a number of tests performed on the integrated circuit and assert the load enable signal based on the count.

[0068] Preferably, the pattern counter is further configured to count a total number of clock chain input bits received by the clock chain during execution of the plurality of tests, and to de-assert the load enable signal when the total number of clock chain input bits becomes equal to a predetermined value.

[0069] Obviously, modifications and variations may be made to what has been described and illustrated herein without departing from the scope of the present disclosure.

[0070] Although the present disclosure has been described using a limited number of embodiments, those skilled in the art having benefit of this disclosure may devise other embodiments that do not depart from the scope of the disclosure. In addition, those skilled in the art may devise embodiments that represent various combinations of the embodiments disclosed herein performed in various ways.

Claims

1. A test circuit system for an integrated circuit, characterized in that: The test circuit system comprises: a scan decompressor configured to receive n scan-in bits from n input pins and decompress the n scan-in bits for distribution as test data among z scan chains, where z is greater than n; a scan compressor configured to receive test response data from the z scan chains and compress the test response data to reconstruct n scan output bits; an on-chip clock controller OCC configured to generate a test clock signal based on a clock bit received from the clock link, the test clock signal being configured to operate the z scan chains and the clock chain; wherein the clock chain is configured to receive m clock chain input bits from m input pins out of the n input pins, where m is less than n, and provide the clock bits to the OCC to generate a test clock signal; control circuitry configured to control the test circuitry to perform a plurality of tests on the integrated circuit, each test being associated with a test clock signal that has been generated by the OCC based on a given set of clock bits; and Wherein tests in the plurality of tests associated with a test clock signal that has been generated by the OCC based on the same given set of clock bits are performed after a single loading of the same given set of clock bits.

2. The test circuit system according to claim 1, characterized in that: The test circuitry also includes clock control logic configured to pass a test clock signal to the clock chain in response to assertion of the load enable signal and to pass the test clock signal to the z scan chains in response to de-assertion of the load enable signal.

3. The test circuit system according to claim 1, wherein: The test circuit system also includes: a first enable buffer configured to pass the test clock signal to the clock chain in response to assertion of the load enable signal; and A second enable buffer is configured to pass the test clock signal to the z scan chains in response to de-assertion of the load enable signal.

4. The test circuit system according to claim 3, characterized in that: The load enable signal is received via the load enable pin.

5. The test circuit system according to claim 3, characterized in that: The test circuitry also includes a pattern counter coupled to the n input pins and configured to count a number of tests performed on the integrated circuit and assert a load enable signal based on a value of the count.

6. The test circuit system according to claim 5, characterized in that: The pattern counter is further configured to count a total number of clock chain input bits received by the clock chain during execution of the plurality of tests and to de-assert the load enable signal when the total number of clock chain input bits becomes equal to a predetermined value.

7. A test circuit system for an integrated circuit, characterized in that: include: an on-chip clock controller OCC configured to generate a test clock signal based on a clock bit received from the clock link, the test clock signal being configured to operate the clock chain; wherein the clock chain is configured to receive m clock chain input bits from m input pins out of the n input pins, where m is less than n, and to provide the clock bits to the OCC to generate a test clock signal; control circuitry configured to control the test circuitry to perform a plurality of tests on the integrated circuit, wherein each test is associated with a test clock signal that has been generated by the OCC based on a given set of clock bits; as well as Wherein tests in the plurality of tests associated with a test clock signal that has been generated by the OCC based on the same given set of clock bits are performed after a single loading of the same given set of clock bits.

8. The test circuit system according to claim 7, characterized in that: Also included is clock control logic configured to pass a test clock signal to the clock chain in response to assertion of the load enable signal.

9. The test circuit system according to claim 7, characterized in that: Also included is a first enable buffer configured to pass the test clock signal to the clock chain in response to assertion of the load enable signal.

10. The test circuit system according to claim 9, characterized in that: The load enable signal is received via the load enable pin.

11. The test circuit system according to claim 9, characterized in that: Also included is a mode counter coupled to the n input pins and configured to count a number of tests performed on the integrated circuit and assert a load enable signal based on a value of the count.

12. The test circuit system according to claim 11, characterized in that: Wherein the pattern counter is further configured to count a total number of clock chain input bits received by the clock chain during execution of the plurality of tests, and to de-assert the load enable signal when the total number of clock chain input bits becomes equal to a predetermined value.

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