CAN bus address automatic distribution device
By introducing a fault detection unit into the CAN bus address automatic allocation device, fault signals can be detected and feedback in a timely manner, solving the problem of untimely fault detection in the prior art, and improving the operating efficiency and convenience of use of the system.
Patent Information
- Application Number
- CN202422033478.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-21
- Publication Date
- 2025-05-27
- Estimated Expiration
- 2034-08-21
AI Technical Summary
The existing CAN bus address automatic allocation device cannot detect it in time when a slave end or transmission line fails, resulting in a lot of time for inspection and maintenance of staff, which increases the difficulty of use.
An automatic CAN bus address allocation device including an MCU, an encoder and a fault detection unit is designed. The fault detection unit includes an input and output PWM signal detection module and a heartbeat packet detection module, which can detect faults on the software and hardware of the detection object and feed back to the MCU in a timely manner.
Through the detection and feedback of the fault detection unit, the fault signal can be recorded in a timely manner and the detection object can be stopped, reducing the difficulty of staff investigation and maintenance and improving the operation efficiency of the CAN bus address automatic allocation device.
Smart Images

Figure CN222916069U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of power electronics, and particularly relates to a CAN bus address automatic allocation device. Background Technique
[0002] CAN bus address automatic allocation is a process of enabling nodes (or stations) in a CAN bus system to automatically obtain unique identifiers (i.e., addresses). This process is crucial for ensuring correct and efficient communication among nodes in the CAN bus network.
[0003] Currently, a Chinese patent discloses a CAN bus address automatic allocation device (authorized publication number: CN216361921U). By setting up a power-on delay circuit, an oscillation circuit, and a temperature acquisition circuit, the time difference of the first power supply, the second power supply, and the third power supply in the power-on delay circuit is used to compete for the first address of the CAN bus address. The discreteness of the oscillation frequency generated by the oscillation circuit and the discreteness of the ambient temperature value collected by the temperature acquisition circuit are used to compete for the remaining CAN bus addresses; that is, the remaining CAN bus addresses are competed for in ascending order according to the sequence of the generation time of each oscillation frequency. If the competition is not completed after exceeding the preset duration threshold, the remaining CAN bus addresses are competed for in ascending order according to the sequence of the generation time of each temperature value until all CAN bus addresses are allocated.
[0004] Since the above device allocates CAN bus addresses through the detection of the upper delay circuit, the oscillation circuit, and the temperature acquisition circuit, this is based on the normal operation of both the slave end and the transmission line. Otherwise, when a failure occurs in the slave end or the transmission line, the above device cannot detect it in time, which will cause staff to spend a lot of time for troubleshooting and maintenance, increasing the difficulty of using the CAN bus address automatic allocation device.
[0005] Therefore, a CAN bus address automatic allocation device is proposed to solve the above problems. Content of the Utility Model
[0006] The utility model realizes the above object through the following technical solutions. A CAN bus address automatic allocation device includes: an MCU; an encoder, the input end of the encoder is electrically connected to the output end of the MCU; a fault detection unit, the fault detection unit includes an input / output PWM signal detection module and a heartbeat packet detection module, the MCU and the encoder are both bidirectionally electrically connected to the input / output PWM signal detection module, and the MCU and the encoder are both bidirectionally electrically connected to the heartbeat packet detection module.
[0007] Preferably, the input / output PWM signal detection module includes a PWM output module, a PWM input module, and a fault detection module. The input end of the PWM output module is electrically connected to the output end of the encoder. The output ends of the PWM output module and the PWM input module are both electrically connected to the input end of the fault detection module. The output end of the fault detection module is electrically connected to the input end of the MCU.
[0008] Preferably, the heartbeat packet detection module includes an instruction output module and a judgment module. The input end of the instruction output module is electrically connected to the output end of the encoder. The input end of the judgment module is electrically connected to the output end of the instruction output module. The output end of the judgment module is electrically connected to the input end of the MCU.
[0009] Preferably, the heartbeat packet detection module further includes a timing module. The input end of the timing module is electrically connected to the input end of the instruction output module.
[0010] Preferably, the MCU is a material component of HyperChips Semiconductor HPM6800.
[0011] The beneficial effects of the present utility model are as follows:
[0012] Before the CAN bus address automatic allocation device performs automatic allocation operations, the fault detection unit can effectively detect faults in both the software and hardware of the detection object, and promptly feedback to the MCU when a fault is detected, enabling it to record the fault signal in a timely manner and stop the operation of the detection object, allowing the staff to promptly troubleshoot and repair the fault location. This can not only ensure the effective operation efficiency of the CAN bus address automatic allocation device but also save the difficulty for the staff to troubleshoot and maintain faults, thereby reducing the usage difficulty of the CAN bus address automatic allocation device. Description of the Drawings
[0013] Figure 1 is the operation flowchart of the CAN bus address automatic allocation device in the present utility model;
[0014] Figure 2 is the operation flowchart of the fault detection unit in the present utility model;
[0015] Figure 3 is the system flowchart of the input / output PWM signal detection module in the present utility model;
[0016] Figure 4 is the system flowchart of the heartbeat packet detection module in the present utility model.
[0017] In the figure: 1. MCU; 2. Encoder; 3. Input / Output PWM Signal Detection Module; 31. PWM Output Module; 32. PWM Input Module; 33. Fault Detection Module; 4. Heartbeat Packet Detection Module; 41. Instruction Output Module; 42. Judgment Module; 43. Timing Module. Detailed Implementation Manner
[0018] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts shall fall within the protection scope of the present utility model.
[0019] During specific implementation: As Figures 1-4 shown, a CAN bus address automatic allocation device includes: MCU1; an encoder 2, the input end of the encoder 2 is electrically connected to the output end of MCU1; a fault detection unit, the fault detection unit includes an input / output PWM signal detection module 3 and a heartbeat packet detection module 4, both MCU1 and the encoder 2 are bidirectionally electrically connected to the input / output PWM signal detection module 3, and both MCU1 and the encoder 2 are bidirectionally electrically connected to the heartbeat packet detection module 4.
[0020] MCU1 is a material component of the Xianji Semiconductor HPM6800. The Xianji Semiconductor HPM6800 is a high-performance product for the fields of industrial automation, new energy, and automotive electronics. They support double-precision floating-point operations and powerful DSP extensions, with a main frequency of up to several hundred MHz, and have characteristics such as high-precision motion control and high-real-time industrial Ethernet interconnection.
[0021] As Figure 3 shown, the input / output PWM signal detection module 3 includes a PWM output module 31, a PWM input module 32, and a fault detection module 33. The input end of the PWM output module 31 is electrically connected to the output end of the encoder 2. The output ends of both the PWM output module 31 and the PWM input module 32 are electrically connected to the input end of the fault detection module 33. The output end of the fault detection module 33 is electrically connected to the input end of MCU1.
[0022] As Figure 4 shown, the heartbeat packet detection module 4 includes an instruction output module 41 and a judgment module 42. The input end of the instruction output module 41 is electrically connected to the output end of the encoder 2. The input end of the judgment module 42 is electrically connected to the output end of the instruction output module 41. The output end of the judgment module 42 is electrically connected to the input end of MCU1; the heartbeat packet detection module 4 further includes a timing module 43, and the input end of the timing module 43 is electrically connected to the input end of the instruction output module 41.
[0023] When the utility model is in use,
[0024] Step 1: The MCU1 presets a duration threshold, and turns on the switch K1 and the switch K2 to supply power to the power-on delay circuit;
[0025] Step 2: The MCU1 detects whether its software and hardware are working properly based on the fault detection unit;
[0026] Step 3: The MCU1 automatically allocates the first address (0000H) of the CAN bus address based on the time when the first power supply, the second power supply, and the third power supply reach the effective working voltage of the system; that is, competes for the first address of the CAN bus address based on the time when the three power supplies reach the effective working voltage of the system;
[0027] Step 4: The MCU1 automatically allocates the remaining addresses of the CAN bus address based on the time generated by each oscillation frequency of the oscillation circuit, and judges whether all the CAN bus addresses have been allocated when the duration threshold arrives. If so, the process ends; if not, it enters Step 5;
[0028] Step 5: The MCU1 automatically allocates the remaining addresses of the CAN bus address based on the time of each temperature value collected by the temperature acquisition circuit;
[0029] Among them, the detailed steps of Step 2 are as follows:
[0030] 1. Software detection: The MCU1 transmits the corresponding electrical signal to the encoder 2. The encoder 2 translates the electrical signal into an instruction that can be read by the instruction output module 41, and then the encoder 2 transmits the instruction to the instruction output module 41. The instruction output module 41 simultaneously transmits the instruction to the detection object and the timing module 43. The timing module 43 starts counting down. Before the countdown of the timing module 43 ends, if the detection object sends a corresponding electrical signal to the judgment module 42 according to the instruction, it indicates that the detection object is running normally. If the detection object does not send a corresponding electrical signal to the judgment module 42 before the countdown of the timing module 43 ends, the judgment module 42 sends a corresponding fault signal to the MCU1, and the MCU1 records the fault signal and stops running the detection object;
[0031] II. Hardware Detection: The MCU1 transmits the corresponding electrical signal to the encoder 2. The encoder 2 translates the electrical signal into an instruction that the PWM output module 31 can read. Then, the PWM output module 31 sends the corresponding PWM instruction to the detection object. When the detection object successfully receives the PWM instruction, the detection object sends the corresponding electrical signal to the fault detection module 33. At this time, it indicates that the incoming path of the detection object is operating normally. If the detection object does not send the corresponding electrical signal to the fault detection module 33, it indicates that the incoming path of the detection object is operating abnormally. The fault detection module 33 sends the corresponding fault signal to the MCU1. The MCU1 records the fault signal and stops the operation of the detection object. After the detection of the normal incoming path of the detection object is completed, the detection object sends the corresponding PWM signal to the PWM input module 32 according to the PWM instruction. When the fault detection module 33 successfully receives the corresponding PWM signal, it indicates that the loop of the detection object is normal. If the PWM input module 32 does not send the corresponding electrical signal to the fault detection module 33, it indicates that the loop of the detection object is operating abnormally. The fault detection module 33 sends the corresponding fault signal to the MCU1. The MCU1 records the fault signal and stops the operation of the detection object.
[0032] It should be noted that the conduction switch K1, switch K2, upper delay circuit, oscillation circuit, and temperature acquisition circuit mentioned in the above device are all mature technologies disclosed in the comparative patent. Since the present application does not improve the above structure, their connection methods, operating principles, and usage methods are also the same as those disclosed in the comparative patent, and will not be elaborated here.
[0033] At the same time, the specific model specifications of the MCU1, encoder 2, PWM output module 31, PWM input module 32, fault detection module 33, instruction output module 41, judgment module 42, timing module 43, conduction switch K1, switch K2, upper delay circuit, oscillation circuit, and temperature acquisition circuit need to be selected according to the actual specifications of the device. The specific selection calculation method uses the existing technology in the field, so it will not be elaborated in detail. The power supply and its principle of the MCU1, encoder 2, PWM output module 31, PWM input module 32, fault detection module 33, instruction output module 41, judgment module 42, timing module 43, conduction switch K1, switch K2, upper delay circuit, oscillation circuit, and temperature acquisition circuit are clear to those skilled in the art and will not be described in detail here.
[0034] In addition, it should be understood that although this specification is described according to the embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A CAN bus address automatic allocation device, characterized in that: include: MCU(1); An encoder (2), wherein an input end of the encoder (2) is electrically connected to an output end of the MCU (1); A fault detection unit, the fault detection unit comprising an input / output PWM signal detection module (3) and a heartbeat packet detection module (4), the MCU (1) and the encoder (2) are both bidirectionally electrically connected to the input / output PWM signal detection module (3), and the MCU (1) and the encoder (2) are both bidirectionally electrically connected to the heartbeat packet detection module (4).
2. The CAN bus address automatic allocation device according to claim 1, characterized in that: The input-output PWM signal detection module (3) comprises a PWM output module (31), a PWM input module (32) and a fault detection module (33); the input end of the PWM output module (31) is electrically connected to the output end of the encoder (2); the output ends of the PWM output module (31) and the PWM input module (32) are both electrically connected to the input end of the fault detection module (33); and the output end of the fault detection module (33) is electrically connected to the input end of the MCU (1).
3. The CAN bus address automatic allocation device according to claim 1, characterized in that: The heartbeat packet detection module (4) comprises an instruction output module (41) and a judgment module (42), wherein the input end of the instruction output module (41) is electrically connected to the output end of the encoder (2), the input end of the judgment module (42) is electrically connected to the output end of the instruction output module (41), and the output end of the judgment module (42) is electrically connected to the input end of the MCU (1).
4. The CAN bus address automatic allocation device according to claim 3, characterized in that: The heartbeat packet detection module (4) further comprises a timing module (43), the input end of the timing module (43) being electrically connected to the input end of the instruction output module (41).
5. The CAN bus address automatic allocation device according to claim 3, characterized in that: The MCU (1) is made of HPM6800 material from Pioneer Semiconductor.
Citation Information
Patent Citations
CAN bus address automatic distribution device
CN216361921U