Display substrate, display screen and display device

Abstract

The utility model relates to a display substrate, a display screen and a display device, a plurality of sub-shielding lines are arranged between output pins on an outermost metal layer of a binding pin area of the display substrate or between the output pins and shielding pins, and a main shielding line is arranged on any other metal layer except the outermost metal layer in the binding pin area. The main shielding wire and the sub shielding wire are connected through the via hole, and then the main shielding wire and the shielding pin are connected through the via hole to form a signal shielding structure. According to the structure, partial shielding pins are replaced by the sub-shielding lines, the number of the shielding pins is reduced while the performance of the display substrate is not affected, the output pins can be increased under the condition that the width of the pin binding area is not changed so as to improve the resolution ratio of the display panel, the width of the pin binding area can be further reduced, and the yield of the display panel is improved. Therefore, the narrow frame requirements of different products are met.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to a display substrate, a display screen, and a display device. Background Art

[0002] The high resolution and full screen requirements of mobile device products have always been parameters that the market and customers pursue and need to be continuously optimized and improved. However, due to the limitations of module binding process equipment, the total pin spacing cannot be further reduced, or the cost of developing and replacing new binding equipment is too high, so the requirements of high resolution and narrow bezels of some displays cannot be met. Summary of the invention

[0003] The present application provides a display substrate that can meet the demand for high resolution while further reducing the width of the frame to meet the demand for a narrow frame.

[0004] In order to solve the above technical problems, the present application provides a display substrate, including a display area, a fan-out area and a binding area, wherein the binding area includes a binding pin area, and in a plane perpendicular to the display substrate, the binding pin area includes a substrate and a first insulating layer, a first metal layer, a second insulating layer, and a second metal layer sequentially arranged on the substrate along a first direction, wherein:

[0005] The second metal layer includes output pin modules, the output pin modules are arranged at intervals along the second direction, and each of the output pin modules includes at least one output pin;

[0006] A shielding pin, wherein the shielding pin is located between adjacent output pins;

[0007] A sub-shielding line, located between adjacent output pin modules, for shielding signal interference between the output pins;

[0008] The first metal layer is provided with a main shielding line, the main shielding line extends along the second direction, the main shielding line is connected to the sub-shielding line via hole, and is connected to the shielding pin via hole.

[0009] In one embodiment, the distance between the center points of two adjacent output pins is a first distance, the distance between the center points of the adjacent output pin and the shielding pin is a second distance, and the first distance is the same as the second distance; wherein,

[0010] The sum of the lengths of a plurality of the first spacings and a plurality of the second spacings on the second metal layer in the second direction is A, and both the first spacing and the second spacing are B, and A and B satisfy:

[0011] A=B×(c1+c2)

[0012] When the number of shielding pin configurations is c2-n, A and B satisfy:

[0013] A=B×(c1+c2-n), n<c2

[0014] Wherein, c1 is the number of the output pins, c2 is the number of the shielding pins, and n is a natural number.

[0015] In one embodiment, the number of the shielding pin configuration is 1, and A and B satisfy:

[0016] A=B×(c1+1).

[0017] In one of the embodiments, the shielding pin and the output pin extend along a third direction and have the same length, and the sub-shielding line has a greater length in the third direction than the shielding pin and the output pin;

[0018] The projections of the shielding pin and the output pin on the first metal layer are located on a side of the main shielding line away from the display area, and a partial projection of the sub-shielding line on the first metal layer overlaps with the main shielding line.

[0019] In one embodiment, at least a plurality of sub-shielding lines are included between adjacent output pin modules.

[0020] In one embodiment, a plurality of the sub-shielding lines are in a straight line shape, and a plurality of the sub-shielding lines are arranged in parallel, and the plurality of the sub-shielding lines arranged in parallel are perpendicular to the output pin; or

[0021] The plurality of sub-shielding lines arranged in parallel are parallel to the output pins.

[0022] In one of the embodiments, the second metal layer further includes a connecting portion, and two of the sub-shielding lines among the plurality of sub-shielding lines arranged in parallel are connected through the connecting portion.

[0023] In one of the embodiments, any two adjacent sub-shielding lines among the plurality of sub-shielding lines arranged in parallel are connected via a connecting portion, and in a direction perpendicular to the sub-shielding lines, two adjacent connecting portions are staggered.

[0024] In one embodiment, the sub-shielding line extends partially or entirely in a wavy shape; or

[0025] The sub-shielding line partially or entirely extends in a serpentine shape.

[0026] In one embodiment, the first metal layer further includes a plurality of signal lines, and the signal lines are connected to the output pin vias; or

[0027] The second metal layer also includes the plurality of signal lines, and the signal lines are connected to the output pins.

[0028] The present application also provides a display screen, comprising the display substrate in any of the above embodiments.

[0029] The present application also provides a display device, comprising the display screen in any of the above embodiments.

[0030] The technical solution provided by the embodiments of the present application may have the following beneficial effects:

[0031] It can be seen from the above embodiments that the present application forms a signal shielding structure by setting a number of sub-shielding wires between the output pins on the outermost metal layer of the binding pin area or between the output pin and the shielding pin, and setting a main shielding wire on any metal layer other than the outermost metal layer in the binding pin area, connecting the main shielding wire and the sub-shielding wire through vias, and then connecting the main shielding wire to the shielding pin through vias. This structure reduces the number of shielding pins without affecting the performance of the display substrate by replacing some shielding pins with sub-shielding wires. It can not only increase the output pins to improve the resolution of the display panel without changing the width of the binding pin area, but also further reduce the width of the binding pin area, thereby meeting the narrow frame requirements of different products.

[0032] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 A schematic diagram of the structure of a display panel at a viewing angle is provided in one embodiment of the present application.

[0035] Figure 2 It is a schematic structural diagram of a display substrate provided in an embodiment of the present application at a viewing angle.

[0036] Figure 3 It is a schematic structural diagram of a display substrate provided in an embodiment of the present application at a viewing angle.

[0037] Figure 4 For this application Figure 3 Sectional view along AA direction.

[0038] Figure 5 For this application Figure 4 Sectional view along CC direction.

[0039] Figure 6 For this application Figure 4 Cross-sectional view along the BB axis.

[0040] Figure 7 It is a schematic structural diagram of the second metal layer provided in one embodiment of the present application at a certain viewing angle.

[0041] Figure 8 Another structural schematic diagram of the second metal layer provided in one embodiment of the present application at a certain viewing angle.

[0042] Description of reference numerals:

[0043] 10. Display area; 11. Fan-out area; 12. Binding pin area; 120. Substrate; 121. First insulating layer; 122. First metal layer; 1220. Main shielding line; 123. Second insulating layer; 124. Second metal layer; 1240. Output pin; 1241. Shielding pin; 1242. Sub-shielding line; 1243. Connecting part; 1244. Signal line; 125. Via; 126. Third metal layer; 127. Third insulating layer; 128. Fourth metal layer; 129. Fourth insulating layer; 130. Fifth insulating layer.

[0044] D1, first direction; D2, second direction; D3, third direction. DETAILED DESCRIPTION

[0045] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The methods described in the following exemplary embodiments do not represent all methods consistent with the present application. Instead, they are merely examples of devices consistent with some aspects of the present application as detailed in the appended claims.

[0046] In this specification, "electrical connection" includes the case where components are connected together through an element having a certain function. There is no particular limitation on the "element having a certain electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0047] In the specification, "film" and "layer" can be interchanged. For example, "metal layer" can sometimes be replaced by "metal film". Or, "insulating film" can sometimes be replaced by "insulating layer".

[0048] In the specification, "pin" can be replaced by "pad", "solder point", "bump", "pin", etc. For example, "shielding pin" can sometimes be replaced by "shielding pad". Or, "output pin" can sometimes be replaced by "output bump".

[0049] like Figure 1-2 As shown, the display panel includes a display substrate 1", a driver chip 2" and a circuit board 3". The display substrate includes a display area 10", a fan-out area 11" and a binding area 12". Among them, the display area is an AA area (Active Area) capable of displaying images, the fan-out area is used to set the fan-out routing, and the binding area is used to set the driver chip and the circuit board. Among them, the binding area used to bind the circuit board is a binding pin area.

[0050] In the manufacturing process of OLED (Organic Light Emitting Diode) display panel, in order to achieve the purpose of connecting signals to the display substrate prepared by thin film process (Thin Film), the external flexible printed circuit (Flexible Printed Circuit, referred to as FPC) can be bound and connected in the binding pin area. The FOP (Fine-Pitch Organic Package) process is generally used for packaging between the flexible circuit board and the circuit binding area. This process allows more connection points to be arranged within a smaller pitch, thereby achieving higher resolution and finer pixel arrangement.

[0051] Currently, there is an increasing demand for products with high resolution and narrow bezels. When the resolution of the display panel increases, more pins (FOP pins) are needed to connect more pixels or process higher data transmission rates. The demand for narrow bezels leads to a need to reduce the total pin pitch (FOP total pitch) of the entire component, that is, in order to adapt to the narrow bezel design, the pins need to be arranged more compactly.

[0052] In electronic device design, GND is generally added between various electrical signals. "GND" is the abbreviation of "Ground", which refers to grounding, which is a common reference point in electronic systems. Specifically, in display panel design, adding GND (ground wire or ground layer) can play the following roles:

[0053] 1. Improve signal integrity: Signal integrity (SI) refers to the ability of a signal to maintain its integrity and accuracy during transmission. Proper GND layout helps maintain signal integrity and reduce distortion.

[0054] 2. Shielding signal interference: GND can be used as a shielding layer to protect signal lines from external electromagnetic fields, while also reducing crosstalk between signal lines.

[0055] 3. Reduce the voltage between bumps: Adding GND can provide additional electrical connection between bumps, which helps to reduce the voltage difference between them and reduce the risk of electromigration and thermal stress.

[0056] 4. It also has the advantages of protecting the circuit from damage, reducing noise levels, maintaining stable operation of the circuit, improving the electromagnetic compatibility of the equipment, and improving the thermal stability of the equipment.

[0057] Continue to refer to Figure 2 Generally, in the binding pin area of ​​the display substrate, a number of output pins 121" for connecting signal lines are arranged at intervals. In order to avoid interference between signals, a number of shielding pins 122" for connecting shielding lines are also arranged. Among them, the output pins 121" and the shielding pins 122" are arranged at intervals. The shielding electrode located in the fan-out area is connected to the shielding pin 122" through the shielding line, and the shielding pin 122" provides a ground (GND) signal to the shielding electrode.

[0058] The current pin pitch limit in the 12" bonding pin area is 100μm (micrometer). The cost of developing and replacing new bonding equipment is too high, and the only way to reduce the FOP total pitch is to reduce the number of pins. However, the setting of shielding pins in the existing solution makes it impossible to further reduce the FOP total pitch while maintaining high resolution and signal stability.

[0059] Reference Figures 3 to 6 The display substrate provided in the present application can meet the demand for narrow bezel of the display panel by reducing the number of pins and reducing the FOP total pitch while ensuring the high resolution and stable operation of the display panel.

[0060] It includes a display area 10, a fan-out area 11 and a binding area. The binding area includes a binding pin area 12. In a plane perpendicular to the display substrate, the binding pin area includes a substrate 120 and a first insulating layer 121, a first metal layer 122, a second insulating layer 123, and a second metal layer 124 sequentially arranged on the substrate 120 along a first direction D1.

[0061] The second metal layer 124 includes output pin modules, shielding pins 1241 and sub-shielding lines 1242. The output pin modules are arranged at intervals along the second direction D2, and each output pin module includes at least one output pin 1240. The shielding pins 1241 are located between adjacent output pins 1240. The sub-shielding lines 1242 are located between adjacent output pin modules and are used to shield signal interference between the output pins 1240.

[0062] Reference Figure 5 The first metal layer 122 is provided with a main shielding line 1220, the main shielding line 1220 extends along the second direction D2, the main shielding line 1220 is connected to the sub-shielding line 1242 through a via hole, and is connected to the shielding pin 1241 through a via hole. It should be noted that in order to understand the solution more clearly and intuitively, Figure 5 The shielding pins, output pins and sub-shielding lines shown in dotted lines represent their projections on the first metal layer 122 .

[0063] It should also be noted that the number of insulating layers and metal layers in the present application is not particularly limited, and those skilled in the art can design them according to the specific conditions of the display substrate. Several metal layers may be included between the first metal layer 122 and the substrate 120, or several metal layers may be included between the first metal layer 122 and the second metal layer 124. A corresponding insulating layer is provided between the two metal layers.

[0064] For example, refer to Figure 4 A third metal layer 126 and a third insulating layer 127 are further disposed between the first metal layer 122 and the first insulating layer 121. A fourth metal layer 128, a fourth insulating layer 129 and a fifth insulating layer 130 are further disposed between the first metal layer 122 and the second metal layer 124.

[0065] In one embodiment, the first insulating layer 121 is generally a buffer layer. The fourth insulating layer 129 is generally an ILD (dielectric) layer. The fifth insulating layer 130 is generally a PLN (support) layer, etc. The different locations of each insulating layer have different effects, which will not be elaborated again.

[0066] Optionally, the metal layer can be made of metal materials, such as any one or more of silver (Ag), copper such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0067] It should be noted that, in this embodiment, the second metal layer 124 can be understood as the metal layer where the output pin 1240, the shielding pin 1241 and the sub-shielding line 1242 are located. It is generally located at the outermost layer of the binding pin area, which is closest to the flexible circuit board electrically connected to the display substrate. The first metal layer 122 can be understood as the metal layer where the main shielding line 1220 is located. The main shielding line 1220 can be set on any metal layer between the second metal layer 124 and the substrate 120.

[0068] In some embodiments, the main shielding line 1220 may be disposed on the third metal layer 126 or on the fourth metal layer 128 .

[0069] Likewise, the insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer.

[0070] The present application sets a main shielding line 1220 on the first metal layer 122, sets a sub-shielding line 1242 and a shielding pin 1241 on the second metal layer 124, then connects the sub-shielding line 1242 and the main shielding line 1220 through vias, and then connects the main shielding line 1220 electrically connected to a plurality of sub-shielding lines 1242 to the shielding pin 1241 through vias. This arrangement enables the shielding electrode to be electrically connected to the shielding pin 1241 through the main shielding line 1220, and enables the shielding pin 1241 to provide a ground (GND) signal to the shielding electrode.

[0071] While ensuring high resolution and stability of the display panel, the present application reduces the number of shielding pins 1241 in the binding pin area by replacing some shielding pins 1241 set between output pins 1240 with sub-shielding lines 1242, reduces the number of pins, and reduces the total pitch of FOP to meet the demand for a smaller and narrower border of the display panel. In particular, it can meet the demand for special long-strip screens required in some wearable devices.

[0072] In some implementations, the number of output pins 1240 included in the output pin module is adjusted according to the display type and display area of ​​the display substrate, and this embodiment does not further limit this. Preferably, each output pin module includes two output pins 1240 .

[0073] In some embodiments, the distance between the center points of two adjacent output pins 1240 is a first spacing, the distance between the center points of adjacent output pins 1240 and shielding pin 1241 is a second spacing, and the first spacing is the same as the second spacing.

[0074] Optionally, in some embodiments, the first spacing and the second spacing may be different in size. The difference between the two may be adjusted and set according to the specific requirements of the display substrate. That is, the first spacing and the second spacing may satisfy any mathematical relationship. No further limitation is made here.

[0075] In some embodiments, reference Figure 6 , the sum of the lengths of the first spacings and the second spacings in the second direction D2 in the binding pin area is A, the first spacing and the second spacing are both B, and A and B satisfy:

[0076] A=B×(c1+c2)

[0077] Wherein, c1 is the number of output pins 1240 , and c2 is the number of shielding pins 1241 .

[0078] Specifically, A is Total Pitch, that is, the total fine pitch, which can also be understood as the width of the binding pin area. The distances between the shielding pins 1241, between the output pins 1240, and between the shielding pins 1241 and the output pins 1240 are all B. For example, the B limit in the binding pin area can be 100μm (micrometer). The cost of developing and replacing new binding equipment is too high. The only way to reduce the total pitch is to reduce the number of output pins 1240 or shielding pins 1241, and both are indispensable to ensure the high resolution and stability of the display panel.

[0079] As can be seen from the above, the present application has a shielding structure formed by combining the sub-shielding line 1242, the main shielding line 1220 and the shielding pin 1241. By replacing the shielding pin 1241 with the sub-shielding line 1242, the total value of A can be reduced, which can further reduce the width of the binding pin area to meet the demand for a narrower frame. Alternatively, more output pins 1240 can be added to improve the resolution of the display surface.

[0080] Specifically, in the present application, the number of shielding pins 1241 configured is c2-n, and A and B satisfy:

[0081] A=B×(c1+c2-n), n<c2

[0082] Wherein, n is a natural number.

[0083] It can be understood that reducing the number of n shielding pins 1241 can reduce the width of the binding pin area. The requirements of high resolution and narrow frame of the display panel are met. Then, in order to ensure the stability of the display panel, several sub-shielding lines 1242 are added to the second metal layer 124. The sub-shielding lines 1242 are respectively connected to the main shielding lines 1220 on the first metal layer 122, and then connected to c2 shielding pins 1241 through the main shielding lines 1220, so as to provide a ground (GND) signal from the shielding pin 1241 to the shielding electrode.

[0084] It should be noted that the number of shielding pins 1241 reduced and the number of sub-shielding lines 1242 increased can be selected by those skilled in the art according to the specific production requirements of the display panel, and no further limitation is made here. The number of shielding pins 1241 reduced and the number of sub-shielding lines 1242 increased can be the same or different.

[0085] In some implementations, the number of shielding pins 1241 configured is 1. A and B satisfy:

[0086] A=B×(c1+1).

[0087] Reducing the number of shielding pins 1241 to 1 can maximize the reduction of the total pitch, that is, maximize the narrowing of the border to achieve the best effect.

[0088] The inventor of the present application has verified that the shielding structure of the present application can reduce the total pin spacing after being applied to a specific product. The comparative example in Table 1 below shows the parameters of the binding pin area before optimization by the present solution, and the embodiment shows the parameters of the binding pin area after optimization by the shielding structure of the present solution.

[0089]

[0090]

[0091] Table 1

[0092] It can be seen from the above table that the total pin spacing before optimization is 49400. If you want to further reduce the border, you can reduce the number of shielding pins 1241 according to actual needs, and then add a certain number of sub-shielding lines 1242. In this way, while meeting the display panel width size requirements, it ensures that the electronic design rules of GND isolation between the display panel signals are met.

[0093] Specifically, the total pin spacing can be optimized by reducing the number of shielding pins 1241 to 1. The added sub-shielding wires 1242 are connected to the main shielding wire 1220 through vias. Then the main shielding wire 1220 is connected to the shielding pins 1241 through vias.

[0094] Optionally, one shielding pin 1241 may be provided between two adjacent output modules in the binding pin area according to the type, structure or requirement of the display panel.

[0095] In some embodiments, one shielding pin 1241 is disposed between the sub-shielding line 1242 and the output pin 1240 , or may be disposed between two adjacent output pins 1240 .

[0096] In some embodiments, reference Figure 6 The shielding pin 1241 and the output pin 1240 extend along the third direction D3 and have the same length, and the length of the sub-shielding line 1242 in the third direction D3 is greater than that of the shielding pin 1241 and the output pin 1240 .

[0097] Reference Figure 5 The projections of the shielding pin 1241 and the output pin 1240 on the first metal layer 122 are located on the side of the main shielding line 1220 away from the display area, and part of the projection of the sub-shielding line 1242 on the first metal layer 122 overlaps with the main shielding line 1220 .

[0098] Continue to refer to Figure 5 The projection of the portion of the sub-shielding line 1242 that exceeds the output pin 1240 and the shielding pin 1241 overlaps with the main shielding line 1220 in the first metal layer 122, which facilitates the via connection between the two.

[0099] In some embodiments, the length of the main shielding line 1220 extending in the second direction D2 is equal to the distance between the two sub-shielding lines 1242 at the end portions of the second metal layer 124 .

[0100] Optionally, refer to Figure 5 The extension length of the main shielding line 1220 in the second direction D2 is greater than the distance between the two sub-shielding lines 1242 at the end. It should be noted that as long as all the sub-shielding lines 1242 can be connected to the main shielding line 1220 through vias, no further limitation is made here.

[0101] In some embodiments, reference Figure 7 , the shielding pin 1241, the output pin 1240 and the sub-shielding line 1242 extend along the third direction D3 and have the same length. The partial projections of the output pin 1240, the shielding pin 1241 and the sub-shielding line 1242 on the first metal layer 122 overlap with the main shielding line 1220. A hole is punched at the position where the projections of the sub-shielding line 1242 and the main shielding line 1220 overlap, so that the two are electrically connected. A hole is punched at the position where the projections of the shielding pin 1241 and the main shielding line 1220 overlap, so that the two are electrically connected.

[0102] It should be noted that for ease of understanding, Figure 7 The dotted rectangle in the figure is the projection position of the main shielding line 1220 on the second metal layer 124.

[0103] In some embodiments, the width of the sub-shielding line 1242 is the same as the width of the touch signal line 1244 in the fan-out region. Preferably, the width of the sub-shielding line 1242 may be 4.5 μm, 5 μm, 6 μm, etc.

[0104] Optionally, the width of the sub-shielding line 1242 is smaller than the width of the main shielding line 1220 .

[0105] In some embodiments, the width of the sub-shielding line 1242 is smaller than the width of the output pin 1240. The width of the sub-shielding line 1242 is smaller than the width of the shielding pin 1241.

[0106] Optionally, the widths of the output pin 1240 and the shielding pin 1241 may be the same or different.

[0107] In some implementations, a plurality of shielding sub-lines 1242 may be provided between any two adjacent output pin modules. The specific setting is adjusted according to the display type and display area of ​​the display panel, and is not further limited in this embodiment.

[0108] In some implementations, the number of sub-shielding lines 1242 disposed between several groups of adjacent output pin modules may be the same or different.

[0109] In some embodiments, when the spacing between adjacent output pins 1240 and shielding pins 1241 remains unchanged, multiple sub-shielding lines 1242 are added between the output pins 1240 and the shielding pins 1241. As the number of sub-shielding lines 1242 increases, the spacing between adjacent output pins 1240 and shielding pins 1241 increases accordingly, so as to meet the via connection between the sub-shielding lines 1242 and the main shielding line 1220.

[0110] In some embodiments, the number of output pins 1240 disposed between adjacent sub-shielding lines 1242 may be the same or different.

[0111] Optionally, refer to Figure 7 Two output pins 1240 are arranged between some adjacent sub-shielding lines 1242 , and one output pin 1240 is arranged between some adjacent sub-shielding lines 1242 .

[0112] In some embodiments, the sub-shielding lines 1242 are arranged in a straight line, and a plurality of sub-shielding lines 1242 are arranged in parallel.

[0113] It should be particularly noted that the projections of several parallel sub-shielding lines 1242 on the first metal layer 122 need to overlap with the main shielding line 1220, so as to ensure the connection between the sub-shielding lines 1242 and the main shielding line 1220. It can also be understood that the projections of the main shielding line 1220 on the second metal layer 124 can only be partially located in the gaps between the sub-shielding lines 1242, and cannot be completely located in the gaps between the sub-shielding lines 1242, so as to avoid the main shielding line 1220 and the sub-shielding line 1242 being unable to be connected by vias.

[0114] In some embodiments, the plurality of sub-shielding lines 1242 arranged in parallel are perpendicular to the output pins 1240 .

[0115] In one embodiment, when the sub-shielding lines 1242 are perpendicular to the output pins 1240 , a plurality of sub-shielding lines 1242 are arranged in parallel and spaced apart along the third direction D3 .

[0116] In some embodiments, the plurality of sub-shielding lines 1242 disposed in parallel are parallel to the output pins 1240 .

[0117] In one embodiment, when the sub-shielding lines 1242 are parallel to the output pins 1240 , a plurality of sub-shielding lines 1242 are arranged in parallel and spaced apart along the second direction D2 .

[0118] In some embodiments, among the plurality of sub-shielding lines 1242 between two adjacent output pins 1240 , two sub-shielding lines 1242 are perpendicular to each other, and one of the two perpendicular shielding lines is parallel to the output pin 1240 .

[0119] In some embodiments, the second metal layer 124 further includes a connection portion 1243, and two sub-shielding lines 1242 among the plurality of sub-shielding lines 1242 arranged in parallel are connected by the connection portion 1243. The material of the connection portion 1243 may be the same as that of the sub-shielding line 1242.

[0120] In some embodiments, reference Figure 8 Any two adjacent sub-shielding lines 1242 among the multiple sub-shielding lines 1242 arranged in parallel are connected by a connecting portion 1243, and in a direction perpendicular to the sub-shielding lines 1242, two adjacent connecting portions 1243 are staggered.

[0121] A plurality of sub-shielding lines 1242 arranged in parallel are connected via a connecting portion 1243 , so that the sub-shielding lines 1242 are in a zigzag shape.

[0122] In some implementations, the sub-shielding line 1242 partially or entirely extends in a wavy shape. Alternatively, the sub-shielding line 1242 partially or entirely extends in a serpentine shape. The specific adjustment and setting is based on the display type and display area of ​​the display substrate, and this embodiment does not further limit this.

[0123] In some implementations, the first metal layer 122 further includes a plurality of signal lines 1244, and the signal lines 1244 are connected to the output pins 1240 via vias. In this embodiment, the signal lines 1244 and the main shielding lines 1220 are located in the same metal layer.

[0124] Optionally, the second metal layer 124 further includes a plurality of signal lines 1244, and the signal lines 1244 are connected to the output pins 1240. In this embodiment, the signal lines 1244, the output pins 1240, the shielding pins 1241, and the sub-shielding lines 1242 are located in the same metal layer.

[0125] It should be noted that the signal lines 1244 may include data signal lines 1244, touch signal lines 1244, power signal lines 1244, etc. The arrangement and connection of the signal lines 1244 are conventional operations in the art and will not be elaborated herein.

[0126] The present application also provides a display screen, including the display substrate in any of the above embodiments. Based on the above display substrate, a high-resolution narrow-frame display screen is provided, which can meet some special product requirements.

[0127] The present application also provides a display device, including the display screen in any of the above embodiments. The display device can be a smart phone, a tablet computer, a wearable device, a gaming device, an augmented reality device, a notebook, a desktop computing device, etc.

Claims

1. A display substrate, comprising a display area, a fan-out area and a binding area, wherein the binding area comprises a binding pin area, characterized in that: In a plane perpendicular to the display substrate, the binding pin area includes a substrate and a first insulating layer, a first metal layer, a second insulating layer, and a second metal layer sequentially arranged on the substrate along a first direction, wherein: The second metal layer includes output pin modules, the output pin modules are arranged at intervals along the second direction, and each of the output pin modules includes at least one output pin; A shielding pin, wherein the shielding pin is located between adjacent output pins; A sub-shielding line, located between adjacent output pin modules, for shielding signal interference between the output pins; The first metal layer is provided with a main shielding line, the main shielding line extends along the second direction, the main shielding line is connected to the sub-shielding line via hole, and is connected to the shielding pin via hole.

2. The display substrate according to claim 1, characterized in that: The distance between the center points of two adjacent output pins is a first distance, the distance between the center points of the adjacent output pin and the shielding pin is a second distance, and the first distance is the same as the second distance; wherein, The sum of the lengths of a plurality of the first spacings and a plurality of the second spacings on the second metal layer in the second direction is A, and both the first spacing and the second spacing are B, and A and B satisfy: A=B×(c1+c2) When the number of shielding pin configurations is c2-n, A and B satisfy: A=B×(c1+c2-n), n<c2 Wherein, c1 is the number of the output pins, c2 is the number of the shielding pins, and n is a natural number.

3. The display substrate according to claim 2, characterized in that: The number of the shielding pin configuration is 1, and A and B satisfy: A=B×(c1+1).

4. The display substrate according to claim 1, characterized in that: The shielding pin and the output pin extend along a third direction and have the same length, and the sub-shielding line has a greater length in the third direction than the shielding pin and the output pin; The projections of the shielding pin and the output pin on the first metal layer are located on a side of the main shielding line away from the display area, and a partial projection of the sub-shielding line on the first metal layer overlaps with the main shielding line.

5. The display substrate according to claim 4, characterized in that: At least a plurality of sub-shielding lines are included between adjacent output pin modules.

6. The display substrate according to claim 5, characterized in that: A plurality of the sub-shielding lines are in a straight line shape, and a plurality of the sub-shielding lines are arranged in parallel, and the plurality of the sub-shielding lines arranged in parallel are perpendicular to the output pin; or The plurality of sub-shielding lines arranged in parallel are parallel to the output pins.

7. The display substrate according to claim 6, characterized in that: The second metal layer further includes a connecting portion, and two of the sub-shielding lines among the plurality of sub-shielding lines arranged in parallel are connected through the connecting portion.

8. The display substrate according to claim 7, characterized in that: Any two adjacent sub-shielding lines among the plurality of sub-shielding lines arranged in parallel are connected via a connecting portion, and in a direction perpendicular to the sub-shielding lines, two adjacent connecting portions are staggered.

9. The display substrate according to claim 5, characterized in that: The sub-shielding line extends partially or entirely in a wavy shape; or The sub-shielding line partially or entirely extends in a serpentine shape.

10. The display substrate according to any one of claims 1 to 9, characterized in that: The first metal layer further includes a plurality of signal lines, and the signal lines are connected to the output pin vias; or The second metal layer also includes the plurality of signal lines, and the signal lines are connected to the output pins.

11. A display screen, characterized in that: The invention comprises a display substrate as claimed in any one of claims 1 to 10.

12. A display device, characterized in that: Comprising a display screen as claimed in claim 11.

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