Chip stacking framework and storage equipment
By adopting chip stacking architecture and pin re-layout technology in chip packaging design, the problems of complex wiring and large substrate size in the prior art are solved, and more efficient transmission and smaller substrate area are achieved.
Patent Information
- Application Number
- CN202421321694.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-11
- Publication Date
- 2025-06-06
- Estimated Expiration
- 2034-06-11
AI Technical Summary
In the existing chip packaging design, the wiring between the main control chip and the memory chip is complex, resulting in large substrate size, making it difficult to effectively reduce wiring difficulty and substrate area.
Using a chip stacking architecture, the pads of the memory chip are re-layed to form the same pads as the pin configuration of the main control chip, and set at a preset angle. The main control chip is stacked on the re-layed memory chip and connected through metal leads.
It effectively reduces wiring complexity, reduces substrate area, improves transmission efficiency, and saves time and structural costs.
Smart Images
Figure CN222953080U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of storage, and in particular to a chip stacking architecture and a storage device. Background Art
[0002] In the existing chip packaging design, the main control chip and the memory (flash) chip are interconnected through the wiring on the substrate, which will lead to complex wiring, too large current return area and substrate size.
[0003] Therefore the prior art still needs to be improved and enhanced. Utility Model Content
[0004] The main purpose of the utility model is to provide a chip stacking structure, aiming to solve the problems of complex wiring and large substrate size during chip packaging in the prior art.
[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:
[0006] In a first aspect, an embodiment of the present application provides a chip stacking architecture, including: a main control chip, a substrate, and a memory chip after pin re-layout;
[0007] The memory chip is arranged on the substrate, and the main control chip is stacked on the memory chip after the pins are rearranged and connected to the memory chip through metal leads.
[0008] In some embodiments, the main control chip includes a plurality of first pads, and the storage chip includes a plurality of second pads, and the second pads and the first pads having the same pin configuration network are arranged at a preset angle.
[0009] In some embodiments, the first pad and the second pad are wire-bonded via metal wires.
[0010] In some embodiments, a plurality of the second pads are obtained by rewiring according to the arrangement positions of an equal number of the first pads.
[0011] In some embodiments, the connection line between the first pad and the second pad of the same pin configuration network forms a preset angle with the horizontal line; the preset angle is within a preset angle range; wherein the preset angle range includes: -45° to +45°.
[0012] In some embodiments, the data pin and the clock pin of the main control chip are bonded to the substrate through metal wires; wherein the first pad includes the data pin and the clock pin.
[0013] In some embodiments, the chip stacking architecture further includes: a plurality of memory chips, each of which includes a plurality of third pads; the third pads are original pads on the memory chip without pin re-layout; the third pads of all the memory chips with the same pin configuration network are connected in series through metal leads;
[0014] After the series connection, the second pad of the highest-level storage chip is correspondingly connected to the first pad of the main control chip with the same pin configuration network through the metal lead.
[0015] In some embodiments, the substrate and the memory chip, and the memory chip and the main control chip are bonded together by an adhesive; wherein the adhesive comprises a wafer bonding film.
[0016] In some embodiments, all re-wired second pads are disposed on one side of the main control chip.
[0017] In a second aspect, an embodiment of the present application provides a storage device comprising the chip stacking architecture as described above.
[0018] Compared with the prior art, the utility model provides a chip stacking architecture and a storage device, comprising: a main control chip, a substrate and a memory chip after pin re-layout; the memory chip is arranged on the substrate, and the main control chip is stacked on the memory chip after pin re-layout and is connected to the memory chip by metal leads.
[0019] In the present application, the pads of the storage chip are rearranged so that the obtained second pad and the first pad of the main control chip with the same network of pin configuration as the second pad are arranged at a preset angle, the storage chip is arranged on the substrate, and then the main control chip is stacked on the memory chip after the pins are rearranged, and a stacked packaging design from the main control chip to the storage chip and then to the substrate is realized through metal lead wiring, which not only effectively reduces the wiring difficulty and reduces the substrate area, thereby saving time and improving transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0021] Figure 1 A front view of the chip layout inside the package in a preferred embodiment of the chip stacking architecture provided by the present invention;
[0022] Figure 2 A top view of the chip layout inside the package in a preferred embodiment of the chip stacking architecture provided by the present invention;
[0023] Figure 3 A schematic diagram of the connection of metal leads in a preferred embodiment of the chip stacking architecture provided by the present invention;
[0024] Figure 4 This is an example diagram of the chip layout inside the package in a preferred embodiment of the chip stacking architecture provided by the present invention.
[0025] Reference numerals: 10: main control chip; 20: storage chip; 30: substrate. DETAILED DESCRIPTION
[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.
[0027] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.
[0028] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.
[0029] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.
[0030] The utility model provides a chip stacking architecture and storage device. In the present application, the pads of the storage chip are rearranged so that the obtained second pad and the first pad of the main control chip with the same network of pin configuration as the second pad are arranged at a preset angle, the storage chip is arranged on the substrate, and then the main control chip is stacked on the memory chip after the pins are rearranged, and a stacking packaging design from the main control chip to the storage chip and then to the substrate is realized through a metal lead method, which not only effectively reduces the wiring difficulty and reduces the substrate area, but also saves time and improves the transmission efficiency.
[0031] The chip stacking method design is described below through specific exemplary embodiments. It should be noted that the following embodiments are only used to explain the technical solution of the utility model and are not specifically limited:
[0032] See also Figure 1 An embodiment of the present application provides a chip stacking architecture, including: a main control chip 10, a memory chip 20 (flash chip) after pin re-layout, and a substrate 30; the memory chip 20 is arranged on the substrate 30, and the main control chip 10 is stacked on the memory chip 20 after pin re-layout and is connected to the memory chip 20 through metal leads.
[0033] The front view of the chip layout inside the package is as follows Figure 1 As shown, the main control chip 10, the RDL (Re-distributed layer, the redistribution process (rewiring) is to change the contact position of the original IC circuit (I / O pad) through the wafer-level metal wiring process and the bump process to make the IC applicable to different component modules) memory chip 20 and the substrate 30 are arranged in sequence, Figure 1 The WB wiring structure is included.
[0034] Optionally, the chip stacking architecture in the present invention is applied to chip packaging design, and the chip stacking architecture is mainly composed of a main control chip 10 , a memory chip 20 and a substrate 30 .
[0035] First, the pads on the memory chip 20 are re-arranged according to the arrangement positions of the pads (or called bonding pads, Bond Pad) on the main control chip 10 to obtain the memory chip 20 after the pin re-arrangement. Then, the main control chip 10, the memory chip 20 after the pin re-arrangement and the substrate 30 are arranged in sequence, that is, the memory chip 20 is arranged on the substrate 30, and the main control chip 10 is stacked on the memory chip 20 after the pin re-arrangement, and the main control chip 10 and the memory chip 20 are interconnected by metal wires.
[0036] In the present application, the main control chip 10 is stacked on the memory chip 20 after pin re-layout by metal leads, replacing the traditional wiring on the substrate 30, reducing the distance between the main control chip 10 and the memory chip 20 and effectively improving the transmission rate.
[0037] Furthermore, the main control chip 10 includes a plurality of first pads, and the storage chip 20 includes a plurality of second pads, and the second pads and the first pads having the same pin configuration network are arranged at a preset angle.
[0038] The preset angle is between -45° and +45°, and more preferably between -10° and +10°, which is easier to implement in terms of process.
[0039] Optionally, the original bond pads of the memory chip 20 are re-layouted by using the re-layout RDL technology to obtain the memory chip 20 after pin re-layout.
[0040] The second pad of the memory chip 20 (i.e., the pad after RDL) and the first pad of the main control chip 10 with the same network as the second pad pin configuration are arranged at a preset angle, that is, the second pad and the first pad with the same network as the second pad pin configuration are arranged at a preset angle on the horizontal line. Figure 2 As shown; wherein, the second pads on the left and right below the main control chip 10 are power and ground Bond Pads, which are connected to the substrate through metal leads to provide power for the memory chip 20 and the main control chip 10.
[0041] In the present application, the pads of the memory chip 20 are rearranged to reduce the scope and complexity of wiring, and the size of the substrate 30 can be reduced, thereby effectively saving time and structural costs, and to a certain extent reducing parasitic effects, such as the impact of impedance, and the area of reflux.
[0042] Furthermore, the first pad is wire-bonded to the second pad via a metal wire.
[0043] Wire bonding is a method of connecting metal wires to pads, that is, a technology that connects internal and external chips. Figure 3 , structurally speaking, the metal lead (corresponding to Figure 3 The chip pad (the chip pad in this application is the first pad, corresponding to Figure 3 The carrier pad (the carrier pad in this application is the second pad, corresponding to Figure 3 The middle bid number ④) acts as a bridge; among them, Figure 3 The number ③ represents the primary bonding, and the number ⑤ represents the secondary bonding.
[0044] There are three main methods for connecting metal leads to pads: thermo-compression method, ultrasonic method and thermo-ultrasonic method. Thermo-compression method is a method of connecting pads and capillary splitters (tools similar to capillary moving metal leads) by heating and compressing; ultrasonic method.
[0045] The first is thermal compression bonding, which is a method of connecting a pad and a capillary cutter (a tool similar to a capillary for moving metal leads) by heating and compressing. The chip pad is heated to about 200°C in advance, and then the temperature of the tip of the capillary cutter is increased to make it spherical. Pressure is applied to the pad through the capillary cutter to connect the metal lead to the pad.
[0046] The second is the ultrasonic method, which is a method of applying ultrasonic waves to a capillary wedge for connection without heating. It is a method of applying ultrasonic waves to a wedge (similar to a capillary wedge, it is a tool for moving metal leads, but it does not form a ball) to connect metal leads to pads. The advantage of this method is low process and material costs; but because the ultrasonic method replaces the heating and pressurizing process with easy-to-operate ultrasonic waves, the bonded tensile strength (the ability to withstand the pulling of the lead after connection) is relatively weak.
[0047] The third method is the thermosonic method, which is a comprehensive method that uses both heating and ultrasound; by applying heat, pressure and ultrasound to the capillary cutter, it is connected under optimal conditions.
[0048] The material of the metal lead is determined by comprehensively considering various welding parameters and combining them into the most appropriate method. Among them, welding parameters include semiconductor product type, package type, pad size, metal lead diameter, welding method, and metal lead tensile strength and elongation and other reliability indicators. Typical metal lead materials are gold (Au), aluminum (Al) and copper (Cu). Among them, the gold wire uses the "thermal ultrasonic-capillary splitter-ball" wire bonding method, and the aluminum wire uses the aluminum wire wedge wire bonding method (Aluminum Wedge Wire Bonding), that is, the "ultrasonic-wedge bonding" method.
[0049] Optionally, continue to Figure 3, the first pad of the main control chip 10 is wire-bonded to the second pad of the re-arranged memory chip 20 through metal wires, so that the main control chip 10 and the flash chip are interconnected through wire bonding. Then, the effect diagram of the interconnection of several memory chips 20 and the main control chip 10 on the substrate 30 is as follows: Figure 4 In order to distinguish, several memory chips 20 are marked as a first memory chip 21, a second memory chip 22, and so on to an nth memory chip 2n, where n is generally 2 or 4.
[0050] In the present application, the first pad is wire-bonded to the second pad by metal wires, so as to avoid wiring the main control chip 10 and the memory chip 20 directly on the substrate 30, thereby reducing wiring difficulty and reducing the size of the substrate.
[0051] Furthermore, a plurality of the second pads are obtained by rewiring according to arrangement positions of an equal number of the first pads.
[0052] Optionally, a number of first pads are selected correspondingly according to the target implementation function of the storage chip 20, and according to the arrangement positions of the first pads, the same number of pads with the same network configuration as the first pad pins are rewired to obtain second pads, thereby realizing the rewiring of the same number of second pads corresponding to the selected first pads, and realizing the function of flexibly re-layouting the pads.
[0053] Furthermore, a line connecting the first pad and the second pad of the same pin configuration network forms a preset angle with a horizontal line; the preset angle is within a preset angle range; wherein the preset angle range includes: -45° to +45°.
[0054] Optionally, continue to Figure 2 , the connection line between the first solder pad and the second solder pad of the same pin configuration network is at a preset angle to the horizontal line, and the preset angle is within a preset angle range; that is, the connection line between the first solder pad and the second solder pad of the same pin configuration network is set within the preset angle range (-45° to +45°) with the horizontal line; under the ideal state in the present application, the first solder pad and the second solder pad of the same pin configuration network are set on the same level.
[0055] Furthermore, the data pin and the clock pin of the main control chip 10 are bonded to the substrate 30 through metal wires; wherein the first pad includes the data pin and the clock pin.
[0056] Optionally, the data bus, power line and clock line on the main control chip 10 are directly connected to the substrate 30 through WB bonding, which helps to avoid damage to the data bus and clock line of the main control chip 10 due to overheating of the memory chip 20, thereby ensuring the normal operation of the main control chip 10 and ensuring the stability of the transmission rate.
[0057] Furthermore, the chip stacking architecture also includes: multiple memory chips 20, each of the memory chips 20 includes a plurality of third pads; the third pads are original pads on the memory chip 20 without pin re-layout; the third pads of the same network of pin configurations in all memory chips 20 are connected in series through metal leads; the second pad of the highest-level memory chip after series connection is connected to the first pad of the same network of pin configurations in the main control chip 10 through corresponding metal leads.
[0058] Optionally, in another embodiment of the present application, there is a situation where a plurality of storage chips 20 are respectively connected in series with a substrate 30 and a main control chip 10:
[0059] First, the third pads of the plurality of memory chips 20 with the same pin configuration network are connected in series through metal leads to form a stacked structure of the plurality of memory chips 20. Then, the second pads of the surface memory chips 20 are connected in series with the first pads with the same pin configuration network through metal leads.
[0060] Similarly, the data bus and clock line on the main control chip 10 are directly connected to the substrate 30 through metal wires.
[0061] It should be noted that in another embodiment of the present application, there is a situation where a storage chip 20 is respectively connected to a substrate 30 and multiple main control chips 10. At this time, the second pads are respectively connected to the first pads of all pins configured with the same network through metal leads, and at the same time, the second pads are connected to the substrate 30 through metal leads.
[0062] Furthermore, the substrate 30 and the memory chip 20 , and the memory chip 20 and the main control chip 10 are bonded together by adhesive; wherein the adhesive includes a wafer bonding film.
[0063] Optionally, in addition to the data pins and clock pins of the main control chip 10 being bonded to the substrate 30 through metal wires, the memory chip 20 is bonded to the main control chip 10 through an adhesive (for example, a die attach film (DAF)), and the memory chip 20 is also bonded to the substrate 30 through an adhesive, so that after the memory chip 20 is bonded to the substrate 30, the main control chip 10 is bonded to the memory chip 20, forming a stacked design of the main control chip 10, the memory chip 20 and the substrate 30.
[0064] Furthermore, all rewired second pads are arranged on one side of the main control chip 10, and the power supply and ground Bond Pad on the other side are connected to the substrate 30 through metal wires to provide power for the memory chip 20 and the main control chip 10. At the same time, several more power supply and ground Bond Pads are arranged to prevent overheating.
[0065] Optionally, in order to better layout and reduce the wiring range, all rewired second pads are set on the same side (left and right) of the main control chip 10, that is, on one side of the main control chip 10; and the first pad and the second pad are set opposite to each other on the same side, so as to better connect the two with metal leads and achieve scientific wiring. Then, in other embodiments of the present application, the first pad and the second pad agree to be set in the same direction, for example, both facing the outside of the substrate 30.
[0066] In summary, the utility model provides a chip stacking architecture and a storage device, comprising: a main control chip 10, a memory chip 20 after pin re-layout, and a substrate 30; the memory chip 20 is arranged on the substrate 30, and the main control chip 10 is stacked on the memory chip 20 after pin re-layout and connected to the memory chip 20 by metal leads. In the present application, the main control chip 10 is stacked on the memory chip 20 after pin re-layout, the main control chip 10 and the memory chip 20 are interconnected by metal leads, and the memory chip 20 is arranged on the substrate 30, so that the complexity of the wiring of the substrate 30 is reduced, and the area of the substrate 30 is reduced, thereby improving the transmission rate.
[0067] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.
Claims
1. A chip stacking architecture, characterized in that: include: The main control chip, substrate and memory chip after pin re-layout; The memory chip is arranged on the substrate, and the main control chip is stacked on the memory chip after the pins are rearranged and connected to the memory chip through metal leads.
2. The chip stacking architecture according to claim 1, characterized in that: The main control chip includes a plurality of first pads, and the storage chip includes a plurality of second pads. The second pads and the first pads having the same pin configuration network are arranged at a preset angle.
3. The chip stacking architecture according to claim 2, characterized in that: The first pad and the second pad are wire-bonded via metal wires.
4. The chip stacking architecture according to claim 2, characterized in that: A plurality of the second pads are obtained by rewiring according to the arrangement positions of an equal number of the first pads.
5. The chip stacking architecture according to claim 2, characterized in that: The connection line between the first pad and the second pad of the same pin configuration network forms a preset angle with the horizontal line; the preset angle is within a preset angle range; wherein the preset angle range is: -45° to +45°.
6. The chip stacking architecture according to claim 2, characterized in that: The data pin and the clock pin of the main control chip are bonded to the substrate through metal wires; wherein the first pad includes the data pin and the clock pin.
7. The chip stacking architecture according to claim 2, characterized in that: Also includes: A plurality of memory chips, each of which comprises a plurality of third pads; the third pads are original pads on the memory chip without pin re-layout, and the third pads with the same pin configuration network in all the memory chips are connected in series through metal leads; After the series connection, the second pad of the highest-level storage chip is correspondingly connected to the first pad of the main control chip with the same pin configuration network through the metal lead.
8. The chip stacking architecture according to claim 1, characterized in that: The substrate and the memory chip, and the memory chip and the main control chip are bonded together by adhesive; wherein the adhesive comprises a wafer bonding film.
9. The chip stacking architecture according to claim 2, characterized in that: All rewired second pads are arranged on one side of the main control chip.
10. A storage device, characterized in that: The invention comprises a chip stacking architecture as claimed in any one of claims 1 to 9.