Chip packaging structure

Abstract

The utility model provides a chip packaging structure. The chip packaging structure comprises a chip, a rewiring layer and at least one component. The chip is provided with a front surface and a back surface which are opposite to each other, the front surface of the chip is provided with a plurality of bonding pads, the plurality of bonding pads comprise functional bonding pads, the front surface of the chip is provided with an open area, the bonding pads are not arranged in the open area, the rewiring layer is formed on the front surface of the chip and leads the functional bonding pads to the open area, and the component is mounted on the rewiring layer. And the component is electrically connected with the functional bonding pad through the rewiring layer. Therefore, when the component is installed on the chip, the electrical performance of the chip packaging structure can be improved, the design of the lead frame does not need to be changed, and the limitation on the installation position of the component is small.

Description

Technical Field

[0001] The utility model relates to the technical field of packaging, in particular to a chip packaging structure. Background Art

[0002] In some existing chip packaging structures, if the GPIO (General-purpose input / output) signal flips too many times, the chip's power supply voltage (Vcore) becomes unstable and drops below the standard value, causing the chip to fail to work. Usually, the chip itself cannot improve the above situation, and an equivalent solution is required by adding capacitors to the periphery.

[0003] In order to solve the problem that the power supply voltage of the chip is unstable and drops below the standard value after the GPIO signal flips too many times, an existing solution is to change the design of the lead frame, mount the capacitor on the lead frame, and electrically connect the capacitor to the power pad of the chip through the lead frame.

[0004] However, the above solution requires changing the lead frame design, that is, a special lead frame needs to be customized. The number and location of the capacitors to be installed are limited by the lead frame pin layout, and the installation of the capacitors will also affect the number of pins, so the scope of application is small. Therefore, how to install components on the periphery of the chip without changing the lead frame design and improve the electrical performance of the chip packaging structure needs to be solved urgently. Utility Model Content

[0005] One of the purposes of the utility model is to achieve the purpose of installing components on the periphery of a chip and improving the electrical performance of a chip packaging structure without changing the design of a lead frame and with less restrictions on the installation position of components.

[0006] In order to achieve the above-mentioned purpose, the utility model provides a chip packaging structure. The chip packaging structure includes a chip, a rewiring layer and at least one component. The chip has a front and a back side opposite to each other, the front side of the chip has a plurality of pads, the plurality of pads include functional pads, the front side of the chip has an open area, and the pads are not arranged in the open area. The rewiring layer is formed on the front side of the chip and leads the functional pads to the open area. The components are mounted on the rewiring layer and are electrically connected to the functional pads through the rewiring layer.

[0007] Optionally, the plurality of pads include at least two functional pads, the rewiring layer leads out at least two of the functional pads, and the components are mounted on the rewiring layer and interconnected with the two functional pads.

[0008] Optionally, two of the functional pads form a group, the plurality of pads include at least two groups of the functional pads, and at least two groups of the functional pads are interconnected with corresponding components.

[0009] Optionally, two functional pads adjacent to each other form a group, wherein the two functional pads have the same function.

[0010] Optionally, the chip packaging structure further includes a lead frame; one of the two functional pads interconnected with the components is electrically connected to the lead frame via a bonding wire.

[0011] Optionally, the lead frame includes a base island and pins, the back side of the chip is mounted on the base island, and the pins are arranged on the side of the base island.

[0012] Optionally, the chip packaging structure further includes a plastic package, which wraps the chip, the redistribution layer, the components and a portion of the lead frame, and a portion of the pins are exposed from the plastic package.

[0013] Optionally, the plurality of pads are distributed in the edge area of ​​the front side of the chip, and the open area is the central area of ​​the front side of the chip.

[0014] Optionally, the components are surface mounted on the rewiring layer by means of solder paste or other conductive materials printed by steel screen.

[0015] Optionally, the functional pad is a power pad, and the component is a capacitor.

[0016] In the chip packaging structure provided by the utility model, the front side of the chip has a plurality of pads, and the plurality of pads include functional pads. A rewiring layer is formed on the front side of the chip and the functional pads are led out to an empty area on the front side of the chip where no pads are arranged. Components are mounted on the rewiring layer and are electrically connected to the functional pads through the rewiring layer. By installing the components on the front side of the chip in this way, the electrical performance of the chip packaging structure can be improved. For example, installing capacitors on the chip improves the problem that the power supply voltage of the chip is unstable and drops below the standard value after the GPIO signal flips too many times. There is no need to change the design of the lead frame, that is, the original lead frame can be used, thereby not affecting the pin arrangement of the lead frame, and not reducing the number of pins. In addition, the number and position of components to be installed are less restricted, and can be flexibly designed without increasing the area of ​​the chip packaging structure. The method of installing components in the present application has a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic structural diagram of a chip packaging structure provided in one embodiment of the utility model.

[0018] Figure 2 A cross-sectional view of a chip packaging structure provided by an embodiment of the utility model.

[0019] Explanation of reference numerals: 100 - lead frame; 101 - base island; 102 - pin; 200 - chip; 201 - functional pad; 300 - redistribution layer; 400 - component; 500 - bonding wire; 600 - plastic package. DETAILED DESCRIPTION

[0020] The chip packaging structure proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0021] The terms used in the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. Unless otherwise defined in the present application document, the technical terms or scientific terms used in the present invention should be the usual meanings understood by people with general skills in the field to which the present invention belongs. Similar words such as "one" or "one" used in the present invention do not indicate a quantitative limitation, but rather indicate the existence of at least one. "Multiple" or "several" means two or more. Unless otherwise specified, similar words such as "upper" and / or "lower" are only for ease of explanation and are not limited to one position or one spatial orientation. Similar words such as "include" or "comprise" mean that the elements or structures appearing before "include" or "comprise" cover the elements or structures listed after "include" or "comprise" and their equivalents, and do not exclude other elements or structures.

[0022] Figure 1 A schematic structural diagram of a chip packaging structure provided in one embodiment of the utility model. Figure 2 This is a cross-sectional view of a chip packaging structure provided by an embodiment of the present invention. Figure 1 and Figure 2 As shown, the chip packaging structure includes a chip 200, a rewiring layer 300 and at least one component 400. The chip 200 has a front side and a back side opposite to each other. The front side of the chip 200 has a plurality of pads, and the plurality of pads include a functional pad 201. The front side of the chip 200 also has an open area, in which the pads are not arranged. The rewiring layer 300 is formed on the front side of the chip 200 and leads the functional pad 201 to the open area on the front side of the chip 200. The component 400 is mounted on the rewiring layer 300 and is electrically connected to the functional pad 201 through the rewiring layer 300.

[0023] The present application arranges a rewiring layer 300 on the front side of the chip 200 to lead the functional pad 201 out to the open area on the front side of the chip, so that the component 400 can be installed on the front side of the chip 200. In this way, there is no need to change the design of the lead frame, that is, the original lead frame can be used, which will not affect the pin arrangement of the lead frame, nor reduce the number of pins. In addition, the number and installation positions of the components 400 are less restricted, can be flexibly designed, and will not increase the area of ​​the chip packaging structure. The method of installing components in the present application has a wide range of applications.

[0024] Specifically, the chip 200 includes a substrate, and the material of the substrate includes silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V group compounds, etc. Exemplarily, the chip 200 can be a bare chip obtained by directly cutting a wafer.

[0025] like Figure 1 As shown, the front side of the chip 200 has a plurality of pads, and the plurality of pads include a functional pad 201. Exemplarily, the material of the pad includes but is not limited to metals such as copper, nickel, gold, silver or aluminum.

[0026] In one embodiment of the present application, the front side of the chip 200 may have a plurality of functional pads 201. The chip 200 may also include an internal metal layer located on the top surface of the substrate. In some embodiments, the functional pad 201 is a power pad, and the plurality of power pads may be interconnected through the internal metal layer, but is not limited thereto.

[0027] refer to Figure 1 As shown, multiple pads can be distributed in the edge area of ​​the front side of the chip 200, and the open area on the front side of the chip is the central area of ​​the front side of the chip, and the pads are not arranged in the open area. Exemplarily, the chip is a rectangular chip, and multiple pads are arranged along the four sides of the chip.

[0028] refer to Figure 1 and Figure 2 As shown, the rewiring layer 300 is formed on the front side of the chip 200 , and the rewiring layer 300 is directly connected to the functional pads 201 and leads the functional pads 201 to the open area on the front side of the chip 200 .

[0029] Exemplarily, the rewiring layer 300 may include a copper layer, a nickel layer, and a gold layer stacked in sequence, but is not limited thereto. The rewiring layer 300 may also be a material layer including one material, such as the rewiring layer 200 may only include a copper layer. The rewiring layer 300 may be formed by processes such as sputtering, electroplating, and etching, and the rewiring layer 300 may be formed on the front side of the wafer before the wafer is cut, and after the rewiring layer 300 is formed, the wafer is cut to obtain the chip 200 with the rewiring layer 300 formed on the front side.

[0030] The component 400 is mounted on the redistribution layer 300 and is electrically connected to the functional pad 201 through the redistribution layer 300 .

[0031] In one embodiment of the present application, the function pad 201 is a power pad, the component 400 is a capacitor, and the component 400 is interconnected with the function pad 201, specifically in series. The capacitor can store charge when the voltage is too high, and release the charge when the voltage drops, thereby smoothing the voltage fluctuation. When the GPIO signal is frequently flipped, a rapid current change will occur, resulting in power supply voltage fluctuations, and the capacitor can reduce these fluctuations and maintain a stable voltage by quickly storing and releasing charge. Therefore, the power pad is interconnected with the capacitor by using the rewiring layer 300 on the front of the chip, which can solve the problem that the power supply voltage of the chip is unstable and falls below the standard value after the GPIO signal flips too many times, and there is no need to change the design of the lead frame, and it will not affect the pin layout and pin number of the lead frame. The capacitor can be, but is not limited to, a ceramic capacitor.

[0032] The following description is made by taking the functional pad 201 as a power pad, the component 400 as a capacitor, and the component 400 being interconnected with the functional pad 201 as an example. However, in other embodiments of the present application, the functional pad 201 is not limited to a power pad, the component 400 is not limited to a capacitor, the component 400 may be a resistor or an inductor, etc., and the connection relationship between the component 400 and the functional pad 201 is not limited to a series connection.

[0033] In one embodiment of the present application, the multiple pads on the front side of the chip 200 include at least two functional pads 201, and the redistribution layer 300 leads at least two functional pads 201 to the open area on the front side of the chip. The components 400 are mounted on the redistribution layer 300 and interconnected with the two functional pads 201. For example, the components 400 are connected in series between the two functional pads 201.

[0034] Exemplary, reference Figure 1As shown, two functional pads 201 form a group, the front side of the chip 200 may have at least two groups of functional pads 201, the front side of the chip 200 may have more than two components 400, and at least two groups of functional pads 201 are interconnected with the corresponding components 400 through the rewiring layer 300. The rewiring layer 300 may only lead the functional pads 201 that need to connect the components to the open area to simplify the wiring of the rewiring layer 300.

[0035] In this embodiment, two function pads 201 close to each other are grouped together, or two function pads 201 close to each other are grouped together, so as to facilitate wiring of the wiring layer 300, but the utility model is not limited to this. In general, the functions of the two function pads 201 are the same.

[0036] It should be noted that, in some embodiments, the multiple functional pads 201 may include pads of different types, the multiple components 400 on the rewiring layer 300 may also be components of different types, and the different types of functional pads 201 may be electrically connected to the corresponding components 400 through the rewiring layer 300.

[0037] In this embodiment, the component 400 can be surface mounted (SMT) on the rewiring layer 300 by means of solder paste or other conductive materials printed by a steel screen.

[0038] refer to Figure 1 and Figure 2 As shown, the chip package structure further includes a lead frame 100, and the lead frame 100 may include a base island 101 and pins 102. The back of the chip 200 may be mounted on the base island 101, and the pins 102 are arranged on the side of the base island 101. The number of pins 102 may be multiple, and the multiple pins 102 are distributed along the four sides of the base island 101. For example, the lead frame 100 may have 64 pins 102, and the 64 pins 102 may be arranged on the base island 101. Figure 1 The numbers shown are 1 to 64.

[0039] refer to Figure 1 As shown, one of the two functional pads 201 interconnected with the component 400 can be electrically connected to the lead frame 100 through a bonding wire 500 to meet the conductive and / or power supply requirements and test requirements of the chip packaging structure. Specifically, one of the two functional pads 201 interconnected with the component 400 can be electrically connected to a pin 102 or a conductive rib of the lead frame 100 through a bonding wire 500.

[0040] Exemplarily, the material of the pin 102 may be metal, for example, one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni. The material of the base island 101 may be the same as or different from the material of the pin 102. In some embodiments, the material of the base island 101 is metal or insulating material, the metal may be one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni, the insulating material may be an inorganic insulating material or an organic insulating material, the inorganic insulating material may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, the organic insulating material may be epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin, or the organic insulating material may be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol.

[0041] like Figure 2 As shown, the chip packaging structure may further include a plastic package 600, wherein the plastic package 600 encapsulates the chip 200, the redistribution layer 300, the component 400, the bonding wire 500 and a portion of the lead frame 100, and a portion of the lead 102 is exposed from the plastic package 600. Exemplarily, the material of the plastic package 600 includes but is not limited to epoxy molding compound (EMC).

[0042] In the present application, a rewiring layer 300 can be formed on the front side of the wafer before cutting the wafer, and then the wafer is cut to obtain a chip 200 with a rewiring layer 300 formed on the front side. In the packaging process, after waferMount, the components 400 can be mounted on the rewiring layer 300, and then wafer Saw is performed, that is, only the SMT process is added between wafer Mount and wafer Saw, so the packaging process of the chip packaging structure of the present application can be compatible with the existing packaging process, the process is simple, and most packaging factories have SMT capabilities.

[0043] In the chip packaging structure provided by the utility model, the front side of the chip 200 has a plurality of pads, the plurality of pads include a functional pad 201, a rewiring layer 300 is formed on the front side of the chip 200 and the functional pad 201 is led out to an open area on the front side of the chip 200 where no pad is arranged, and the component 400 is mounted on the rewiring layer 300 and is electrically connected to the functional pad 201 through the rewiring layer 300. In this way, by arranging the rewiring layer 300 on the front side of the chip 200 and then mounting the component 400 on the rewiring layer 300, the component 400 and the functional pad 201 are connected. The electrical connection of the functional pad 201 can improve the electrical performance of the chip packaging structure. For example, it can improve the problem that the chip power supply voltage is unstable and drops below the standard value after the GPIO signal flips too many times. There is no need to change the design of the lead frame, that is, the original lead frame can be used, which will not affect the pin arrangement of the lead frame, nor will it reduce the number of pins. The number and installation positions of the components 400 are less restricted and can be flexibly designed without increasing the area of ​​the chip packaging structure. The method of installing components in the present application has a wide range of applications.

[0044] The above description is only a description of the preferred embodiment of the utility model, and is not any limitation on the scope of rights of the utility model. Any technical personnel in this field can make possible changes and modifications to the technical solution of the utility model by using the methods and technical contents disclosed above without departing from the spirit and scope of the utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the utility model without departing from the content of the technical solution of the utility model are within the protection scope of the technical solution of the utility model.

Claims

1. A chip packaging structure, characterized in that: include: A chip, wherein the chip has a front side and a back side opposite to each other, the front side of the chip has a plurality of pads, the plurality of pads include functional pads, the front side of the chip has an open area, and the pads are not arranged in the open area; a rewiring layer, the rewiring layer being formed on the front side of the chip and leading the functional pads out to the open area; as well as At least one component is mounted on the redistribution layer and is electrically connected to the functional pad through the redistribution layer.

2. The chip packaging structure according to claim 1, characterized in that: The plurality of pads include at least two functional pads, the rewiring layer leads out the at least two functional pads, and the components are mounted on the rewiring layer and interconnected with the two functional pads.

3. The chip packaging structure according to claim 2, characterized in that: The two functional pads form a group, the plurality of pads include at least two groups of functional pads, and the at least two groups of functional pads are interconnected with the corresponding components.

4. The chip packaging structure according to claim 3, characterized in that: Two functional pads adjacent to each other form a group, wherein the two functional pads have the same functions.

5. The chip packaging structure according to claim 2, characterized in that: It also includes a lead frame; one of the two functional pads interconnected with the components is electrically connected to the lead frame through a bonding wire.

6. The chip packaging structure according to claim 5, characterized in that: The lead frame includes a base island and pins. The back side of the chip is mounted on the base island, and the pins are arranged on the side of the base island.

7. The chip packaging structure according to claim 6, characterized in that: The chip packaging structure further includes a plastic package, which wraps the chip, the redistribution layer, the components and a portion of the lead frame, and a portion of the pins is exposed from the plastic package.

8. The chip packaging structure according to claim 1, characterized in that: The plurality of pads are distributed in the edge area of ​​the front side of the chip, and the open area is the central area of ​​the front side of the chip.

9. The chip packaging structure according to claim 1, characterized in that: The components are surface mounted on the rewiring layer through solder paste or other conductive materials printed by steel screen.

10. The chip packaging structure according to any one of claims 1 to 9, characterized in that: The functional pad is a power pad, and the component is a capacitor.

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