Control system and electronic equipment

Abstract

According to the control system and the electronic equipment provided by the embodiment of the utility model, the control system comprises a first embedded system and at least one second embedded system, the first embedded system comprises a first reset circuit and a first main control chip, and the first reset circuit is electrically connected with the first main control chip; the first main control chip is directly or indirectly electrically connected with the second embedded system; the first reset circuit is used for outputting a first startup reset signal to the first main control chip when the first embedded system is powered on so as to enable the first main control chip to be subjected to startup reset, and the first main control chip is used for controlling the second embedded system to be subjected to startup reset after the startup reset is completed. Due to the fact that the first embedded system is automatically powered on and reset immediately when powered on, the first embedded system controls the second embedded system to be powered on and reset after completing the power-on reset, the first embedded system and the second embedded system are started in sequence, and therefore stability and reliability of the control system are guaranteed.

Description

Technical Field

[0001] The utility model relates to the technical field of reset circuits, and more specifically, to a control system and an electronic device. Background Art

[0002] With the rapid development of electronic technology, embedded systems have been widely used in fields such as industrial automation and energy management. When an embedded system encounters abnormalities during operation, it is usually necessary to perform a reset operation to restart the entire system and restore it to its initial state for operation.

[0003] In some complex control systems, a single embedded system may not be able to meet all functional requirements, and multiple embedded systems need to work together. However, during reset control, if the reset control of multiple embedded systems is unreasonable, it may cause some embedded systems to fail to start, thereby affecting the stability and reliability of the entire control system operation. Summary of the Utility Model

[0004] The purpose of the utility model is to provide a control system and an electronic device, which can realize the sequential startup between the first embedded system and the second embedded system, thereby ensuring the stability and reliability of the control system.

[0005] The utility model provides a technical solution:

[0006] In a first aspect, the utility model provides a control system, including a first embedded system and at least one second embedded system. The first embedded system includes a first reset circuit and a first main control chip. The first reset circuit is electrically connected to the first main control chip, and the first main control chip is directly or indirectly electrically connected to the second embedded system;

[0007] The first reset circuit is used to output a first power-on reset signal to the first main control chip when the first embedded system is powered on, so that the first main control chip performs a power-on reset;

[0008] The first main control chip is used to control the second embedded system to perform a power-on reset after completing the power-on reset.

[0009] In an optional embodiment, the first reset circuit includes a switch control unit and a first switch unit. The switch control unit is electrically connected between a first power supply and the ground. The output end of the switch control unit is electrically connected to the first control end of the first switch unit. The first connection end of the first switch unit is electrically connected to the first main control chip and the first power supply, and the second connection end of the first switch unit is grounded;

[0010] The switch control unit is used to control the first switch unit to conduct when the first embedded system is powered on, so that the first switch unit outputs the first power-on reset signal to the first main control chip.

[0011] In an alternative embodiment, the switch control unit includes a first capacitor, a first resistor, and a second resistor. The first capacitor, the first resistor, and the second resistor are connected in series between the first power supply and the ground, and a first control end of the first switch unit is electrically connected between the first resistor and the second resistor.

[0012] In an alternative embodiment, the first embedded system further includes a watchdog reset circuit, and the watchdog reset circuit is electrically connected to the first main control chip;

[0013] The watchdog reset circuit is used to re-count when receiving a clear signal output by the first main control chip, and output an abnormal reset signal to the first main control chip when the count overflows, so that the first main control chip is reset.

[0014] In an alternative embodiment, the first main control chip is further used to control the second embedded system to be reset when the second embedded system runs abnormally.

[0015] In an alternative embodiment, there are one or more second embedded systems, and one or more of the second embedded systems are all directly electrically connected to the first main control chip;

[0016] The first main control chip is used to control each of the second embedded systems to be powered on and reset respectively after completing the power-on reset.

[0017] In an alternative embodiment, there are multiple second embedded systems, and the multiple second embedded systems are connected in series in sequence and then electrically connected to the first main control chip;

[0018] The first main control chip is used to control the second embedded system directly connected to the first main control chip to be powered on and reset after completing the power-on reset;

[0019] Each of the second embedded systems is used to control the next adjacent second embedded system to be powered on and reset after completing the power-on reset.

[0020] In an alternative embodiment, the second embedded system includes a second main control chip and a second reset circuit. The second main control chip is electrically connected to the second reset circuit, and the second reset circuit is electrically connected to the first main control chip or the second main control chip in the previous adjacent second embedded system;

[0021] The second reset circuit is configured to output a second power-on reset signal to the second main control chip in the second embedded system where the second reset circuit is located under the control of the first main control chip or the second main control chip in the previous adjacent second embedded system, so as to power-on and reset the second main control chip in the second embedded system where the second reset circuit is located.

[0022] In an optional embodiment, the second reset circuit includes a second switch unit; a second control end of the second switch unit is electrically connected to the first main control chip or the second main control chip in the previous adjacent second embedded system, a third connection end of the second switch unit is electrically connected to the second main control chip and a second power supply in the second embedded system where the second switch unit is located, and a fourth connection end of the second switch unit is grounded;

[0023] The second switch unit is configured to be turned on or off under the control of the first main control chip or the second main control chip in the previous adjacent second embedded system. When turned on, the second switch unit outputs the second power-on reset signal to the second main control chip in the second embedded system where the second reset circuit is located.

[0024] In a second aspect, the present invention provides an electronic device, including the control system according to any one of the foregoing embodiments.

[0025] The control system and the electronic device provided by the embodiments of the present invention. The control system includes a first embedded system and at least one second embedded system. The first embedded system includes a first reset circuit and a first main control chip. The first reset circuit is electrically connected to the first main control chip, and the first main control chip is directly or indirectly electrically connected to the second embedded system. The first reset circuit is configured to output a first power-on reset signal to the first main control chip when the first embedded system is powered on, so as to power-on and reset the first main control chip. The first main control chip is configured to control the second embedded system to power-on and reset after completing the power-on reset. Since the first embedded system automatically powers on and resets immediately when powered on, and then controls the second embedded system to power on and reset after the first embedded system completes the power-on reset, sequential startup between the first embedded system and the second embedded system is realized, thereby ensuring the stability and reliability of the control system. Description of the Drawings

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0027] Figure 1 Shows a schematic diagram of the control system provided by an embodiment of the present utility model;

[0028] Figure 2 Shows a connection schematic diagram of multiple second embedded systems in the control system provided by an embodiment of the present utility model;

[0029] Figure 3 Shows another connection schematic diagram of multiple second embedded systems in the control system provided by an embodiment of the present utility model;

[0030] Figure 4 Shows a schematic diagram of two second embedded systems connected in series in sequence and electrically connected to the first main control chip;

[0031] Figure 5 Shows a schematic diagram of the second reset circuit provided by an embodiment of the present utility model;

[0032] Figure 6 Shows a schematic diagram of the first reset circuit provided by an embodiment of the present utility model;

[0033] Figure 7 Shows another schematic diagram of the first reset circuit provided by an embodiment of the present utility model;

[0034] Figure 8 Shows another schematic diagram of the watchdog reset circuit provided by an embodiment of the present utility model;

[0035] Figure 9 Shows another schematic diagram of the control system provided by an embodiment of the present utility model.

[0036] Icons: 110 - First embedded system; 111 - First reset circuit; 112 - First main control chip; 113 - Watchdog reset circuit; 1111 - First switch unit; 1112 - Switch control unit; 120 - Second embedded system; 121 - Second reset circuit; 122 - Second main control chip; 130 - First power supply; 140 - Second power supply; 1211 - Second switch unit; 150 - SPI module. Detailed implementation manners

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present utility model clearer, the technical solutions in the embodiments of the present utility model will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are some but not all of the embodiments of the present utility model. Usually, the components of the embodiments of the present utility model described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0038] Accordingly, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0039] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0040] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the present invention is customarily placed during use, or the orientation or positional relationship commonly understood by those skilled in the art. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation on the present invention.

[0041] In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and should not be construed as indicating or implying relative importance.

[0042] In the description of the present invention, it should also be noted that unless otherwise clearly specified and defined, the terms "set", "installed", "connected", "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0043] Please refer to Figure 1 , Figure 1 which shows a schematic diagram of a control system provided by an embodiment of the present invention. The control system includes a first embedded system 110 and at least one second embedded system 120. The first embedded system includes a first reset circuit 111 and a first main control chip 112. The first reset circuit 111 is electrically connected to the first main control chip 112, and the first main control chip 112 is directly or indirectly electrically connected to the second embedded system 120.

[0044] The first reset circuit 111 is used to output a first power-on reset signal to the first main control chip 112 when the first embedded system 110 is powered on, so that the first main control chip 112 is reset when powered on.

[0045] Among them, the first main control chip 112 may include an MCU and a DSP (Digital Signal Processor). The functions of each second embedded system 120 can be set according to specific applications.

[0046] The first main control chip 112 is used to control the second embedded system 120 to be reset when the power-on reset is completed.

[0047] In some embodiments, at least one power-on reset time corresponding to the second embedded system 120 may be preset and stored in the first main control chip 112. After the first main control chip 112 completes the power-on reset, it can control the second embedded system 120 to be reset according to the stored power-on reset time corresponding to each second embedded system 120.

[0048] It can be understood that there are timing requirements for the power-on sequence of the first main control chip 112. By enabling the second embedded system 120 to be reset after the first main control chip 112 is reset when powered on, it is possible to avoid the problem that the second embedded system 120 reversely supplies power to the IO port of the first embedded system 110, resulting in the power-on timing of the first main control chip 112 not meeting the requirements and the first embedded system 110 being unable to start.

[0049] The control system provided by the embodiment of the present invention includes a first embedded system and at least one second embedded system. The first embedded system includes a first reset circuit and a first main control chip. The first reset circuit is electrically connected to the first main control chip, and the first main control chip is directly or indirectly electrically connected to the second embedded system. The first reset circuit is used to output a first power-on reset signal to the first main control chip when the first embedded system is powered on, so that the first main control chip is reset when powered on. The first main control chip is used to control the second embedded system to be reset when the power-on reset is completed. Since the first embedded system is automatically reset immediately when powered on, and the second embedded system is controlled to be reset after the first embedded system completes the power-on reset, sequential startup between the first embedded system and the second embedded system is achieved, thereby ensuring the stability and reliability of the control system.

[0050] In some embodiments, as Figure 2 shown, the second embedded system 120 is one or more, and one or more second embedded systems 120 are all directly electrically connected to the first main control chip 112.

[0051] The first main control chip 112 is used to control the power-on reset of each second embedded system 120 respectively after completing the power-on reset of itself.

[0052] In some embodiments, the first main control chip 112 stores the power-on reset times corresponding to each second embedded system 120. After completing the power-on reset of itself, the first main control chip 112 performs the power-on reset of each second embedded system 120 according to the corresponding power-on reset times of each second embedded system 120.

[0053] Among them, the power-on reset times corresponding to each second embedded system 120 can be the same; the power-on reset times corresponding to each second embedded system 120 can be partially the same; the power-on reset times corresponding to each second embedded system 120 can also be all different. Specifically, the power-on reset times corresponding to each second embedded system 120 can be set according to the functions implemented by each second embedded system 120.

[0054] In some embodiments, as Figure 3 shown, there are multiple second embedded systems 120, and the multiple second embedded systems 120 are connected in series in sequence and electrically connected to the first main control chip 112.

[0055] The first main control chip 112 is used to control the power-on reset of the second embedded system 120 directly connected to the first main control chip 112 after completing the power-on reset of itself.

[0056] Each second embedded system 120 is used to control the power-on reset of the next adjacent second embedded system 120 after completing the power-on reset of itself.

[0057] In some embodiments, the power-on reset time of the next adjacent second embedded system 120 can be set and stored in each second embedded system 120. Each second embedded system 120 can control the power-on reset of the next adjacent second embedded system 120 according to the stored power-on reset time of the next adjacent second embedded system 120 after completing the reset.

[0058] The second embedded system 120 includes a second main control chip and a second reset circuit. The second main control chip is electrically connected to the second reset circuit, and the second reset circuit is electrically connected to the first main control chip or the second main control chip in the previous adjacent second embedded system 120.

[0059] As Figure 4 , Figure 4Taking the example that two second embedded systems 120 included in the control system are connected in series in sequence and then electrically connected to the first main control chip 1111. The second embedded system 120A includes a second main control chip 122A and a second reset circuit 121A. The second main control chip 122A is electrically connected to the second reset circuit 121A. The second embedded system 120B includes a second main control chip 122B and a second reset circuit 121B. The second main control chip 122B is electrically connected to the second reset 121B circuit. The second reset circuit 121A is electrically connected to the first main control chip 112. The second reset circuit 121B is electrically connected to the second main control chip 122A in the previous adjacent second embedded system 120A.

[0060] The second reset circuit 121 is configured to output a second power-on reset signal to the second main control chip 122 in the second embedded system 120 where the second reset circuit 121 is located under the control of the first main control chip 112 or the second main control chip 122 in the previous adjacent second embedded system 120, so that the second main control chip 122 in the second embedded system 120 where the second reset circuit 121 is located performs a power-on reset.

[0061] As Figure 4 shown, the second reset circuit 121A is configured to output a second power-on reset signal to the second main control chip 122A in the second embedded system 120A where the second reset circuit 121A is located under the control of the first main control chip 112, so that the second main control chip 122A in the second embedded system 120A where the second reset circuit 121A is located performs a power-on reset; the second reset circuit 121B is configured to output a second power-on reset signal to the second main control chip 122B in the second embedded system 120B where the second reset circuit 121B is located under the control of the first main control chip 112, so that the second main control chip 122B in the second embedded system 120B where the second reset circuit 121B is located performs a reset.

[0062] As Figure 5 shown, the second reset circuit 121 includes a second switch unit 1211. The second control end A2 of the second switch unit 1211 is electrically connected to the first main control chip 112 or the second main control chip 122 in the previous adjacent second embedded system 120. The third connection end B3 of the second switch unit 1211 is electrically connected to the second main control chip 122 and the second power supply 140 in the second embedded system 120 where the second switch unit 1211 is located. The fourth connection end B4 of the second switch unit 12111 is grounded.

[0063] The second switch unit 1211 can be used to conduct or disconnect under the control of the first main control chip 112 or the second main control chip 122 in the adjacent previous second embedded system 120. When conducting, it outputs a second power-on reset signal to the second main control chip 122 in the second embedded system 120 where the second reset circuit 121 is located.

[0064] In some embodiments, the second switch 1211 may include an NMOS transistor and a triode. Specifically, the second switch unit 1211 may be an NPN-type triode. If the second switch unit 1211 is an NPN-type triode, the second control terminal A2 of the second switch unit 1211 is the base of the NPN-type triode, the third connection terminal B3 of the second switch unit 1211 is the collector of the NPN-type triode, and the fourth connection terminal B4 of the second switch unit 12111 is the emitter of the NPN-type triode.

[0065] As Figure 5 shown, the second reset circuit 121 further includes a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The fourth resistor R4 is electrically connected between the second power supply 140 and the third connection terminal B3 of the second switch unit 1211. One end of the fifth resistor R5 is electrically connected to the first main control chip 112 or the second main control chip 122 in the adjacent previous second embedded system 120, and the other end of the fifth resistor R5 is electrically connected to the second control terminal A2 of the second switch unit 1211. One end of the sixth resistor R6 is electrically connected between the other end of the fifth resistor R5 and the second control terminal A2 of the second switch unit 1211, and the other end of the sixth resistor R6 is grounded.

[0066] It should be noted that when the second control terminal A2 of the second switch unit 1211 receives the reset signal sent by the first main control chip 112 or the second main control chip 122 in the adjacent previous second embedded system 120, the third connection terminal B3 and the fourth connection terminal B4 of the second switch unit 1211 are connected, pulling down the reset terminal level of the second main control chip 122 in the second embedded system 120 where the second switch unit 1211 is located, and the second main control chip 122 is reset.

[0067] The fifth resistor R5 and the sixth resistor R6 are voltage-dividing resistors. The fifth resistor R5 and the sixth resistor R6 can provide a stable voltage for the second switch unit 1211 and can also limit the current to prevent the current flowing through the second control terminal A2 of the second switch unit 1211 from being too large and damaging the second switch unit 1211.

[0068] The fourth resistor R4 is a pull-up resistor. When the second power supply 140 starts up, the voltage may be unstable. The fourth resistor R4 can ensure that the reset terminal of the second main control chip 122 remains at a high level before the second power supply 140 stabilizes, preventing the second main control chip 122 from starting up when the power supply is unstable.

[0069] To ensure stable power-on reset, as Figure 6 shown, the first reset circuit 111 includes a switch control unit 1112 and a first switch unit 1111. The switch control unit 1112 is electrically connected between the first power supply 130 and the ground. The output terminal of the switch control unit 1112 is electrically connected to the first control terminal A1 of the first switch unit 1111. The first connection terminal B1 of the first switch unit 1111 is electrically connected to the first main control chip 112 and the first power supply 130. The second connection terminal B2 of the first switch unit 1111 is grounded.

[0070] The switch control unit 1112 is used to control the first switch unit 1111 to conduct when the first embedded system 110 is powered on, so that the first switch unit 1111 outputs a first power-on reset signal to the first main control chip 112.

[0071] Among them, the first switch unit 1111 may include an NMOS transistor and a triode. Specifically, the first switch unit 1111 may be an NPN-type triode. If the first switch unit 1111 is an NPN-type triode, the first control terminal A1 of the first switch unit 1111 is the base of the NPN-type triode, the first connection terminal B1 of the first switch unit 1111 is the collector of the NPN-type triode, and the second connection terminal B2 of the first switch unit 1111 is the emitter of the NPN-type triode.

[0072] As Figure 7 shown, taking the first switch unit 1111 as an NPN-type triode as an example, the first switch control unit 1112 includes a first capacitor C1, a first resistor R1, and a second resistor R2. The first capacitor C1, the first resistor R1, and the second resistor R2 are connected in series between the first power supply 130 and the ground. The first control terminal A1 of the first switch unit 1111 is electrically connected between the first resistor R1 and the second resistor R2.

[0073] It should be noted that when the first embedded system 110 is powered on, the first power supply 130 charges the first capacitor C1. The charges on the two plates of the first capacitor C1 are not equal, and the first capacitor C1 is equivalent to a short - circuit state. At this time, the voltage output by the first power supply 130 can pass through the first capacitor C1, and after being divided by the first resistor R1 and the second resistor R2, it flows to the base of the NPN - type triode (the first control terminal A1 of the first switching unit 1111). When the voltage at the base of the NPN - type triode (the first control terminal A1 of the first switching unit 1111) is greater than the forward - conduction voltage of the base of the NPN - type triode (the first control terminal A1 of the first switching unit 1111), the collector of the NPN - type triode (the first connection terminal B1 of the first switching unit 1111) is conducted with the emitter of the NPN - type triode (the second connection B2 of the first switching unit 1111), pulling down the reset - terminal level of the first main control chip 112, and the first main control chip 112 performs a power - on reset. In this way, a capacitor - conduction phenomenon will occur in the first capacitor C1 instantaneously at power - on. A voltage value will flow into the base of the triode, and the triode will surely conduct. After the triode conducts, the first main control chip 112 will surely be reset, so that the power - on reset of the first main control chip 112 can be stabilized.

[0074] It can be understood that since the first power supply 130 charges the first capacitor C1, the charges on the two plates of the first capacitor C1 gradually become equal, and the voltage at the base of the NPN - type triode (the first control terminal A1 of the first switching unit 1111) gradually becomes smaller. After a period of time, the voltage at the base of the NPN - type triode (the first control terminal A1 of the first switching unit 1111) is less than the forward - conduction voltage of the NPN - type triode (the first switching unit 1111), and the NPN - type triode (the first switching unit 1111) turns off, causing the collector of the NPN - type triode (the first connection terminal B1 of the first switching unit 1111) to return to a high level. Thus, the first main control chip 112 jumps out of the reset state. Therefore, the power - on reset time of the first main control chip 112 is determined by the charging time of the first capacitor C1, and the charging time of the first capacitor C1 is the product of the capacitance value of the first capacitor C1 and the resistance value of the first resistor R1.

[0075] If it is necessary to adjust the power - on reset time of the first main control chip 112, only the capacitance value of the first capacitor C1 and the resistance value of the first resistor R1 need to be adjusted.

[0076] In some embodiments, by appropriately adjusting the capacitance value of the first capacitor C1 and the resistance value of the first resistor R1, the conduction time of the first switching unit 1111 can be made long enough, so that the reset - terminal of the first main control chip 112 can maintain a low level for a long enough time, thereby achieving stable reset of the first main control chip 112.

[0077] The first reset circuit 111 further includes a third resistor R3 and a second capacitor C2. The third resistor R3 is electrically connected between the first power supply 130 and the first connection end of the first switch unit 1111. One end of the second capacitor C2 is electrically connected to the first connection end of the first switch unit 1111, and the other end of the second capacitor C2 is grounded.

[0078] To ensure the stable operation of the first main control chip 112, as Figure 8 shown, the first embedded system 110 further includes a watchdog reset circuit 113, and the watchdog reset circuit 113 is electrically connected to the first main control chip.

[0079] The watchdog reset circuit 113 is used to re - count when receiving a clear signal output by the first main control chip 112, and output an abnormal reset signal to the first main control chip 112 when the count overflows, so as to reset the first main control chip 112.

[0080] The watchdog reset circuit 113 can be a watchdog chip. The watchdog chip can include a timer chip and a chip with a timing function, etc. Specifically, the watchdog chip can include a CN8255 chip.

[0081] The input terminal (WDI) of the watchdog chip is electrically connected to the reset signal output terminal of the first main control chip 112, the output terminal (RST) of the watchdog chip is electrically connected to the reset terminal of the first main control chip 112, and the power input terminal (VCC) of the watchdog chip is electrically connected to the second power supply. The watchdog reset circuit 113 receives the clear signal output by the first main control chip 112 through the input terminal (WDI) of the watchdog chip, and outputs an abnormal reset signal to the first main control chip 112 through the output terminal (RST) of the watchdog chip.

[0082] It should be noted that the watchdog reset circuit 113 starts counting after the control system is powered on or reset. During the normal operation of the program in the first main control chip 112, before the timer counts to zero, it is necessary to reset the timer through the clear signal output by the first main control chip 112. If the program in the first main control chip 112 cannot output a clear signal due to an error or an infinite loop, after the timer counts to zero, the watchdog chip will output a reset signal to the reset terminal of the first main control chip 112, forcing the first main control chip 112 to reset, so as to restore the normal operation of the first main control chip 112, thereby enhancing the stability and reliability of the first main control chip 112.

[0083] As Figure 9As shown in the figure, taking the control system including a second embedded system as an example, the first main control chip 112 can be electrically connected to the second embedded system 120 through an SPI (Serial Peripheral Interface) module 150. The first main control chip 112 can receive data sent by the second embedded system 120 through the SPI module 150.

[0084] In some embodiments, the first main control chip 112 is further configured to control the second embedded system 120 to reset in the case where the second embedded system 120 runs abnormally.

[0085] As Figure 2 shown, there are one or more second embedded systems 120, and one or more second embedded systems 120 are all directly electrically connected to the first main control chip 112. One or more second embedded systems 120 can transmit data to the first main control chip 112 through corresponding SPI modules, and the first main control chip 112 processes the received data.

[0086] As Figure 4 shown, the second embedded system 120 includes a second embedded system 120A and a second embedded system 120B. The second embedded system 120A and the second embedded system 120B are connected in series in sequence and then electrically connected to the first main control chip 112. SPI modules are connected between the second embedded system 120A and the second embedded system 120B and between the first main control chip 112 and the second embedded system 120A. The second embedded system 120B transmits data to the second embedded system 120A through the SPI module. The second embedded system 120A can send both the data collected by itself and the data sent by the second embedded system 120B to the first main control chip 112 through the SPI module, and the first main control chip 112 can process the data sent by the second embedded system 120A and the data sent by the second embedded system 120B.

[0087] It should be noted that if the abnormality that occurs in the second embedded system 120 does not affect the key parts of the SPI communication, such as the clock signal, data line, and chip select signal, and the second embedded system 120 has a certain error detection and recovery mechanism, the second main control chip 122 can still send data. The first main control chip 112 can analyze and judge whether the second main control chip 122 runs abnormally based on the data. If it is judged that the second main control chip 122 runs abnormally, the first main control chip 112 can reset the second main control chip 122 of the second embedded system 120 with abnormal operation through the second reset circuit 121 of the second embedded system 120 with abnormal operation.

[0088] If an exception occurring in the second embedded system 120 affects a critical part of the SPI communication, when the first main control chip 112 fails to receive data sent by the second main control chip 122, it determines that the second main control chip 122 is operating abnormally. The first main control chip 112 can reset the second main control chip 122 of the second embedded system 120 with an abnormal operation through the second reset circuit 121 of the second embedded system 120 with an abnormal operation.

[0089] As Figure 9 shown, the first main control chip 112 can be a GD32F103CBT6 chip, and the second main control chip 122 can be an RN7326E chip. The power input terminals (AVCC1, DVCC) of the second main control chip 122 and the power input terminal (+3.3v_ME) of the SPI module 150 are both electrically connected to the output terminal (VOUT_1) of the second power supply 140. The reset terminal (NRST) of the first main control chip 112 is electrically connected to the first connection terminal B1 of the first switch unit 1111 and the output terminal of the watchdog reset circuit 113 respectively. The reset control terminal (PB3) of the first main control chip 112 is electrically connected to the second control terminal A2 of the second switch unit 1211. The third connection terminal B3 of the second switch unit 1211 is electrically connected to the reset terminal (RSTN) of the second main control chip 122. The SPI communication terminals (SPI1_NSS, SPI1_SCK, SPI1_MOSI, SPI1_MISO) of the first main control chip 112 are correspondingly electrically connected to the SPI communication terminals (SPIS_SCSN, SPIS_SCLK, SPIS_SDI, SPIS_SDO) of the second main control chip 122 through the SPI module 150.

[0090] The embodiment of the present invention further provides an electronic device, and the electronic device may include the above control system.

[0091] In some embodiments, the electronic device may include a smart meter, an industrial controller, etc.

[0092] Taking the electronic device as a smart meter as an example, the second embedded system 120 can continuously monitor and collect the operation data of the meter, and then transmit the data to the first embedded system 110. After receiving the data, the first embedded system 110 can process the data, such as data verification, formatting, storage, etc. The first embedded system 110 can also execute specific functions according to the collected data, such as generating reports, sending alerts, executing remote control commands, etc. The first embedded system 110 can also display the data and reports, etc.

[0093] The control system and the electronic device provided by the embodiment of the present utility model, the control system includes a first embedded system and at least one second embedded system, the first embedded system includes a first reset circuit and a first main control chip, the first reset circuit is electrically connected to the first main control chip, and the first main control chip is directly or indirectly electrically connected to the second embedded system; the first reset circuit is configured to output a first power-on reset signal to the first main control chip when the first embedded system is powered on, so that the first main control chip performs a power-on reset, and the first main control chip is configured to control the second embedded system to perform a power-on reset after completing the power-on reset. Since the first embedded system automatically performs a power-on reset immediately when powered on, and controls the second embedded system to perform a power-on reset after the first embedded system completes the power-on reset, sequential startup between the first embedded system and the second embedded system is achieved, thereby ensuring the stability and reliability of the control system.

[0094] The above are only the preferred embodiments of the present utility model and are not intended to limit the present utility model. For those skilled in the art, the present utility model can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. A control system, characterized in that: It includes a first embedded system and at least one second embedded system, wherein the first embedded system includes a first reset circuit and a first main control chip, the first reset circuit is electrically connected to the first main control chip, and the first main control chip is directly or indirectly electrically connected to the second embedded system; The first reset circuit is used to output a first power-on reset signal to the first main control chip when the first embedded system is powered on, so as to power on and reset the first main control chip; The first main control chip is used to control the second embedded system to power on and reset after completing the power on and reset.

2. The control system according to claim 1, characterized in that: The first reset circuit includes a switch control unit and a first switch unit, the switch control unit is electrically connected between a first power supply and ground, an output end of the switch control unit is electrically connected to a first control end of the first switch unit, a first connection end of the first switch unit is electrically connected to the first main control chip and the first power supply, and a second connection end of the first switch unit is grounded; The switch control unit is used to control the first switch unit to be turned on when the first embedded system is powered on, so that the first switch unit outputs the first power-on reset signal to the first main control chip.

3. The control system according to claim 2, characterized in that: The switch control unit includes a first capacitor, a first resistor and a second resistor, the first capacitor, the first resistor and the second resistor are connected in series between the first power supply and the ground, and the first control end of the first switch unit is electrically connected between the first resistor and the second resistor.

4. The control system according to claim 1, characterized in that: The first embedded system further includes a watchdog reset circuit, and the watchdog reset circuit is electrically connected to the first main control chip; The watchdog reset circuit is used to re-count when receiving a reset signal output by the first master control chip, and output an abnormal reset signal to the first master control chip when the count overflows, so as to reset the first master control chip.

5. The control system according to claim 1, characterized in that: The first main control chip is also used to control the second embedded system to reset when the second embedded system runs abnormally.

6. The control system according to claim 1, characterized in that: There are one or more second embedded systems, and the one or more second embedded systems are directly electrically connected to the first main control chip; The first main control chip is used to control the power-on reset of each of the second embedded systems after completing the power-on reset.

7. The control system according to claim 1, characterized in that: There are multiple second embedded systems, and the multiple second embedded systems are connected in series in sequence and then electrically connected to the first main control chip; The first main control chip is used to control the power-on reset of the second embedded system directly connected to the first main control chip after completing the power-on reset; Each of the second embedded systems is used for controlling the next adjacent second embedded system to power on and reset after completing the power-on and reset.

8. The control system according to any one of claims 1 to 7, characterized in that: The second embedded system comprises a second main control chip and a second reset circuit, the second main control chip is electrically connected to the second reset circuit, and the second reset circuit is electrically connected to the first main control chip or the second main control chip in the previous adjacent second embedded system; The second reset circuit is used to output a second power-on reset signal to the second master control chip in the second embedded system where the second reset circuit is located under the control of the first master control chip or the second master control chip in the adjacent previous second embedded system, so as to power on and reset the second master control chip in the second embedded system where the second reset circuit is located.

9. The control system according to claim 8, characterized in that: The second reset circuit includes a second switch unit; a second control end of the second switch unit is electrically connected to the first main control chip or the second main control chip in the adjacent second embedded system, a third connection end of the second switch unit is electrically connected to the second main control chip and the second power supply in the second embedded system where the second switch unit is located, and a fourth connection end of the second switch unit is grounded; The second switch unit is used to turn on or off under the control of the first main control chip or the second main control chip in the adjacent previous second embedded system. When turned on, it outputs the second power-on reset signal to the second main control chip in the second embedded system where the second reset circuit is located.

10. An electronic device, characterized in that: A control system comprising any one of claims 1 to 9.

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