Groove type power MOS device
By designing the trench-type structure and specific doping regions in silicon carbide MOS devices, the device's response speed and switching capabilities are improved, and the voltage withstandability is improved, solving the problem of slow response speed of existing devices.
Patent Information
- Application Number
- CN202421660753.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-12
- Publication Date
- 2025-06-10
- Estimated Expiration
- 2034-07-12
AI Technical Summary
The existing silicon carbide MOS devices have slow response speed, resulting in the need to improve switching capabilities.
A trench power MOS device is designed, adopting an N-type heavily doped silicon carbide substrate and an N-type epitaxial layer, and introducing a P-type well region, a trench, an N-type heavily doped source region and a gate column in the device single cell. The gate column includes a wide sub-post and a narrow sub-post, and a silicon dioxide layer and a P-type heavily doped region are provided on its side surface.
By reducing the gate capacitance of the device, the response speed of the MOS device is improved, the switching capability is improved, and the overall voltage withstandability is improved.
Smart Images
Figure CN222967302U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor devices, in particular to a trench-type power MOS device. Background Art
[0002] The metal-oxide-semiconductor (MOS) power device made of silicon carbide material can perform fast switching while withstanding high voltage. In recent years, due to the development of power electronics technology, the silicon carbide MOS device has brought a profound impact on the high efficiency and miniaturization of power electronic devices. The response speed of the existing silicon carbide MOS device needs to be improved, and how to improve the switching ability of the device has become the direction of the efforts of those skilled in the art. Summary of the Utility Model
[0003] The purpose of the utility model is to provide a trench-type power MOS device, which improves the response speed of the MOS device, thereby improving the switching ability of the device and also enhancing the overall voltage withstand ability of the device.
[0004] To achieve the above object, the technical solution adopted by the utility model is: a trench-type power MOS device, comprising: an N-type heavily doped silicon carbide substrate and an N-type epitaxial layer located on the N-type heavily doped silicon carbide substrate, at least two device cells are included on the N-type epitaxial layer, and a lower metal electrode layer is provided on the surface of the N-type heavily doped silicon carbide substrate opposite to the N-type epitaxial layer;
[0005] Each device cell further includes: a P-type well region located in the upper part of the N-type epitaxial layer and a trench located in the P-type well region, the trench extends into the N-type epitaxial layer, an N-type heavily doped source region is provided in the upper part of the P-type well region and around the trench, a gate column is provided in the trench, the gate column includes a wide sub-column located in the upper part and a narrow sub-column located below the wide sub-column, a silicon dioxide layer is provided between the side surface of the wide sub-column of the gate column and the inner wall of the upper part of the trench, a P-type heavily doped region is provided between the side surface of the narrow sub-column of the gate column and the inner wall of the lower part of the trench, and the upper surface of the P-type heavily doped region is located below the lower surface of the P-type well region;
[0006] An N-type heavily doped deep implantation part is provided in the N-type epitaxial layer between the P-type well regions of adjacent device cells, the upper end of the N-type heavily doped deep implantation part is flush with the N-type epitaxial layer, and the lower end of the N-type heavily doped deep implantation part extends to the lower part of the N-type epitaxial layer;
[0007] An insulating dielectric layer is located above the trench and covers the gate column, and an upper metal electrode layer is located above the insulating dielectric layer and the N-type heavily doped source region and is in contact with the upper surfaces of the insulating dielectric layer and the N-type heavily doped source region respectively.
[0008] The further improved solutions in the above technical solutions are as follows:
[0009] 1. In the above solution, the height ratio of the wide sub-column to the narrow sub-column is 10:2 to 4.
[0010] 2. In the above solution, the bottom of the gate column in the trench is located below the P-type well region, and this gate column extends to the middle of the N-type epitaxial layer.
[0011] 3. In the above solution, the lower end of the N-type heavily doped deep implantation part is lower than the bottom of the trench.
[0012] 4. In the above solution, the upper width of the N-type heavily doped deep implantation part is greater than the lower width.
[0013] Due to the application of the above technical solutions, the present utility model has the following advantages compared with the prior art:
[0014] 1. For the trench-type power MOS device of the present utility model, there is a gate column in the trench. This gate column includes a wide sub-column at the upper part and a narrow sub-column below the wide sub-column. There is a silicon dioxide layer between the side surface of the wide sub-column of the gate column and the upper inner wall of the trench, and there is a P-type heavily doped region between the side surface of the narrow sub-column of the gate column and the lower inner wall of the trench. The upper surface of the P-type heavily doped region is located below the lower surface of the P-type well region, reducing the gate capacitance of the device, improving the response speed of the MOS device, and thus improving the switching ability of the device.
[0015] 2. For the silicon carbide MOS device of the present utility model, there is an N-type heavily doped deep implantation part in the N-type epitaxial layer between the P-type well regions of adjacent device unit cells. The upper end of this N-type heavily doped deep implantation part is flush with the N-type epitaxial layer, and the lower end of the N-type heavily doped deep implantation part extends to the lower part of the N-type epitaxial layer, effectively and uniformly dispersing the electric field intensity, reducing the probability of occurrence of the breakdown effect, and improving the overall breakdown voltage ability of the device. Description of the Drawings
[0016] Attached Figure 1 is a schematic structural diagram of the trench-type power MOS device of the present utility model.
[0017] In the above drawings: 1. N-type heavily doped silicon carbide substrate; 2. N-type epitaxial layer; 3. Lower metal electrode layer; 4. P-type well region; 5. Trench; 6. Gate column; 61. Wide sub-column; 62. Narrow sub-column; 7. Silicon dioxide layer; 8. N-type heavily doped source region; 9. Insulating dielectric layer; 10. Upper metal electrode layer; 11. P-type heavily doped region; 12. N-type heavily doped deep implantation part; 13. Device unit cell. Detailed Embodiments
[0018] The present patent can be further clearly understood through the following specific embodiments given, but they do not limit the present patent.
[0019] Embodiment 1: A trench-type power MOS device includes: an N-type heavily doped silicon carbide substrate 1 and an N-type epitaxial layer 2 located on the N-type heavily doped silicon carbide substrate 1. The N-type epitaxial layer 2 includes at least two device cells 13. The surface of the N-type heavily doped silicon carbide substrate 1 opposite to the N-type epitaxial layer 2 has a lower metal electrode layer 3;
[0020] Each device cell 13 further includes: a P-type well region 4 located in the upper part of the N-type epitaxial layer 2 and a trench 5 located in the P-type well region 4. This trench 5 extends into the N-type epitaxial layer 2. An N-type heavily doped source region 8 is located in the upper part of the P-type well region 4 and around the trench 5. A gate column 6 is located in the trench 5. This gate column 6 includes a wide sub-column 61 located in the upper part and a narrow sub-column 62 located below the wide sub-column 61. There is a silicon dioxide layer 7 between the side surface of the wide sub-column 61 of the gate column 6 and the upper inner wall of the trench 5. There is a P-type heavily doped region 11 between the side surface of the narrow sub-column 62 of the gate column 6 and the lower inner wall of the trench 5. The upper surface of the P-type heavily doped region 11 is located below the lower surface of the P-type well region 4;
[0021] An N-type heavily doped deep implantation portion 12) is located in the N-type epitaxial layer 2 between the P-type well regions 4 of adjacent device cells 13. The upper end of this N-type heavily doped deep implantation portion 12) is flush with the N-type epitaxial layer 2, and the lower end of the N-type heavily doped deep implantation portion 12) extends to the lower part of the N-type epitaxial layer 2;
[0022] An insulating dielectric layer 9 is located above the trench 5 and covers the gate column 6. An upper metal electrode layer 10 is located above the insulating dielectric layer 9 and the N-type heavily doped source region 8 and is in contact with the upper surfaces of the insulating dielectric layer 9 and the N-type heavily doped source region 8 respectively.
[0023] The height ratio of the above-mentioned wide sub-column 61 to the narrow sub-column 62 is 10:2.5.
[0024] The lower end of the above-mentioned N-type heavily doped deep implantation portion 12) is lower than the bottom of the trench 5.
[0025] The upper width of the above-mentioned N-type heavily doped deep implantation portion 12) is greater than the lower width.
[0026] Embodiment 2: A trench-type power MOS device includes: an N-type heavily doped silicon carbide substrate 1 and an N-type epitaxial layer 2 located on the N-type heavily doped silicon carbide substrate 1. The N-type epitaxial layer 2 includes at least two device cells 13. The surface of the N-type heavily doped silicon carbide substrate 1 opposite to the N-type epitaxial layer 2 has a lower metal electrode layer 3;
[0027] The device unit cell 13 further includes: a P-type well region 4 located above the N-type epitaxial layer 2 and a trench 5 located within the P-type well region 4, the trench 5 extending into the N-type epitaxial layer 2. The N-type heavily doped source region 8 is provided within the upper part of the P-type well region 4 and around the trench 5. A gate pillar 6 is provided within the trench 5, the gate pillar 6 including a wide sub-pillar 61 at the upper part and a narrow sub-pillar 62 below the wide sub-pillar 61. A silicon dioxide layer 7 is provided between the side surface of the wide sub-pillar 61 of the gate pillar 6 and the upper inner wall of the trench 5. A P-type heavily doped region 11 is provided between the side surface of the narrow sub-pillar 62 of the gate pillar 6 and the lower inner wall of the trench 5, the upper surface of the P-type heavily doped region 11 being located below the lower surface of the P-type well region 4;
[0028] An N-type heavily doped deep implant region 12 is provided within the N-type epitaxial layer 2 between the P-type well regions 4 of adjacent device unit cells 13. The upper end of the N-type heavily doped deep implant region 12 is flush with the N-type epitaxial layer 2, and the lower end of the N-type heavily doped deep implant region 12 extends to the lower part of the N-type epitaxial layer 2;
[0029] An insulating dielectric layer 9 is located above the trench 5 and covers the gate pillar 6, and an upper metal electrode layer 10 is located above the insulating dielectric layer 9 and the N-type heavily doped source region 8 and is in contact with the upper surfaces of the insulating dielectric layer 9 and the N-type heavily doped source region 8 respectively.
[0030] The height ratio of the above-mentioned wide sub-pillar 61 to the narrow sub-pillar 62 is 10:3.
[0031] The bottom of the gate pillar 6 within the above-mentioned trench 5 is located below the P-type well region 4, and the gate pillar 6 extends to the middle of the N-type epitaxial layer 2.
[0032] The lower end of the above-mentioned N-type heavily doped deep implant region 12 is lower than the bottom of the trench 5.
[0033] The upper width of the above-mentioned N-type heavily doped deep implant region 12 is greater than the lower width.
[0034] When the above-mentioned trench-type power MOS device is adopted, its gate capacitance of the device is reduced, the response speed of the MOS device is improved, thereby improving the switching ability of the device. Moreover, an N-type heavily doped deep implant region 12 is provided within the N-type epitaxial layer 2 between the P-type well regions 4 of adjacent device unit cells. The upper end of the N-type heavily doped deep implant region 12 is flush with the N-type epitaxial layer 2, and the lower end of the N-type heavily doped deep implant region 12 extends to the lower part of the N-type epitaxial layer 2, effectively and uniformly dispersing the electric field intensity, reducing the occurrence probability of the breakdown effect, and improving the overall breakdown voltage ability of the device.
[0035] The above embodiments are only used to illustrate the technical concept and features of the present utility model. The purpose is to enable those skilled in the art to understand the content of the present utility model and implement it accordingly, and it should not be used to limit the protection scope of the present utility model. Any equivalent changes or modifications made according to the spirit of the present utility model should be covered within the protection scope of the present utility model.
Claims
1. A trench power MOS device, characterized in that: include: An N-type heavily doped silicon carbide substrate (1) and an N-type epitaxial layer (2) located on the N-type heavily doped silicon carbide substrate (1), wherein the N-type epitaxial layer (2) comprises at least two device cells (13), and the surface of the N-type heavily doped silicon carbide substrate (1) opposite to the N-type epitaxial layer (2) has a lower metal electrode layer (3); The device unit cell (13) further comprises: a P-type well region (4) located at the upper part of the N-type epitaxial layer (2) and a groove (5) located in the P-type well region (4), wherein the groove (5) extends into the N-type epitaxial layer (2), wherein an N-type heavily doped source region (8) is provided in the upper part of the P-type well region (4) and at the periphery of the groove (5), wherein a gate column (6) is provided in the groove (5), wherein the gate column (6) comprises a wide sub-column (61) located at the upper part and a narrow sub-column (62) located below the wide sub-column (61), wherein a silicon dioxide layer (7) is provided between the side surface of the wide sub-column (61) of the gate column (6) and the upper inner wall of the groove (5), wherein a P-type heavily doped region (11) is provided between the side surface of the narrow sub-column (62) of the gate column (6) and the lower inner wall of the groove (5), wherein the upper surface of the P-type heavily doped region (11) is provided below the lower surface of the P-type well region (4); An N-type heavily doped deep injection portion (12) is provided in the N-type epitaxial layer (2) between the P-type well regions (4) of adjacent device cells (13); the upper end of the N-type heavily doped deep injection portion (12) is flush with the N-type epitaxial layer (2), and the lower end of the N-type heavily doped deep injection portion (12) extends to the lower part of the N-type epitaxial layer (2); An insulating dielectric layer (9) is located above the trench (5) and covers the gate column (6); an upper metal electrode layer (10) is located above the insulating dielectric layer (9) and the N-type heavily doped source region (8) and is in contact with the upper surfaces of the insulating dielectric layer (9) and the N-type heavily doped source region (8).
2. The trench power MOS device according to claim 1, characterized in that: The height ratio of the wide sub-column (61) to the narrow sub-column (62) is 10:2-4.
3. The trench power MOS device according to claim 1, characterized in that: The bottom of the gate column (6) in the trench (5) is located below the P-type well region (4), and the gate column (6) extends to the middle of the N-type epitaxial layer (2).
4. The trench power MOS device according to claim 1, characterized in that: The lower end of the N-type heavily doped deep implantation portion (12) is lower than the bottom of the trench (5).
5. The trench power MOS device according to claim 1, characterized in that: The upper width of the N-type heavily doped deep injection portion (12) is greater than the lower width.