Carrier plate capable of simultaneously testing multiple chips
By performing groove processing on the conductive plane of the same measuring carrier plate of the multi-chip, the problem of inconsistent performance of the power supply system between different chips to be tested is solved, and the voltage drop of the conductive plane is unified, which improves the multi-chip detection effect and reduces the design cost.
Patent Information
- Application Number
- CN202421830909.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-31
- Publication Date
- 2025-06-13
- Estimated Expiration
- 2034-07-31
AI Technical Summary
During the process of multi-chip testing, it is difficult for existing carrier board design to ensure the consistency of the performance of power supply systems between different chips to be tested, resulting in reduced reliability and efficiency of test results and increased testing costs.
A carrier plate that can be tested by multiple chips is designed. The carrier plate has multiple independent conductivity planes on it. By slotting the conductive plane with excellent power supply performance, its power supply performance is reduced and the voltage drop of the conductive plane is unified.
Without changing the original supply path, the power supply performance of the conductive plane is unified, the detection effect of multi-chip is improved, and the production design cost is reduced.
Smart Images
Figure CN222979655U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of chip testing, and specifically relates to a carrier board for simultaneous testing of multiple chips. Background Technique
[0002] An ATE (Auto Test Equipment) carrier board is an interface circuit board dedicated to connecting a chip under test and a test device in chip testing. The carrier board can test only one chip or multiple chips simultaneously. The advantage of testing multiple chips under test is to reduce the test cost and shorten the test time.
[0003] During the test, power needs to be supplied to the chip under test. The power supply pins on the carrier board are connected to the power source, usually in the form of a conductive plane connected to the power supply pins of the chip under test in the middle of the carrier board. If a carrier board tests multiple chips simultaneously, multiple groups of conductive planes need to be designed simultaneously.
[0004] When testing high-end chips, it is necessary to ensure the stable performance of the power supply system, and the consistency of the power supply system performance between different chips under test also needs to be considered. If the power supply system performances between different chips under test are not designed consistently and the differences are large, then the quality of the test results may not necessarily indicate the quality of the chips themselves, and problems will occur in the reliability and test efficiency of the test results, which will further lead to an increase in the test cost.
[0005] For the chips at the test positions with excellent power supply system performance, the test results are always good. For the chips at the test positions with poor power supply system performance, the test results are always bad. The test results are unreasonable.
[0006] In actual design, the layout of the chips under test and the circuits around the chips under test are made similar and there will be no significant differences. The position of the power supply end of the carrier board is determined by the test machine and is not adjustable. Therefore, there must be differences in the distance between the power supply end of the carrier board and the chips under test, resulting in different power supply paths.
[0007] Therefore, when designing the power supply paths for multiple chips under test, there will definitely be some power supply paths that are straight and short, and some that are long and tortuous, resulting in poor consistency in the performance of the power supply paths for different chips under test. If it is objectively impossible to further optimize the power supply path of the longest group of chips under test, then in order to ensure the consistency of the power supply performance between different chips under test, it is only possible to degrade the power supply paths of the remaining chips under test.
[0008] The traditional methods for degrading the power supply path are, one is to select a farther position of the power supply end of the carrier board to make the power supply path longer, and the other is to redesign the power supply path to make it detour and bend, thus making the power supply path longer.
[0009] The disadvantage of these two methods is that both require significant modification to the power supply path design that has already been completed. If the original design is relatively complex, the amount of work for modification is even equivalent to re-designing from scratch, and this phenomenon has become an urgent problem to be solved by those skilled in the art. Summary of the Invention
[0010] The purpose of the present utility model is to provide a carrier board for simultaneous testing of multiple chips in view of the existing technical defects, so as to solve the problems raised in the above background art.
[0011] To solve the above technical problems, the present utility model provides the following technical solution: A carrier board for simultaneous testing of multiple chips, the carrier board has multiple independent conductive planes for conducting electricity, one end of the conductive plane is provided with a carrier board power supply terminal for connecting to a power supply, the other end of the conductive plane is provided with a chip installation end for installing chips to be tested, the conductive plane at least includes a first conductive plane and a second conductive plane, the length of the power supply path of the first conductive plane is less than that of the second conductive plane, the width of the first conductive plane is greater than that of the second conductive plane, and a notch is opened at the edge of the first conductive plane.
[0012] The present utility model further explains that a power supply pin is provided on the carrier board power supply terminal, and one end of the conductive plane is connected to the power supply pin.
[0013] The present utility model further explains that a power supply pin of the chip to be tested is provided at the chip installation end, and the end of the conductive plane far from the power supply pin is connected to the power supply pin of the chip to be tested.
[0014] The present utility model further explains that multiple notches are provided, and the multiple notches are arranged on both sides in the length direction of the power supply path of the conductive plane.
[0015] The present utility model further explains that the notches are arranged in a staggered manner along both sides of the power supply path of the conductive plane.
[0016] The present utility model further explains that the width W of the notch is greater than or equal to 0.25 mm.
[0017] Compared with the prior art, the beneficial effects achieved by the present utility model are as follows: When testing multiple chips, the present utility model performs grooving treatment on the conductive plane with excellent power supply performance, thereby reducing the power supply performance of this conductive plane, achieving the effect of deteriorating the power supply path of the conductive plane, realizing the unity of the voltage drop of the overall conductive plane, and improving the detection effect of multiple chips.
[0018] By grooving the conductive plane, without changing the original power supply path, the power supply performance of the conductive plane is unified, and the production design cost is reduced. Brief Description of the Drawings
[0019] The accompanying drawings are used to provide a further understanding of the present utility model and form a part of the specification. Together with the embodiments of the present utility model, they are used to explain the present utility model and do not constitute a limitation to the present utility model. In the accompanying drawings:
[0020] Figure 1 is a schematic diagram of the overall structure of the present utility model;
[0021] In the figure: 1, carrier board; 2, chip mounting end; 21, power supply pin of the chip to be tested; 3, carrier board power supply end; 31, power supply pin; 4, conductive plane; 41, first conductive plane; 42, second conductive plane; 5, notch. Specific embodiments
[0022] The technical solution of the present utility model will be further described in detail and non - restrictively below in conjunction with the preferred embodiments and their accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative work belong to the scope of protection of the present utility model.
[0023] Please refer to Figure 1 , the present utility model provides a technical solution: a carrier board for multi - chip co - testing, including the carrier board 1 body. There are several groups of chip mounting ends 2 for mounting the chips to be tested on the carrier board 1. A carrier board power supply end 3 for connecting to the power supply is provided on the carrier board 1 corresponding to each group of chip mounting ends 2. A conductive plane 4 for conducting electricity is provided between each group of chip mounting ends 2 and the corresponding carrier board power supply end 3.
[0024] A power supply pin 31 is provided on the carrier board power supply end 3, and a power supply pin 21 of the chip to be tested is provided on the chip mounting end 2. After the power supply pin 31 is connected to the power supply, it is electrically connected to the power supply pin 21 of the chip to be tested through the conductive plane 4.
[0025] The conductive plane 4 forms a power supply path connecting the power supply pin 31 and the power supply pin 21 of the chip to be tested.
[0026] A plurality of notches 5 are formed on both side edges of the conductive plane 4 along the length direction of the power supply path. The plurality of notches 5 are arranged in a staggered manner along the length direction of the power supply path of the conductive plane 4.
[0027] In this embodiment, a voltage drop will be formed in the conductive plane 4 when connecting the power supply pin 2 of the chip to be tested and the power supply pin 3. The voltage drop of the conductive plane 4 is positively correlated with the length of the power supply path of the conductive plane 4 and negatively correlated with the width of the conductive plane 4, that is, the shorter the path of the conductive plane 4 and the longer the path width, the lower the voltage drop of the conductive plane 4.
[0028] The conductive plane 4 includes at least a first conductive plane 41 and a second conductive plane 42. The length of the power supply path of the first conductive plane 41 is less than that of the second conductive plane 42, the width of the first conductive plane 41 is greater than that of the second conductive plane, and the second conductive plane 42 is in a zigzag shape to connect the power supply pin 31 and the power supply pin 21 of the chip under test. Therefore, the voltage drop of the second conductive plane 42 is higher than that of the first conductive plane 41. According to EDA, the voltage drops of the first conductive plane 41 and the second conductive plane 42 are calculated. EDA (Electronic Design Automation) is a prior art and is a software tool for the automated design and verification of electronics and integrated circuits, used to calculate the voltage drop values generated by the conductive plane 4.
[0029] Then, by controlling the number of notches 5 opened on the first conductive plane 41, the length L of the corresponding notches 5, and the width W of the notches 5, the voltage drop difference between the first conductive plane 41 and the second conductive plane 42 is made not greater than 10 millivolts.
[0030] In another embodiment, there are multiple groups of chip mounting ends 2 on the carrier board 1 with a number greater than two. The multiple groups of chip mounting ends 2 are connected through the conductive plane 4 to the carrier board power supply ends 3 at different positions correspondingly. Therefore, multiple groups of conductive planes 4 with different paths and widths will be formed. When no grooving treatment is carried out, each group of conductive planes 4 will form different voltage drops.
[0031] Calculate the voltage drops of different conductive planes 4 through EDA, and do not perform grooving treatment on the group of conductive planes 4 with the highest voltage drop formed among them.
[0032] Through the EDA calculation of the voltage drops of the remaining groups of conductive planes 4, by controlling the number of notches 5 opened on the corresponding conductive plane 4, the length L of the corresponding notches 5, and the width W of the notches 5, on the basis that the width W of the notches 5 is greater than or equal to 0.25 mm, the voltage drop difference between the remaining groups of conductive planes 4 and the group of conductive planes 4 without grooving is made not greater than 10 millivolts.
[0033] Specifically, the length of the notch 5 of the conductive plane 4 and the number of notches 5 are negatively correlated with the voltage drop difference between it and the group of conductive planes 4 with the highest voltage drop. That is, the greater the voltage drop difference between this conductive plane 4 and the group of conductive planes 4 with the highest voltage drop, the longer the length of the notch 5 or the more the number of notches 5, so that the voltage drops formed after grooving all the conductive planes 4 are the same as or tend to be the same as the voltage drop of the group of conductive planes 4 with the highest voltage drop, that is, the voltage drop difference of all the conductive planes 4 on the carrier board 1 is not greater than 10 millivolts, so as to achieve the simultaneous testing of multiple groups of chips under test on the carrier board 1 without modifying the existing conductive plane 4.
[0034] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present utility model, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present utility model.
[0035] Finally, it should be pointed out that the above embodiments are only used to illustrate the technical solutions of the present utility model, rather than to limit it. Although the present utility model has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present utility model.
Claims
1. A carrier board capable of testing multiple chips simultaneously, characterized in that: The carrier board (1) has a plurality of mutually independent conductive planes (4) for conducting electricity, one end of the conductive plane (4) is provided with a carrier board power supply terminal (3) for connecting to a power source, the other end of the conductive plane (4) is provided with a chip mounting terminal (2) for mounting a chip to be tested, the conductive plane (4) comprises at least a first conductive plane (41) and a second conductive plane (42), the power supply path length of the first conductive plane (41) is shorter than that of the second conductive plane (42), the width of the first conductive plane (41) is greater than that of the second conductive plane (42), and a notch (5) is provided at the edge of the first conductive plane (41).
2. The carrier board capable of simultaneously testing multiple chips according to claim 1, characterized in that: A power supply pin (31) is provided on the carrier board power supply end (3), and one end of the conductive plane (4) is connected to the power supply pin (31).
3. The carrier board capable of simultaneously testing multiple chips according to claim 2, characterized in that: The chip mounting end (2) is provided with a power pin (21) of the chip to be tested, and one end of the conductive plane (4) away from the power pin (31) is connected to the power pin (21) of the chip to be tested.
4. The carrier board capable of simultaneously testing multiple chips according to claim 1, characterized in that: A plurality of the slots (5) are provided, and the plurality of the slots (5) are provided on both sides of the length direction of the power supply path of the conductive plane (4).
5. A carrier capable of simultaneously testing multiple chips according to claim 1, characterized in that: the notches (5) are arranged in a staggered manner on both sides of the power supply path of the conductive plane (4).
6. The carrier board capable of simultaneously testing multiple chips according to claim 1, characterized in that: The width W of the notch (5) is greater than or equal to 0.25 mm.