Chip test platform

Abstract

The utility model discloses a chip test platform, comprising a detection area which is at least provided with a power coupling unit and a spectrum coupling unit; the power coupling unit at least comprises a PD probe and a collimating lens which is arranged along the straight line where the PD probe is located and located on the front side of the PD probe. The spectrum coupling unit at least comprises an optical fiber and double lenses which are arranged along the straight line where the optical fiber is located and located on the front side of the optical fiber. According to the utility model, through adding the collimating lens in the power coupling unit, when the chip is detected, the collimating lens converts laser into parallel light to enter the PD probe after the chip emits light; the double lenses are additionally arranged in the spectrum coupling unit, light emitted by the chip is converted into parallel light through the front lens, the parallel light is converted into converged light through the rear lens, the converged light enters the optical fiber, the light emitted by the chip is converged and introduced into the PD probe and the optical fiber, the intensity of light received by the PD probe and the optical fiber is increased, and the test requirement is met.

Description

Technical Field

[0001] The utility model relates to the technical field of chip testing, and specifically relates to a chip testing platform. Background Art

[0002] Semiconductor laser chips for high-speed optical communication transmission are usually not directly packaged into optical devices. The common practice in the industry is to first package them into COC semi-finished products using processes such as eutectic soldering and wire bonding, and then screen out potential early failure products through the aging & testing process. Finally, the tested qualified products are used for the production of optical devices. This approach greatly reduces the generation of early failure products at the client side and thus improves the operating stability of the entire optical network.

[0003] In the traditional COC design, the laser chip is usually mounted at the edge position of the substrate. Although the laser chip has a certain divergence angle in the horizontal and vertical light-emitting directions, power coupling and spectral coupling tests can generally meet the test requirements by installing corresponding PD probes and spectral probes at appropriate positions in the front end of the COC.

[0004] With the increase in the optical communication transmission rate, a new design has been made for the traditional edge-emitting structure. The new structure design requires a longer distance to be reserved between the chip and the substrate edge. At this time, according to the traditional test structure, the light actually entering the PD probe and the spectral probe will be very weak. Although the test can be carried out through software compensation, it is very difficult to ensure the repeatability and stability of the test equipment. Therefore, mismeasurement often occurs, leading to the outflow of defective products. Summary of the Utility Model

[0005] The technical problem to be solved by the utility model is to provide a chip testing platform that can ensure sufficient light intensity is received during power coupling testing and spectral coupling testing.

[0006] To solve the above technical problem, the utility model adopts the following technical scheme: A chip testing platform, comprising:

[0007] A detection area, at least provided with a power coupling unit and a spectral coupling unit;

[0008] The power coupling unit at least includes a PD probe and a collimating lens arranged along the straight line where the PD probe is located and in front of the PD probe;

[0009] The spectral coupling unit at least includes an optical fiber and a doublet lens arranged along the straight line where the optical fiber is located and in front of the optical fiber.

[0010] Furthermore, both the power coupling unit and the spectral coupling unit further include a mounting bracket for assembly and a first adjustment component for adjusting the position of the mounting bracket on the X, Y, and Z axes.

[0011] Furthermore, the detection area is also provided with:

[0012] A power-on unit for powering on the chip to be tested and capable of adjusting its position on the X, Y, and Z axes.

[0013] Furthermore, the detection area is also provided with:

[0014] An image recognition unit, at least including a camera for taking pictures of the chip position and a second adjustment component for adjusting the position of the camera on the X, Y, and Z axes.

[0015] Furthermore, the detection area is also provided with:

[0016] A temperature control platform for placing the chip to be tested and capable of controlling the temperature of the chip to be tested.

[0017] Furthermore, heat dissipation fins are also provided on the temperature control platform.

[0018] Furthermore, the temperature control platform can also adjust its position between the power coupling unit and the spectral coupling unit.

[0019] Furthermore, it further includes:

[0020] A loading and unloading area, at least provided with a loading mechanism, an unloading mechanism, and a picking mechanism;

[0021] The loading mechanism at least includes a first receiving platform for receiving the chip to be tested and a third adjustment component for adjusting the position of the first receiving platform in the X and Y directions;

[0022] The unloading mechanism at least includes a second receiving platform for receiving the tested chip and a fourth adjustment component for adjusting the position of the second receiving platform in the X and Y directions;

[0023] The picking mechanism at least includes a picking component for picking the chip and a fifth adjustment component for adjusting the position of the picking component in the X, Y, and Z directions.

[0024] The beneficial effects of the present utility model are reflected in:

[0025] In the chip test platform of the present utility model, by adding a collimating lens in the power coupling unit, when detecting the chip, after the chip emits light, the collimating lens converts the laser into parallel light and enters the PD probe; by adding a double-lens in the spectral coupling unit, after the chip emits light, it is converted into parallel light by the front lens, and the parallel light is converted into convergent light and enters the optical fiber after passing through the rear lens, realizing the convergence of the chip's emitted light and respectively introducing it into the PD probe and the optical fiber, increasing the light intensity received by the PD probe and the optical fiber to meet the test requirements. Description of the Drawings

[0026] Figure 1 is a schematic structural diagram of the chip test platform of the present utility model;

[0027] Figure 2 is a schematic structural diagram of the chip test platform of the present utility model;

[0028] Figure 3 is a schematic structural diagram of the power coupling unit of the present utility model;

[0029] Figure 4 is Figure 3 an enlarged view of part C;

[0030] Figure 5 is a schematic structural diagram of the spectral coupling unit of the present utility model;

[0031] Figure 6 is Figure 5 an enlarged view of part D.

[0032] The marks of each component in the drawings are: 1, power coupling unit; 101, PD probe; 102, collimating lens; 2, spectral coupling unit; 201, optical fiber; 202, doublet lens; 203, mounting bracket; 204, first adjustment component; 3, power supply unit; 4, image recognition unit; 401, camera; 402, second adjustment component; 5, temperature control platform; 6, heat dissipation fins; 7, feeding mechanism; 701, first receiving table; 702, third adjustment component; 8, discharging mechanism; 801, second receiving table; 802, fourth adjustment component; 9, extraction mechanism; 901, extraction component; 902, fifth adjustment component; A, detection area; B, loading and unloading area. Specific embodiments

[0033] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. Without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0034] Refer to Figure 1 、 4 、6.

[0035] The chip test platform of the present utility model includes:

[0036] A detection area A, which is at least provided with a power coupling unit 1 and a spectral coupling unit 2;

[0037] The power coupling unit 1 includes at least a PD probe 101 and a collimating lens 102 arranged along the line where the PD probe 101 is located and located on the front side of the PD probe 101;

[0038] The spectral coupling unit 2 includes at least an optical fiber 201 and a bi-lens 202 arranged along the line where the optical fiber 201 is located and located on the front side of the optical fiber 201. With such a design, when performing power coupling detection on the chip, after the chip emits light, the collimating lens 102 converts the laser into parallel light and enters the PD probe 101; when performing spectral coupling detection on the chip, after the chip emits light, it is converted into parallel light by the front lens, and the parallel light is converted into convergent light after passing through the rear lens and enters the optical fiber 201, realizing the convergence of the light emitted by the chip and introducing it into the PD probe 101 and the optical fiber 201 respectively, increasing the light intensity received by the PD probe 101 and the optical fiber 201 to meet the test requirements. And among them, the optical fiber 201 is connected to the spectrometer port.

[0039] In this embodiment, referring to Figures 3 - 6 , both the power coupling unit 1 and the spectral coupling unit 2 further include a mounting bracket 203 for assembly and a first adjustment component 204 for adjusting the positions of the mounting bracket 203 on the X, Y, and Z axes. With such a design, the positions of the power coupling unit 1 and the spectral coupling unit 2 are adjustable, which is convenient for aligning with the light outlet of the chip to be tested. And among them, the first adjustment component 204 can adopt the existing technology, for example, an adjustment structure that realizes the movement of the X, Y, and Z axes through three linear drivers respectively.

[0040] In this embodiment, referring to Figure 1 , the detection area A is also provided with:

[0041] A power supply unit 3 for powering the chip to be tested and capable of adjusting the position on the X, Y, and Z axes. With such a design, it is convenient to adjust the position during detection to power the chip. And among them, the power supply unit 3 can adopt the existing technology, for example, composed of a cylinder and a set of spring pins, and after finding the corresponding position, it descends to complete the power supply. And this part is externally connected to a source meter and a Switchbox to control the power on and off through software. At the same time, the power supply unit 3 can also adopt the existing technology, for example, an adjustment structure that realizes the movement of the X, Y, and Z axes through three linear drivers respectively.

[0042] In this embodiment, referring to Figure 1 , the detection area A is also provided with:

[0043] The image recognition unit 4 at least includes a camera 401 for taking pictures of the chip position and a second adjustment component 402 for adjusting the position of the camera 401 on the X, Y, and Z axes. With this design, the chip position can be determined through the camera 401 connected to an external recognition system, which facilitates the movement and alignment of the power coupling unit 1, the spectral coupling unit 2, and the power-on unit 3. Among them, the image recognition unit 4 can also adopt an adjustment structure in the prior art, for example, an adjustment structure that realizes the movement on the X, Y, and Z axes through three linear drivers respectively, and the image recognition unit 4 and the power-on unit 3 can adopt the same adjustment structure for movement on the Y axis.

[0044] In this embodiment, referring to Figure 1 , the detection area A is further provided with:

[0045] A temperature control platform 5 for placing the chip to be tested and capable of controlling the temperature of the chip to be tested. With this design, the performance test of the chip at different temperatures can be satisfied, and the temperature control platform 5 is externally connected to a TEC control system to facilitate real-time reading of the temperature of the test platform. During the temperature control process, it can be cooled or heated, specifically depending on the difference between the actual temperature and the target temperature of the temperature control platform 5 itself. That is, if the current temperature of the temperature control platform 5 is higher than the set temperature, it will be cooled; if the temperature of the temperature control platform 5 is lower than the set temperature, it will be heated.

[0046] In this embodiment, referring to Figure 1 , heat dissipation fins 6 are further provided on the temperature control platform 5. With this design, cooling is achieved through the heat dissipation fins 6 to ensure the stability of the temperature of the temperature control platform 5.

[0047] In this embodiment, referring to Figure 1 , the temperature control platform 5 can also be adjusted in position between the power coupling unit 1 and the spectral coupling unit 2. Among them, the position adjustment of the temperature control platform 5 can be realized by a linear driver for moving in the X-axis direction in the prior art.

[0048] In this embodiment, referring to Figure 2 , it further includes:

[0049] A loading and unloading area B, which at least includes a loading mechanism 7, an unloading mechanism 8, and a picking mechanism 9;

[0050] The loading mechanism 7 at least includes a first receiving platform 701 for receiving the chip to be detected and a third adjustment component 702 for adjusting the position of the first receiving platform 701 in the X and Y axis directions;

[0051] The unloading mechanism 8 at least includes a second receiving platform 801 for receiving the detected chip and a fourth adjustment component 802 for adjusting the position of the second receiving platform 801 in the X and Y axis directions;

[0052] The extraction mechanism 9 includes at least an extraction component 901 for extracting the chip and a fifth adjustment component 902 for adjusting the position of the extraction component 901 in the X, Y, and Z axis directions. With such a design, through the partition setting, the detection table has clear division of labor and regular structure, and through automated loading and unloading, the detection efficiency is accelerated.

[0053] Moreover, the extraction mechanism 9 can adopt a negative pressure suction mechanism in the prior art. The chip is extracted from the first receiving platform 701 by the extraction mechanism 9 and placed on the temperature control platform 5, and after detection, the chip is extracted from the temperature control platform 5 and placed on the second receiving platform 801 for output.

[0054] Moreover, the first receiving platform 701 and the second receiving platform 801 can adopt, for example, in the prior art, an adjustment structure for realizing the adjustment in the X and Y axis directions through two linear drivers.

[0055] It should also be noted that when the chip is tested in this application, a carrier can be set for loading to avoid damaging the chip during the moving process.

[0056] It should be noted that if there are directional indications such as up, down, left, right, front, back... in the embodiments of the present utility model, the directional indications are only used to explain the relative position relationship and movement conditions between components in a specific posture as shown in the drawings. If the specific posture changes, the directional indications will also change accordingly.

[0057] In addition, if there are descriptions such as "first", "second", etc. in the embodiments of the present utility model, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the meaning of "and / or" appearing throughout the text includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, or solution B, or the solution where A and B are satisfied simultaneously. In addition, "a plurality" means more than two. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the fact that those skilled in the art can implement it. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present utility model.

[0058] It should be understood that the examples and embodiments described herein are only for illustration and are not used to limit the present utility model. Those skilled in the art can make various modifications or changes according to it. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. A chip testing platform, characterized in that: include: The detection area (A) is provided with at least a power coupling unit (1) and a spectrum coupling unit (2); A power coupling unit (1) comprising at least a PD probe (101), and a collimating lens (102) arranged along a straight line where the PD probe (101) is located and located in front of the PD probe (101); The spectrum coupling unit (2) comprises at least an optical fiber (201) and a double lens (202) arranged along a straight line where the optical fiber (201) is located and located in front of the optical fiber (201).

2. The chip testing platform according to claim 1, characterized in that: The power coupling unit (1) and the spectrum coupling unit (2) also include a mounting frame (203) for assembly and a first adjustment component (204) for adjusting the position of the mounting frame (203) on the X, Y and Z axes.

3. The chip testing platform according to claim 1, characterized in that: The detection area (A) is also provided with: The power-on unit (3) is used to power on the chip to be tested and can adjust the position on the X, Y and Z axes.

4. The chip testing platform according to claim 2 or 3, characterized in that: The detection area (A) is also provided with: The image recognition unit (4) comprises at least a camera (401) for photographing the position of a chip and a second adjustment component (402) for adjusting the position of the camera (401) on the X, Y and Z axes.

5. The chip testing platform according to claim 1, characterized in that: The detection area (A) is also provided with: The temperature control platform (5) is used to place the chip to be tested and can control the temperature of the chip to be tested.

6. The chip testing platform according to claim 5, characterized in that: The temperature control platform (5) is also provided with heat dissipation fins (6).

7. The chip testing platform according to claim 5, characterized in that: The temperature control platform (5) can also perform position adjustment between the power coupling unit (1) and the spectrum coupling unit (2).

8. The chip testing platform according to claim 1, characterized in that: Also includes: The loading and unloading area (B) is provided with at least a loading mechanism (7), a unloading mechanism (8) and an extracting mechanism (9); A loading mechanism (7) at least comprises a first receiving platform (701) for receiving the test chip and a third adjusting component (702) for adjusting the position of the first receiving platform (701) in the X-axis and Y-axis directions; The unloading mechanism (8) comprises at least a second receiving platform (801) for receiving the chips after testing and a fourth adjusting component (802) for adjusting the position of the second receiving platform (801) in the X-axis and Y-axis directions; The extraction mechanism (9) comprises at least an extraction component (901) for extracting a chip and a fifth adjustment component (902) for adjusting the position of the extraction component (901) in the X, Y and Z axis directions.

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