Clock circuit and clock source device thereof
By dividing the voltage of the power supply to the microcontroller and clock module, the existing clock circuit has solved the problem of high space and cost, and a battery-free clock circuit is realized, saving space and reducing costs.
Patent Information
- Application Number
- CN202421397616.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-18
- Publication Date
- 2025-06-17
- Estimated Expiration
- 2034-06-18
AI Technical Summary
The existing clock circuits take up a lot of space and cost, especially because of the need for battery-assisted power supply, which increases the size and price of the equipment.
A clock circuit is designed, which avoids dependence on the battery by supplying the voltage of the power supply to the microcontroller and the clock module in two channels, reducing space consumption and reducing costs.
A clock circuit without battery-assisted power is realized, saving space and reducing costs, and improving the portability and economicality of the device.
Smart Images
Figure CN222996531U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electronic circuits, and particularly to a clock circuit and a clock source device thereof. Background Art
[0002] A clock circuit is used to provide a clock signal uniformly used by each component in the system, so that each component operates according to a specific clock sequence, ensuring the stability of the system operation.
[0003] The existing clock circuit, such as Figure 1 shown, includes: a first power supply 10, a third voltage conversion chip 20, a controller 30, a clock source 40, and a battery 50.
[0004] The first power supply 10 is connected to the input end of the third voltage conversion chip 20.
[0005] The output end of the third voltage conversion chip 20 is connected to the controller 30 and the clock source 40; the third voltage conversion chip 20 is configured to: receive the voltage of the first power supply 10 and convert it into a third voltage for output to the controller 30 and the clock source 40.
[0006] The clock source 40 is communicatively connected to the controller 30 through an interface.
[0007] The battery 50 is connected to the input end of the clock source 40 and is used to output a fourth voltage to the clock source 40.
[0008] Wherein, the interface includes a clock interface and a data interface; the clock source 40 outputs a clock signal to the controller 30 through the clock interface and outputs the system time (such as time information such as year, month, day, hour, minute, second, etc.) through the data interface.
[0009] During actual use, when the system is operating normally, the third voltage output by the third voltage conversion chip 20 powers the controller 30 and the clock source 40; when the system is turned off, for example, when the controller 30 is turned off and other situations that cause the third voltage to lose power, the fourth voltage output by the battery 50 powers the clock source 40 to ensure that the clock source 40 continues to provide a reliable clock signal and system time for the controller 30.
[0010] For the above clock circuit, on the one hand, the battery 50 needs to occupy a certain space, and the portability is not high; on the other hand, the power supply through the battery 50 has a high cost. Summary of the Utility Model
[0011] The embodiments of the present application aim to provide a clock circuit that can solve the defects of the existing clock circuit in occupying space and high cost.
[0012] To solve the above technical problems, an embodiment of the present utility model provides a clock circuit. The clock circuit includes:
[0013] A control module, which is connected to a power supply and is configured to output a first signal according to the voltage of the power supply;
[0014] A power supply module, which is connected to the output end of the control module and is used to receive the first signal; the first output end of the power supply module is connected to the input end of the control module;
[0015] Wherein, the power supply module is configured to: when the first signal is at a high level, the power supply module outputs a first voltage to the control module and outputs a second voltage; when the first signal is at a low level, the power supply module outputs the second voltage;
[0016] A clock module, the input end of which is connected to the second output end of the power supply module and is used to receive the second voltage; the output end of the clock module is connected to the clock receiving end of the control module and is used to output a clock to the control module.
[0017] Optionally, in the clock circuit, the detection module includes: the power supply module includes: a power-on / off unit, a first power supply unit and a second power supply unit; the first input end of the power-on / off unit is connected to the power supply; the second input end of the power-on / off unit is connected to the output end of the control module; one end of the first power supply unit is connected to the output end of the power-on / off unit; the other end of the first power supply unit is connected to the input end of the control module; one end of the second power supply unit is connected to the power supply; the other end of the second power supply unit is connected to the input end of the clock module.
[0018] Optionally, in the clock circuit, the power-on / off unit includes: a first switch, a first capacitor, a second capacitor, a first diode and a second diode; the first end of the first switch is connected to the power supply; the second end of the first switch is connected to the first end of the first capacitor and the anode of the first diode; the second end of the first capacitor is grounded; the first end of the second capacitor is connected to the anode of the second diode and the output end of the control module; the second end of the second capacitor is grounded; the cathode of the first diode is connected to the cathode of the second diode and one end of the first power supply unit.
[0019] Optionally, in the clock circuit, the first power supply unit includes: a first voltage conversion chip, a first resistor, a third capacitor, a fourth capacitor, and a fifth capacitor; the input end of the first voltage conversion chip is connected to the first end of the third capacitor and the power supply; the enable end of the first voltage conversion chip is connected to the first end of the first resistor and the output end of the power-on / off unit; the output end of the first voltage conversion chip is connected to the first end of the fourth capacitor, the first end of the fifth capacitor, and the input end of the control module; the ground end of the first voltage conversion chip is grounded; the second end of the first resistor, the second end of the third capacitor, the second end of the fourth capacitor, and the second end of the fifth capacitor are grounded.
[0020] Optionally, in the clock circuit, the second power supply unit includes: a second voltage conversion chip, a sixth capacitor, and a seventh capacitor; the input end of the second voltage conversion chip is connected to the first end of the sixth capacitor and the power supply; the output end of the second voltage conversion chip is connected to the first end of the seventh capacitor and the clock receiving end of the control module; the ground end of the second voltage conversion chip is grounded; the second end of the sixth capacitor and the second end of the seventh capacitor are grounded.
[0021] Optionally, in the clock circuit, the control module includes: a voltage dividing unit and at least one microcontroller; wherein, the voltage dividing unit includes a second resistor, a third resistor, and an eighth capacitor; the first end of the second resistor is connected to the power supply; the second end of the second resistor is connected to the first end of the third resistor, the first end of the eighth capacitor, and the input end of the microcontroller; the second end of the third resistor and the second end of the eighth capacitor are grounded.
[0022] Optionally, in the clock circuit, one end of the microcontroller is connected to the power supply; the output end of the microcontroller is connected to the power supply module for outputting the first signal; wherein, the microcontroller is configured to output a high-level first signal when the voltage at the sampling port is greater than the preset voltage; and output a low-level first signal when the voltage at the sampling port is less than the preset voltage.
[0023] Optionally, in the clock circuit, the clock module includes: a crystal oscillator, a ninth capacitor, a tenth capacitor, an eleventh capacitor, and a clock chip; one end of the crystal oscillator is connected to the first end of the ninth capacitor and the oscillator input end of the clock chip; the other end of the crystal oscillator is connected to the first end of the tenth capacitor and the oscillator output end of the clock chip; the power supply end of the clock chip is connected to the first end of the eleventh capacitor and the second output end of the power supply unit; the clock output end of the clock chip is connected to the control module; the clock chip is communicatively connected to the control module through a data interface; the second ends of the ninth capacitor, the tenth capacitor, the eleventh capacitor, and the ground end of the clock chip are grounded.
[0024] Optionally, in the clock circuit, the first voltage conversion chip uses the ME6211 C33M5G-N chip with an output voltage of 3.3V; the second voltage conversion chip uses the XC6206P301 MR chip with an output voltage of 3V.
[0025] To solve the above problems, an embodiment of the present application further provides a clock source device, including: the clock circuit as described above.
[0026] The clock circuit provided by the present utility model supplies power to the microcontroller and the clock module separately through two paths of the power supply voltage, without using a battery for auxiliary power supply, saving space and reducing costs at the same time. Description of the Drawings
[0027] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the drawings in the drawings do not constitute a proportional limitation.
[0028] Figure 1 is a schematic structural diagram of an existing clock circuit;
[0029] Figure 2 is a schematic structural diagram of the clock circuit provided by an embodiment of the present utility model;
[0030] Figure 3 is a schematic diagram of the principle of the clock circuit provided by an embodiment of the present utility model. Detailed Embodiments
[0031] The present utility model will be described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present utility model, but do not limit the utility model in any form. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present utility model, several modifications and improvements can be made. These all belong to the protection scope of the present utility model.
[0032] In order to make the purpose, technical solution and advantages of the present application more clear, the following further details the present application in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0033] It should be noted that if there is no conflict, the various features in the embodiments of the present utility model can be combined with each other, and all are within the protection scope of the present application. In addition, although the functional modules are divided in the device schematic diagram and the logical sequence is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order from the module division in the device or the sequence in the flowchart.
[0034] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by those skilled in the technical field to which the present utility model belongs. The terms used in this specification in the description of the present utility model are only for the purpose of describing specific embodiments and are not used to limit the present utility model. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items.
[0035] In addition, the technical features involved in the various embodiments of the present utility model described below can be combined with each other as long as they do not conflict with each other.
[0036] Figure 2 The structural schematic diagram of the clock circuit provided by the embodiment of the present utility model is shown, as Figure 3 shown:
[0037] The clock circuit 1 includes: a control module 200, a power supply module 300, and a clock module 400.
[0038] The control module 200 is connected to the power supply 100 and is configured to: output a first signal according to the voltage of the power supply 100.
[0039] The power supply module 300 is connected to the output end of the control module 200 for receiving the first signal; the first output end of the power supply module 300 is connected to the input end of the control module 200.
[0040] Among them, the power supply module 300 is configured to: when the first signal is at a high level, the power supply module 300 outputs a first voltage to the control module 200 and outputs a second voltage; when the first signal is at a low level, the power supply module 300 outputs the second voltage.
[0041] The input end of the clock module 400 is connected to the second output end of the power supply module 300 for receiving the second voltage; the output end of the clock module 400 is connected to the clock receiving end of the control module 200 for outputting a clock to the control module 200; the clock module 400 is communicatively connected to the control module 200 through a serial interface for outputting the system time to the control module 200.
[0042] Specifically, the power supply 100 can directly use a battery pack and other fixed power supplies, or can be obtained by rectifying alternating current (such as household three-phase electricity).
[0043] During actual use, when the voltage of the power supply 100 is greater than the first voltage, the output first signal is at a high level. At this time, the power supply module 300 outputs the first voltage and the second voltage to supply power to the control module 200 and the clock module 400; when the voltage of the power supply 100 is less than the first voltage, the output first signal is at a low level. At this time, the power supply module 300 only outputs the second voltage to supply power to the clock module 400.
[0044] Figure 3 The schematic diagram of the clock circuit provided by the embodiment of the present invention is shown as Figure 3 shown:
[0045] The power supply module 300 includes: a power on / off unit 310, a first power supply unit 320, and a second power supply unit 330.
[0046] The first input end of the power on / off unit 310 is connected to the power supply 100; the second input end of the power on / off unit 310 is connected to the output end of the control module 200 for receiving the first signal.
[0047] In this embodiment, the power on / off unit 310 is configured to: when the first signal received by the second input end of the power on / off unit 310 is at a high level, the output end of the power on / off unit 310 is at a high level; when the first signal received by the second input end of the power on / off unit 310 is at a low level, the output end of the power on / off unit 310 is at a low level.
[0048] One end of the first power supply unit 320 is connected to the output end of the power on / off unit 310; the other end of the first power supply unit 320 is connected to the input end of the control module 200.
[0049] One end of the second power supply unit 330 is connected to the power supply 100; the other end of the second power supply unit 330 is connected to the input end of the clock module 400.
[0050] During actual use, when the output end of the power-on / off unit 310 is at a high level, the first power supply unit 320 supplies power to the control module 200, and the second power supply unit 330 supplies power to the clock module 400; when the output end of the power-on / off unit 310 is at a low level, the first power supply unit 320 does not supply power, and the second power supply unit 330 supplies power to the clock module 400.
[0051] The power-on / off unit 310 includes: a first switch S1, a first capacitor C1, a second capacitor C2, a first diode D1, and a second diode D2.
[0052] The first end of the first switch S1 is connected to the power supply 100; the second end of the first switch S1 is connected to the first end of the first capacitor C1 and the anode of the first diode D1, and is used to output a switching signal to the first diode D1; specifically, when the first switch S1 is off, the switching signal is at a low level; when the first switch S1 is on, the switching signal is at a high level.
[0053] Among them, the first switch S1 can use a push-button switch, a DIP switch, and other types of switches to control whether to connect to the power supply 100; when the first switch S1 is closed, due to mechanical switch jitter, there will be short-time contact and interruption. Since the first capacitor C1 has the ability to store charge and the charge changes slowly, the output voltage has stability.
[0054] The second end of the first capacitor C1 is grounded.
[0055] The first end of the second capacitor C2 is connected to the anode of the second diode D2 and the output end of the control module 200, and is used to receive the first signal; the second end of the second capacitor C2 is grounded; the second capacitor C2 is used to filter out high-frequency noise in the circuit and reduce interference to the circuit.
[0056] The cathode of the first diode D1 is connected to the cathode of the second diode D2 and one end of the first power supply unit 320.
[0057] During actual use, when the switching signal is at a low level, the output end of the power-on / off unit 310 is at a low level; when the switching signal is at a high level, at this time, the level of the output end of the power-on / off unit 310 changes following the level of the first signal; when the first signal is at a low level, the level of the output end of the power-on / off unit 310 is at a low level; when the first signal is at a high level, the level of the output end of the power-on / off unit 310 is at a high level.
[0058] The first power supply unit 320 includes: a first voltage conversion chip U1, a first resistor R1, a third capacitor C3, a fourth capacitor C4, and a fifth capacitor C5.
[0059] The input terminal of the first voltage conversion chip U1 is connected to the first terminal of the third capacitor C3 and the power supply 100; the enable terminal of the first voltage conversion chip U1 is connected to the first terminal of the first resistor R1 and the output terminal of the power on / off unit 310; the output terminal of the first voltage conversion chip U1 is connected to the first terminal of the fourth capacitor C4, the first terminal of the fifth capacitor C5, and the input terminal of the control module 200; the ground terminal of the first voltage conversion chip U1 is grounded.
[0060] It can be understood that the level of the enable terminal of the first voltage conversion chip U1 controls the level of the output terminal of the first voltage conversion chip U1, that is, whether to supply power to the control module 200; when the level of the enable terminal of the first voltage conversion chip U1 is low, the output terminal level is low and no power is supplied; when the level of the enable terminal of the first voltage conversion chip U1 is high, power is supplied to the control module 200.
[0061] The second terminal of the first resistor R1, the second terminal of the third capacitor C3, the second terminal of the fourth capacitor C4, and the second terminal of the fifth capacitor C5 are grounded.
[0062] Among them, the first resistor R1 is used to ensure that the level is low when the enable terminal is floating, so as to confirm whether to supply power to the control module 200; the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 are used to filter out high-frequency noise in the circuit and reduce the impact of current mutation on the circuit.
[0063] The second power supply unit 330 includes: a second voltage conversion chip U2, a sixth capacitor C6, and a seventh capacitor C7.
[0064] The input terminal of the second voltage conversion chip U2 is connected to the first terminal of the sixth capacitor C6 and the power supply 100; the output terminal of the second voltage conversion chip U2 is connected to the first terminal of the seventh capacitor C7 and the clock module 400; the ground terminal of the second voltage conversion chip U2 is grounded.
[0065] The second terminal of the sixth capacitor C6 and the second terminal of the seventh capacitor C7 are grounded.
[0066] In this embodiment, the second voltage conversion chip U2 converts the voltage of the power supply 100 into a second voltage to supply power to the clock module 400.
[0067] The control module 200 includes: a voltage division unit 210 and at least one microcontroller 220.
[0068] Among them, the voltage division unit 210 includes a second resistor R2, a third resistor R3, and an eighth capacitor C8.
[0069] The first end of the second resistor R2 is connected to the power supply 100; the second end of the second resistor R2 is connected to the first end of the third resistor R3, the first end of the eighth capacitor C8, and the input end of the microcontroller 220.
[0070] The second end of the third resistor R3 and the second end of the eighth capacitor C8 are grounded.
[0071] One end of the microcontroller 220 is connected to the power supply 100.
[0072] The output end of the microcontroller 220 is connected to the power supply module 300, for outputting a first signal.
[0073] Wherein, the microcontroller 220 is configured to output a high-level first signal when the voltage at the sampling port is greater than the preset voltage; and output a low-level first signal when the voltage at the sampling port is less than the preset voltage.
[0074] In the actual use process, the preset voltage refers to the voltage divided by the series connection of the second resistor R2 and the third resistor R3; the voltage at the sampling port is obtained by dividing the voltage of the power supply 100 by the second resistor R2 and the third resistor R3.
[0075] The clock module 400 includes: a crystal oscillator Y1, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, and a clock chip U3.
[0076] One end of the crystal oscillator Y1 is connected to the first end of the ninth capacitor C9 and the oscillator input end of the clock chip U3; the other end of the crystal oscillator Y1 is connected to the first end of the tenth capacitor C10 and the oscillator output end of the clock chip U3.
[0077] The power supply end of the clock chip U3 is connected to the first end of the eleventh capacitor C11 and the second output end of the power supply unit; the clock output end of the clock chip U3 is connected to the control module 200; the clock chip U3 is communicatively connected to the control module 200 through a serial interface.
[0078] The second end of the ninth capacitor C9, the second end of the tenth capacitor C10, the second end of the eleventh capacitor C11, and the ground end of the clock chip U3 are grounded.
[0079] It can be understood that the crystal oscillator Y1 is used to generate a reference clock frequency and output it to the clock chip U3; the clock chip U3 is internally provided with a frequency divider for receiving and reducing the reference clock frequency, and one or more registers for calculating the system time (such as time information of year, month, day, hour, minute, second, etc.); the serial interface includes an interrupt output port, a serial clock interface, and a serial data interface.
[0080] Specifically, the reference clock frequency generated by the crystal oscillator Y1 can be adjusted by adjusting the capacitance values of the ninth capacitor C9 and the tenth capacitor C10; the frequency divider obtains the second clock (frequency of 1 Hz) by dividing the reference clock frequency multiple times; the clock chip U3 outputs the second clock to the control module 200 through the clock output terminal; the interrupt output port of the clock chip U3 is configured to be active low, and when the interrupt output port is at a low level, the system time is transmitted to the control module 200 through the serial clock interface and the serial data interface.
[0081] It can be understood that when the serial clock interface is at a high level and the serial data interface is at a high level, the bus between the clock chip U3 and the control module 200 is idle, that is, there is no data transmission between the clock chip U3 and the control module 200; when the serial clock interface is at a high level and the serial data interface jumps from a high level to a low level, data transmission starts; during data transmission, when the serial clock interface is at a low level, the level of the serial data interface can change, that is, one byte of data is transmitted; when the serial clock interface is at a high level and the serial data interface jumps from a high level to a low level, data transmission stops.
[0082] Further, taking the reference clock frequency of 32.768 KHz as an example, the second clock can be obtained after 15 times of frequency division by the frequency divider (2 to the 15th power equals 32768); when the interrupt output port of the clock chip U3 is at a low level, a communication request is sent to the control module 200; when the control module 200 cannot communicate with the clock chip U3 (for example, it is communicating with other devices), both the serial clock interface and the serial data interface are configured to be at a high level; when the control module 200 starts to communicate with the clock chip U3, a start signal is sent, the serial clock interface is configured as a clock signal, and when the clock signal is at a high level, the serial data interface is configured to jump from a high level to a low level; when the control module 200 stops communicating with the clock chip U3, a stop signal is sent, the serial clock interface is configured as a clock signal, and when the clock signal is at a high level, the serial data interface is configured to jump from a low level to a high level.
[0083] In this embodiment, the first voltage conversion chip U1 uses the ME6211 C33M5G-N chip with an output voltage of 3.3V, and the second voltage conversion chip U2 uses the XC6206P301 MR chip with an output voltage of 3V.
[0084] The embodiment of the present application also provides a clock source device, including: the clock circuit as described above.
[0085] The technical features involved in the embodiments of the present application can be combined with each other as long as they do not conflict with each other, and can be independently applied in different embodiments as long as they do not depend on each other.
[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than limiting them; under the idea of the present application, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order, and there are many other variations in different aspects of the present application as described above. For the sake of brevity, they are not provided in detail; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A clock circuit, characterized in that: include: A control module, the control module is connected to the power supply and is configured to: output a first signal according to the voltage of the power supply; A power supply module, the power supply module is connected to the output end of the control module and is used to receive the first signal; the first output end of the power supply module is connected to the input end of the control module; The power supply module is configured as follows: when the first signal is at a high level, the power supply module outputs a first voltage to the control module, and outputs a second voltage; when the first signal is at a low level, the power supply module outputs the second voltage; A clock module, wherein the input end of the clock module is connected to the second output end of the power supply module for receiving the second voltage; the output end of the clock module is connected to the clock receiving end of the control module for outputting the clock to the control module; the clock module is communicatively connected to the control module via a serial interface.
2. The clock circuit according to claim 1, characterized in that: The power supply module includes: a switch unit, a first power supply unit and a second power supply unit; The first input end of the switch unit is connected to the power supply; the second input end of the switch unit is connected to the output end of the control module for receiving the first signal; Wherein, the switch unit is configured such that: when the first signal is at a high level, the output end of the switch unit is at a high level; when the first signal is at a low level, the output end of the switch unit is at a low level; One end of the first power supply unit is connected to the output end of the switch unit; the other end of the first power supply unit is connected to the input end of the control module; One end of the second power supply unit is connected to the power supply; the other end of the second power supply unit is connected to the input end of the clock module.
3. The clock circuit according to claim 2, characterized in that: The switch unit comprises: a first switch, a first capacitor, a second capacitor, a first diode and a second diode; The first end of the first switch is connected to the power supply; the second end of the first switch is connected to the first end of the first capacitor and the anode of the first diode; The second end of the first capacitor is grounded; The first end of the second capacitor is connected to the anode of the second diode and the output end of the control module; the second end of the second capacitor is grounded; The cathode of the first diode is connected to the cathode of the second diode and one end of the first power supply unit.
4. The clock circuit according to claim 3, characterized in that: The first power supply unit includes: a first voltage conversion chip, a first resistor, a third capacitor, a fourth capacitor and a fifth capacitor; The input end of the first voltage conversion chip is connected to the first end of the third capacitor and the power supply; the enable end of the first voltage conversion chip is connected to the first end of the first resistor and the output end of the switch unit; the output end of the first voltage conversion chip is connected to the first end of the fourth capacitor, the first end of the fifth capacitor and the input end of the control module; the ground end of the first voltage conversion chip is grounded; The second end of the first resistor, the second end of the third capacitor, the second end of the fourth capacitor, and the second end of the fifth capacitor are grounded.
5. The clock circuit according to claim 4, characterized in that: The second power supply unit includes: a second voltage conversion chip, a sixth capacitor and a seventh capacitor; The input end of the second voltage conversion chip is connected to the first end of the sixth capacitor and the power supply; the output end of the second voltage conversion chip is connected to the first end of the seventh capacitor and the clock module; the ground end of the second voltage conversion chip is grounded; The second end of the sixth capacitor and the second end of the seventh capacitor are grounded.
6. The clock circuit according to claim 1, characterized in that: The control module includes: a voltage dividing unit and at least one microcontroller; Wherein, the voltage dividing unit includes a second resistor, a third resistor and an eighth capacitor; The first end of the second resistor is connected to the power supply; the second end of the second resistor is connected to the first end of the third resistor, the first end of the eighth capacitor and the input end of the microcontroller; A second end of the third resistor and a second end of the eighth capacitor are grounded.
7. The clock circuit according to claim 6, characterized in that: One end of the microcontroller is connected to the power supply; the voltage of the sampling port of the microcontroller is obtained by dividing the voltage of the power supply through the second resistor and the third resistor; The output terminal of the microcontroller is connected to the power supply module for outputting the first signal; The microcontroller is configured such that when the voltage of the sampling port is greater than a preset voltage, the output first signal is a high level; when the voltage of the sampling port is less than the preset voltage, the output first signal is a low level.
8. The clock circuit according to claim 1, characterized in that: The clock module includes: a crystal oscillator, a ninth capacitor, a tenth capacitor, an eleventh capacitor and a clock chip; One end of the crystal oscillator is connected to the first end of the ninth capacitor and the oscillator input end of the clock chip; the other end of the crystal oscillator is connected to the first end of the tenth capacitor and the oscillator output end of the clock chip; The power supply end of the clock chip is connected to the first end of the eleventh capacitor and the second output end of the power supply module; the clock output end of the clock chip is connected to the control module; the clock chip is connected to the control module through the serial interface; The second end of the ninth capacitor, the second end of the tenth capacitor, the second end of the eleventh capacitor, and a grounding terminal of the clock chip are grounded.
9. The clock circuit according to claim 5, characterized in that: The first voltage conversion chip uses a ME6211 C33M5G-N chip with an output voltage of 3.3V; The second voltage conversion chip uses an XC6206P301 MR chip with an output voltage of 3V.
10. A clock source device, characterized in that: Comprising the clock circuit described in any one of claims 1-9.