Array substrate and display panel

Abstract

The utility model discloses an array substrate and a display panel, the display panel is provided with a display area and a fan-out area, and the array substrate comprises a substrate, a metal shading layer and a thin film transistor layer; the metal shading layer is arranged on one side of the substrate, and the metal shading layer comprises a shading part and a metal wire; the thin film transistor layer is arranged on the side, away from the substrate, of the metal shading layer, and the thin film transistor layer comprises a thin film transistor located in the display area and a driving circuit wire located in the fan-out area; wherein the metal wire is located in the fan-out area and electrically connected with the driving circuit wire through the via hole, the metal wire is of a multi-layer metal structure, the orthographic projection of the channel part of the thin film transistor on the substrate is located in the orthographic projection range of the shading part on the substrate, and the thickness of the shading part is smaller than that of the metal wire.

Description

Technical Field

[0001] The present application relates to the technical field of displays, and particularly relates to an array substrate and a display panel. Background Art

[0002] Currently, LTPS (English full name: Low-temperature polycrystalline silicon, Chinese abbreviation: low-temperature polysilicon) products are widely used in display screens. To improve product performance, the metal signal line impedance of LTPS products is generally reduced in the following ways: one is to increase the thickness of the metal layer, but the reduction of the metal impedance is limited; the second is to increase the parallel metal layer. Although the metal signal line impedance can be reduced, the process is complex and the cost is high; the third is based on the LTPS process, using a metal stack for LS and using LS as a metal trace to reduce the metal signal line impedance; however, since the thickness of LS increases significantly after using the metal stack material, there will be a risk of slope breakage in the subsequent active layer and it will also affect the crystallization process of the active layer. Summary of the Utility Model

[0003] The embodiments of the present application provide an array substrate and a display panel, which can reduce the step difference between the light-shielding portion and the substrate while reducing the metal impedance of the metal light-shielding layer, thereby eliminating the risk of slope breakage in the active layer and facilitating the subsequent crystallization process of the active layer.

[0004] In a first aspect, the embodiments of the present application provide an array substrate for a display panel, where the display panel has a display area and at least a fan-out area located on one side of the display area, and the array substrate includes:

[0005] A substrate;

[0006] A metal light-shielding layer disposed on one side of the substrate, the metal light-shielding layer including a light-shielding portion and a metal trace; and,

[0007] A thin-film transistor layer disposed on the side of the metal light-shielding layer away from the substrate, the thin-film transistor layer including thin-film transistors located in the display area and drive circuit traces located in the fan-out area;

[0008] Wherein, the metal trace is located in the fan-out area and is electrically connected to the drive circuit trace through a via, the metal trace is set as a multi-layer metal structure, the orthographic projection of the channel portion of the thin-film transistor on the substrate is located within the orthographic projection range of the light-shielding portion on the substrate, and the thickness of the light-shielding portion is less than the thickness of the metal trace.

[0009] In one embodiment, the multi-layer metal structure includes a first sub-film layer closest to the substrate side;

[0010] The light-shielding portion is provided as a single-layer metal structure, and in the thickness direction of the array substrate, the thickness of the light-shielding portion is the same as that of the first sub-film layer.

[0011] In one embodiment, the array substrate further includes a buffer layer, the buffer layer is disposed on one side of the substrate, and a first opening and a second opening are provided on the buffer layer, the first opening is located in the display area, and the second opening is located in the fan-out area;

[0012] The light-shielding portion is disposed in the first opening and above the substrate;

[0013] The metal trace is disposed in the second opening and above the substrate;

[0014] Wherein, the thin film transistor layer is disposed on the side of the buffer layer away from the substrate.

[0015] In one embodiment, in the thickness direction of the array substrate, the thickness of the buffer layer is less than that of the light-shielding portion;

[0016] The surface of the light-shielding portion away from the substrate extends beyond the surface of the buffer layer away from the substrate, and the surface of the metal trace away from the substrate extends beyond the surface of the buffer layer away from the substrate.

[0017] In one embodiment, in the thickness direction of the array substrate, the thickness of the buffer layer is the same as that of the light-shielding portion;

[0018] The surface of the light-shielding portion away from the substrate is flush with the surface of the buffer layer away from the substrate, and the surface of the metal trace away from the substrate extends beyond the surface of the buffer layer away from the substrate.

[0019] In one embodiment, in the thickness direction of the array substrate, the thickness of the buffer layer is greater than that of the light-shielding portion and less than that of the metal trace;

[0020] The surface of the light-shielding portion away from the substrate is lower than the surface of the buffer layer away from the substrate, and the surface of the metal trace away from the substrate extends beyond the surface of the buffer layer away from the substrate.

[0021] In one embodiment, the array substrate further includes a planarization layer, the planarization layer is disposed on the side of the buffer layer away from the substrate and covers the light-shielding portion and the metal trace;

[0022] Wherein, the thin film transistor layer is disposed on the side of the planarization layer away from the buffer layer.

[0023] In one embodiment, the material of the metal trace is set as a combined layer of at least two materials among titanium, molybdenum, copper, and aluminum; and / or,

[0024] In the thickness direction of the array substrate, the thickness of the metal trace is greater than and / or;

[0025] In the thickness direction of the array substrate, the thickness of the light-shielding portion is less than or equal to

[0026] In one embodiment, the thin film transistor layer includes a plurality of the thin film transistors arranged in an array. Among the plurality of the thin film transistors, some of the thin film transistors are set as oxide thin film transistors, and some of the thin film transistors are set as low-temperature polycrystalline silicon thin film transistors.

[0027] In a second aspect, an embodiment of the present application further provides a display panel, including the above-mentioned array substrate.

[0028] Beneficial effects: In the array substrate provided by the present application, a metal light-shielding layer is disposed on one side of the substrate, and a thin film transistor layer is disposed on the side of the metal light-shielding layer away from the substrate; the thin film transistor layer includes thin film transistors located in the display area and drive circuit traces located in the fan-out area; the metal light-shielding layer includes a light-shielding portion and a metal trace; the metal trace is located in the fan-out area and is electrically connected to the drive circuit trace via a via, so as to serve as a signal trace in the fan-out area of the array substrate; the metal trace is set as a multi-layer metal structure, so that the thickness of the metal trace is relatively thick and is formed by laminating multiple metal layers, thereby making the metal trace have a lower metal impedance; at the same time, the light-shielding portion is located in the display area and is used to shield the channel portion of the thin film transistor, and the thickness of the light-shielding portion is less than the thickness of the metal trace, so that the step difference between the light-shielding portion and the substrate is relatively small. When the thin film transistor layer is fabricated on the metal light-shielding layer subsequently, the insulating layer covering the thin film transistor can cover the light-shielding portion and fill the step difference, which can not only eliminate the risk of the active layer of the thin film transistor breaking due to climbing, but also reduce the film layer lifting amplitude of the active layer, making the active layer tend to be flat and facilitating the subsequent crystallization process of the active layer. Description of the Drawings

[0029] The following will make the technical solutions and other beneficial effects of the present application obvious by describing the specific embodiments of the present application in detail with reference to the drawings.

[0030] Figure 1 It is the first film layer diagram of the array substrate provided by the embodiment of the present application;

[0031] Figures 2a to 2c is Figure 1 the manufacturing process diagram of the metal light-shielding layer in

[0032] Figure 3 the second film layer diagram of the array substrate provided by the embodiment of the present application;

[0033] Figure 4 the third film layer diagram of the array substrate provided by the embodiment of the present application;

[0034] Figure 5 the fourth film layer diagram of the array substrate provided by the embodiment of the present application;

[0035] Figure 6 the plan view of the display panel provided by the embodiment of the present application. Specific embodiments

[0036] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application.

[0037] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and cannot be construed as a limitation to the present application. And, unless otherwise clearly specified and limited, the fact that the first feature is "above" or "below" the second feature only means that the first feature has a higher horizontal height than the second feature or the first feature has a lower horizontal height than the second feature, and does not indicate a direct connection relationship.

[0038] In addition, the terms "first" and "second" are only used for descriptive purposes, and the features defined with "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, the meaning of "a plurality" is two or more, unless otherwise clearly and specifically defined.

[0039] In the description of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense and the connection method is not specifically limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0040] The following disclosure provides many different embodiments for implementing different structures of the present application. To simplify the disclosure of the present application, components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, various specific examples of processes and materials are provided in the present application, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0041] In a first aspect, an embodiment of the present application provides an array substrate 100 for a display panel 1000. The display panel 1000 has a display area A and at least a fan-out area B located on one side of the display area A. The array substrate 100 includes a substrate 1, a metal light-shielding layer 4, and a thin-film transistor layer 3. The metal light-shielding layer 4 is disposed on one side of the substrate. The metal light-shielding layer 4 includes a light-shielding portion 41 and a metal trace 42. The thin-film transistor layer 3 is disposed on the side of the metal light-shielding layer 4 away from the substrate 1. The thin-film transistor layer 3 includes thin-film transistors 3a located in the display area A and drive circuit traces 3b located in the fan-out area. Among them, the metal trace 42 is located in the fan-out area B and is electrically connected to the drive circuit trace 3b through a via. The metal trace 42 is provided as a multi-layer metal structure. The orthographic projection of the channel portion of the thin-film transistor 3a on the substrate 1 is within the orthographic projection range of the light-shielding portion 41 on the substrate 1, and the thickness of the light-shielding portion 41 is less than the thickness of the metal trace 42.

[0042] In the array substrate 100 provided by the present application, a metal light-shielding layer 4 is disposed on one side of the substrate 1, and a thin-film transistor layer 3 is disposed on the side of the metal light-shielding layer 4 away from the substrate 1; the thin-film transistor layer 3 includes thin-film transistors 3a located in the display area A and driving circuit traces 3b located in the fan-out area B; the metal light-shielding layer 4 includes a light-shielding portion 41 and metal traces 42, and the metal traces 42 are electrically connected to the driving circuit traces 3b via vias, so as to serve as signal traces in the fan-out area B of the array substrate 100; the metal traces 42 are arranged as a multi-layer metal structure, so that the metal traces 42 have a relatively thick thickness and are stacked by multiple metal layers, thereby enabling the metal traces 42 to have a lower metal impedance; at the same time, the light-shielding portion 41 is located in the display area A and is used to shield the channel portion of the thin-film transistor 3a, and the light-shielding portion 41 is smaller than the thickness of the metal traces 42, so that the step difference H1 between the light-shielding portion 41 and the substrate 1 is smaller. When the thin-film transistor layer 3 is fabricated on the metal light-shielding layer 4 subsequently, the insulating layer covering the thin-film transistor 3a will cover the light-shielding portion 41 and fill in the step difference H1, which can not only eliminate the risk of the active layer 31 of the thin-film transistor 3a breaking due to slope, but also reduce the film layer lifting amplitude of the active layer 31, making the active layer 31 tend to be flat and facilitating the subsequent crystallization process of the active layer 31.

[0043] The present application does not specifically limit the material of the metal traces 42. The material of the metal traces 42 is set as a combined layer of at least two materials among titanium, molybdenum, copper, and aluminum. For example, the material of the metal traces 42 can be set as laminated metal materials such as Mo-Al-Mo, Ti-Al-Ti, Mo-Cu-Mo, Ti-Cu-Ti, Al-Mo, Al-Ti, Cu-Mo, and Cu-Ti.

[0044] Moreover, taking "the material of the metal light-shielding layer 4 is set as Mo-Al-Mo" as an example, the thickness of the bottom Mo layer closest to the substrate 1 is usually set as The thickness of the Al layer located in the middle layer is usually set as The thickness of the top Mo layer farthest from the substrate 1 is usually set as The metal traces 42 are arranged as a multi-layer metal structure of Mo-Al-Mo, and the light-shielding portion 41 is arranged as a single-layer metal structure with only the bottom Mo layer retained; at this time, in the thickness direction of the array substrate 100, the thickness of the light-shielding portion 41 is less than or equal to

[0045] Meanwhile, taking "the material of the metal light-shielding layer 4 is set as Mo-Al-Mo" as an example, the metal trace 42 is set as a multi-layer metal structure of Mo-Al-Mo. In the thickness direction of the array substrate 100, the total thickness of the metal trace 42 is set to be greater than

[0046] It should be noted that the above three technical features can be set selectively, or two of them can be set, or all of them can be set simultaneously. In an embodiment of the present application, the above three technical features are set simultaneously. In this way, the metal impedance of the metal trace 42 can be effectively reduced.

[0047] Taking "the material of the metal light-shielding layer 4 is set as Mo-Al-Mo" as an example for illustration; the metal light-shielding layer 4 includes a bottom Mo layer closest to the substrate 1, an Al layer in the middle layer, and a top Mo layer farthest from the substrate 1. The metal trace 42 is set as a multi-layer metal structure of Mo-Al-Mo; the light-shielding portion 41 is set as a single-layer metal structure that only retains the bottom Mo layer; that is to say, in the metal trace 42, the first sub-film layer closest to the substrate side is set as the bottom Mo layer, and the thickness of the light-shielding portion is the same as the thickness of the first sub-film layer.

[0048] Please refer to Figure 1 , Figure 1 which is the first embodiment provided by the present application. In this embodiment, the metal light-shielding layer 4 is disposed on one side of the substrate 1; the array substrate 100 further includes a buffer layer 2, and the buffer layer 2 is disposed on one side of the substrate 1 and covers the metal light-shielding layer 4; the thin-film transistor layer 3 is disposed on the side of the buffer layer 2 away from the substrate 1.

[0049] In this embodiment, please refer to Figure 2a , Figure 2b and Figure 2c, a substrate 1 is provided; a multi-layer metal structure is fabricated on one side surface of the substrate 1 to form the metal light-shielding layer 4; a photoresist layer 6 is fabricated on the metal light-shielding layer 4, and the photoresist layer 6 is exposed and developed using a halftone mask 7 as a mask to pattern the photoresist layer 6. Among them, the photoresist layer 6 includes a first photoresist pattern 61 and a second photoresist pattern 62, and the thickness of the first photoresist pattern 61 is less than the thickness of the second photoresist pattern 62; the metal light-shielding layer 4 is etched, the part of the metal light-shielding layer 4 not covered by the photoresist pattern is etched away, the metal light-shielding layer 4 covered by the second photoresist pattern 62 forms the metal trace 42, and the part of the metal light-shielding layer 4 covered by the first photoresist pattern 61 is partially etched to form the light-shielding portion 41, and the light-shielding portion 41 is a single-layer metal structure; taking "the material of the metal light-shielding layer 4 is set as Mo-Al-Mo" as an example, the metal trace 42 is a single layer of Mo-Al-Mo laminated metal, and the light-shielding portion 41 only remains a single-layer metal structure of the bottom Mo layer.

[0050] At this time, the thickness of the light-shielding portion 41 is the thickness of the bottom Mo layer, that is Since the film thickness of the light-shielding portion 41 is small, the step difference H1 between the light-shielding portion 41 and the substrate 1 is small; after the buffer layer 2 is fabricated on the substrate 1, the buffer layer 2 will fill in the step difference H1, so that the surface of the buffer layer 2 away from the substrate 1 tends to be flat. When the thin-film transistor layer 3 is fabricated on the surface of the buffer layer 2 away from the substrate 1, the risk of the active layer 31 of the thin-film transistor 3a breaking due to slope can be eliminated; at the same time, when the active layer 31 is fabricated on the relatively flat buffer layer 2, the film layer lifting amplitude of the active layer 31 can be greatly reduced, making the active layer 31 tend to be flat, which is convenient for the subsequent crystallization process of the active layer 31.

[0051] Please refer to Figures 3 to 6 , Figures 3 to 6 are the second to fourth embodiments provided by this application. Different from the first embodiment, in these embodiments, the array substrate 100 further includes a buffer layer 2, and the buffer layer 2 is disposed on one side of the substrate 1; a first opening 21 and a second opening 22 are provided on the buffer layer 2, the first opening 21 is located in the display area A, and the second opening 22 is located in the fan-out area B; the light-shielding portion 41 is disposed in the first opening 21 and above the substrate 1; the metal trace 42 is disposed in the second opening 22 and above the substrate 1; wherein, the thin-film transistor layer 3 is disposed on the side of the buffer layer 2 away from the substrate 1.

[0052] In this embodiment, a first opening 21 and a second opening 22 are provided on the buffer layer 2. By filling the light-shielding portion 41 into the first opening 21, the step difference H2 between the light-shielding portion 41 and the surface of the buffer layer 2 is reduced. When the thin-film transistor layer 3 is fabricated on the buffer layer 2, the insulating layer covering the thin-film transistor 3a on the thin-film transistor layer 3 will fill in this step difference H2, thereby eliminating the risk of the active layer 31 of the thin-film transistor 3a breaking due to slope, and making the active layer 31 disposed thereon also tend to be flat, which is convenient for subsequent crystallization treatment of the active layer 31.

[0053] This application does not specifically limit the state of the light-shielding portion 41 in the first opening 21. The light-shielding portion 41 may be higher than the first opening 21, the light-shielding portion 41 may be flush with the first opening 21, and the light-shielding portion 41 may also be lower than the first opening 21.

[0054] Please refer to Figure 3 , in the second embodiment of this application, in the thickness direction of the array substrate 100, the thickness of the buffer layer 2 is less than the thickness of the light-shielding portion 41; the light-shielding portion 41 is located in the first opening 21, and the surface of the light-shielding portion 41 on the side away from the substrate 1 extends beyond the surface of the buffer layer 2 on the side away from the substrate 1, and the surface of the metal trace 42 on the side away from the substrate 1 extends beyond the surface of the buffer layer 2 on the side away from the substrate 1.

[0055] Different from the first embodiment, in the second embodiment, the buffer layer 2 is fabricated on one side surface of the substrate 1; the first opening 21 and the second opening 22 are provided on the buffer layer 2, and a multi-layer metal structure is fabricated on the surface of the buffer layer 2 on the side away from the substrate 1 as the metal light-shielding layer 4; using the method in the first embodiment, the metal light-shielding layer 4 is patterned to form the light-shielding portion 41 located in the first opening 21 and the metal trace 42 located in the second opening 22.

[0056] By filling the light-shielding portion 41 into the first opening 21, the distance between the surface of the light-shielding portion 41 on the side away from the substrate 1 and the surface of the buffer layer 2 on the side away from the substrate 1 is reduced, thereby further reducing the step difference H2 between the light-shielding portion 41 and the surface of the buffer layer 2. When the thin-film transistor layer 3 is fabricated on the buffer layer 2, the insulating layer covering the thin-film transistor 3a on the thin-film transistor layer 3 will fill in this step difference H2, thereby eliminating the risk of the active layer 31 of the thin-film transistor 3a breaking due to slope, and making the active layer 31 disposed thereon also tend to be flat, which is convenient for subsequent crystallization treatment of the active layer 31.

[0057] Please refer to Figure 4 , in the third embodiment of the present application, in the thickness direction of the array substrate 100, the thickness of the buffer layer 2 is the same as that of the light-shielding portion 41; the light-shielding portion 41 is located within the first opening 21, and the surface of the light-shielding portion 41 away from the substrate 1 is flush with the surface of the buffer layer 2 away from the substrate 1, and the surface of the metal trace 42 away from the substrate 1 extends beyond the surface of the buffer layer 2 away from the substrate 1.

[0058] Different from the second embodiment, in the third embodiment, by setting the thickness of the buffer layer 2 to be the same as that of the light-shielding portion 41, the light-shielding portion 41 can be completely filled in the first opening 21, so that without increasing the film layer thickness, the surface of the buffer layer 2 away from the substrate 1 tends to be flattened, that is, there is no step difference between the surfaces of the light-shielding portion 41 and the buffer layer 2. When manufacturing the thin-film transistor layer 3 on the buffer layer 2, the risk of the active layer 31 of the thin-film transistor 3a climbing and breaking can be eliminated, and the active layer 31 disposed thereon also tends to be flat, thereby facilitating the subsequent crystallization process of the active layer 31.

[0059] Please refer to Figure 5 , in the fourth embodiment of the present application, in the thickness direction of the array substrate 100, the thickness of the buffer layer 2 is greater than that of the light-shielding portion 41 and less than that of the metal trace 42; the light-shielding portion 41 is located within the first opening 21, and the surface of the light-shielding portion 41 away from the substrate 1 is lower than the surface of the buffer layer 2 away from the substrate 1; the metal trace 42 is located within the second opening 22, and the surface of the metal trace 42 away from the substrate 1 extends beyond the surface of the buffer layer 2 away from the substrate 1.

[0060] Different from the second embodiment, in the fourth embodiment, by setting the thickness of the buffer layer 2 to be greater than that of the light-shielding portion 41, the light-shielding portion 41 is completely filled; when subsequently manufacturing the thin-film transistor layer 3 on the metal light-shielding layer 4, the insulating layer covering the thin-film transistor 3a will fill the first opening 21, thereby completely eliminating the step difference H2 between the light-shielding portion 41 and the buffer layer 2, which can not only eliminate the risk of the active layer 31 of the thin-film transistor 3a climbing and breaking; but also can reduce the film layer lifting amplitude of the active layer 31, making the active layer 31 tend to be flat and facilitating the subsequent crystallization process of the active layer 31.

[0061] The present application does not specifically limit the structure of the thin film transistor 3a. In some embodiments, the thin film transistor 3a may be a top-gate structure; in other embodiments, the thin film transistor 3a may be a bottom-gate structure.

[0062] Taking the top-gate structure as an example for illustration, the thin film transistor layer 3 further includes a gate insulating layer 32 covering the gate of the thin film transistor 3a and a first interlayer insulating layer 34; an active layer 31 is disposed on the side of the buffer layer 2 away from the substrate 1; the gate insulating layer 32 is disposed on the active layer 31; a first metal layer 33 is disposed on the gate insulating layer 32, and the first metal layer 33 includes a gate 331 located in the display area A and a driving circuit trace 3b located in the fan-out area B; the first interlayer insulating layer 34 is disposed on the gate insulating layer 32, and the first interlayer insulating layer 34 covers the gate 331 and the driving circuit trace 3b; a second metal layer 35 is disposed on the first interlayer insulating layer 34, and the second metal layer 35 includes a source electrode 351 and a drain electrode 352; a first via 321 is formed in the gate insulating layer 32, a second via 341 and a third via 342 are formed in the first interlayer insulating layer 34, the positions of the first via 321 and the third via 342 correspond to each other and are interconnected, and the second metal layer 35 is electrically connected to the metal trace 42 via the first via 321 and the third via 342, and the second metal layer 35 is electrically connected to the driving circuit trace 3b through the second via 341.

[0063] Among them, the active layer 31, the gate insulating layer 32, the gate 331, the first interlayer insulating layer 34, the source electrode 351, and the drain electrode 352 constitute the thin film transistor 3a.

[0064] A second interlayer insulating layer 36 is further disposed on the side of the first interlayer insulating layer 34 away from the substrate, and the second interlayer insulating layer 36 covers the second metal layer 35; a pixel electrode layer 37 is disposed on the side of the second interlayer insulating layer 36 away from the first interlayer insulating layer 34, and the pixel electrode layer 37 is electrically connected to the drain electrode 352 through a fourth via 361.

[0065] As described above, in an embodiment of the present application, the array substrate 100 further includes a planarization layer 5, the planarization layer 5 is disposed on the side of the buffer layer 2 away from the substrate 1 and covers the light-shielding portion 41 and the metal trace 42, and the thin film transistor layer 3 is disposed on the side of the planarization layer 5 away from the buffer layer 2.

[0066] Moreover, a planarization layer 5 is disposed between the buffer layer 2 and the thin film transistor layer 3. On the one hand, it can planarize the metal light-shielding layer 4 on the buffer layer 2 to eliminate the risk of the active layer 31 breaking due to slope; on the other hand, it can isolate the metal light-shielding layer 4 from the active layer 31 of the thin film transistor 3a.

[0067] It should be noted that the array substrate 100 provided in the embodiment of the present application is applicable to an LTPS (English full name: Low Temperature Poly-Silicon, Chinese abbreviation: low temperature polycrystalline silicon) display panel; that is, the thin film transistor layer 3 includes a plurality of the thin film transistors 3a distributed in an array. Among the plurality of the thin film transistors 3a, some of the thin film transistors 3a are oxide thin film transistors 3a, and some of the thin film transistors 3a are low temperature polycrystalline silicon thin film transistors 3a.

[0068] It can be known that based on the manufacturing process of LTPS products, after optimizing by reducing the process temperature, the material of the gate 331 is changed to a metal stack structure such as Mo, Ti, Al, Cu, etc., so as to achieve the purpose of reducing the metal impedance; then the metal trace 42 is fabricated by using a stacked multi-layer metal film layer, thereby greatly reducing the metal impedance of the metal trace 42, and using the metal trace 42 as the signal line in the fan-out region B, so as to improve the product performance while saving photomasks and reducing production costs; and by thinning the film layer of the light-shielding portion 41 or filling the light-shielding portion 41, on the basis of reducing the metal impedance, the step difference between the light-shielding portion 41 and the substrate 1 can be reduced. Furthermore, when fabricating the thin film transistor 3a subsequently, not only can the risk of the active layer 31 breaking due to slope be eliminated; but also the film layer lift of the active layer 31 can be reduced, making the active layer 31 tend to be planarized, which is convenient for the subsequent crystallization process of the active layer 31.

[0069] In a second aspect, an embodiment of the present application further provides a display panel 1000. The display panel 1000 has a display area A and at least a fan-out area B located on one side of the display area A. The display panel 1000 includes an array substrate 100. The array substrate 100 has a metal light-shielding layer 4. The metal light-shielding layer 4 includes a light-shielding portion 41 and a metal trace 42. The metal trace 42 is located in the fan-out area B and is electrically connected to the thin film transistor 3a of the array substrate 100 through a via hole.

[0070] It should be noted that the array substrate 100 is set as the above-mentioned array substrate 100, that is to say, the array substrate 100 includes all the technical features of the above-mentioned array substrate 100, and the display panel includes all the embodiments of the above-mentioned array substrate 100. The metal trace 42 of the array substrate 100 is electrically connected to the thin film transistor 3a via a via, so as to serve as a signal trace in the fan-out region B of the array substrate 100; at the same time, the metal trace 42 is set as a multi-layer metal structure, so that the metal trace 42 has a relatively thick thickness and is arranged in parallel by multiple metal layers, thereby enabling the metal trace 42 to have a lower metal impedance; and, the thickness of the light-shielding portion 41 is less than the thickness of the metal trace 42. When the thin film transistor layer 3 is fabricated subsequently, the insulating layer covering the thin film transistor 3a can cover and fill the light-shielding portion 41. In this way, the risk of the active layer 31 breaking due to slope can be eliminated, and the crystallization process of the active layer 31 can be facilitated subsequently.

[0071] The above has introduced in detail an array substrate and a display panel provided by an embodiment of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate for a display panel, the display panel having a display area and a fan-out area at least located on one side of the display area, characterized in that: The array substrate comprises: substrate; a metal light shielding layer, disposed on one side of the substrate, the metal light shielding layer comprising a light shielding portion and a metal wiring; and A thin film transistor layer, arranged on a side of the metal light shielding layer away from the substrate, the thin film transistor layer comprising thin film transistors located in the display area and drive circuit wiring located in the fan-out area; Among them, the metal routing is located in the fan-out area and is electrically connected to the driving circuit routing through a via, the metal routing is arranged as a multi-layer metal structure, the orthographic projection of the channel portion of the thin film transistor on the substrate is located within the orthographic projection range of the shading portion on the substrate, and the thickness of the shading portion is less than the thickness of the metal routing.

2. The array substrate according to claim 1, characterized in that: The multi-layer metal structure includes a first sub-film layer closest to a side of the substrate; The light shielding portion is configured as a single-layer metal structure, and in the thickness direction of the array substrate, the thickness of the light shielding portion is the same as the thickness of the first sub-film layer.

3. The array substrate according to claim 1, characterized in that: The array substrate further comprises a buffer layer, the buffer layer is arranged on one side of the substrate, a first opening and a second opening are arranged on the buffer layer, the first opening is located in the display area, and the second opening is located in the fan-out area; The light shielding portion is disposed in the first opening and located on the substrate; The metal trace is disposed in the second opening and is located on the substrate; Wherein, the thin film transistor layer is arranged on a side of the buffer layer away from the substrate.

4. The array substrate according to claim 3, characterized in that: In the thickness direction of the array substrate, the thickness of the buffer layer is smaller than the thickness of the light shielding portion; A side surface of the light shielding portion away from the substrate is arranged beyond a side surface of the buffer layer away from the substrate, and a side surface of the metal wiring away from the substrate is arranged beyond a side surface of the buffer layer away from the substrate.

5. The array substrate according to claim 3, characterized in that: In the thickness direction of the array substrate, the thickness of the buffer layer is the same as the thickness of the light shielding portion; A surface of the light shielding portion away from the substrate is flush with a surface of the buffer layer away from the substrate, and a surface of the metal wiring away from the substrate is disposed beyond a surface of the buffer layer away from the substrate.

6. The array substrate according to claim 3, characterized in that: In the thickness direction of the array substrate, the thickness of the buffer layer is greater than the thickness of the light shielding portion and less than the thickness of the metal wiring; A surface of the light shielding portion away from the substrate is arranged lower than a surface of the buffer layer away from the substrate, and a surface of the metal wiring away from the substrate is arranged beyond a surface of the buffer layer away from the substrate.

7. The array substrate according to any one of claims 4 to 6, characterized in that: The array substrate further comprises a flat layer, which is arranged on a side of the buffer layer away from the substrate and covers the light shielding portion and the metal wiring; Wherein, the thin film transistor layer is arranged on a side of the planar layer away from the buffer layer.

8. The array substrate according to claim 1, wherein: The material of the metal wiring is set to a composite layer of at least two materials selected from titanium, molybdenum, copper and aluminum; and / or, In the thickness direction of the array substrate, the thickness of the metal trace is greater than and / or; In the thickness direction of the array substrate, the thickness of the light shielding portion is less than or equal to 9. The array substrate according to claim 1, wherein: The thin film transistor layer includes a plurality of thin film transistors arranged in an array. Among the plurality of thin film transistors, some of the thin film transistors are configured as oxide thin film transistors, and some of the thin film transistors are configured as low-temperature polysilicon thin film transistors.

10. A display panel, characterized in that: It comprises an array substrate as described in any one of claims 1 to 9.

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