Monolithic integrated silicon optical chip and photoelectric integrated system
By setting side by side end-face couplers and coupling grooves in the silicon optical passive device, the precise alignment of the light source and the end-face couplers is achieved, which solves the problems of low coupling accuracy and complex packaging of silicon optical chips, and is suitable for large-scale photoelectric integration.
Patent Information
- Application Number
- CN202422115264.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2025-07-01
- Estimated Expiration
- 2034-08-29
AI Technical Summary
The existing silicon optical chips have low coupling accuracy and complex packaging, making it difficult to meet the needs of large-scale photoelectric integration.
The monolithic integrated silicon optical chip design is adopted. By providing side-by-side end-face couplers and coupling grooves in the silicon optical passive device, the light emitting part of the light source is fitted into the coupling grooves, so as to achieve precise alignment between the light source and the end-face couplers and avoid the packaging process.
The coupling accuracy between the light source and the silicon optical passive device is improved, and the structure is more compact, suitable for large-scale photoelectric integration without additional packaging.
Smart Images
Figure CN223051536U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of optoelectronic integration technology, and particularly to a monolithic integrated silicon photonic chip and an optoelectronic integration system. Background Art
[0002] The silicon-based photon integration process is compatible with the complementary metal oxide semiconductor process. Using this technology, silicon photonic chips can be fabricated on large silicon substrates, making the fabricated silicon photonic chips have the advantages of low cost, suitability for large-scale production, and high integration. Therefore, the silicon-based photon integration process is considered to be the best solution for realizing optical interconnection. The silicon-based photon integration process refers to integrating various photonic devices together using optical waveguides to form a silicon photonic chip.
[0003] Silicon photonic chips can be divided into off-chip integrated silicon photonic chips and on-chip integrated silicon photonic chips. Due to the problem of low coupling accuracy of on-chip integrated silicon photonic chips, off-chip integrated silicon photonic chips are currently widely used. In the off-chip integration scheme, a relatively mature external light source is usually used as the input of the device, and the light wave of the external light source needs to be end-coupled with an end-face coupler using an external optical fiber so that the light wave of the light source enters the waveguide of the silicon photonic chip. In the coupling scheme of off-chip integration, the coupling tolerance between the optical fiber and the end-face coupler is small and the coupling accuracy is not high. And because the light source is external, the off-chip integration scheme needs to mechanically package and integrate the external light source and the optical fiber with other parts of the silicon photonic chip (such as the end-face coupler). This kind of packaging is relatively complex and not conducive to large-scale optoelectronic integration. Therefore, there is a need for a silicon photonic chip with high coupling accuracy and low packaging difficulty currently. Summary of the Utility Model
[0004] The purpose of the embodiments of this application is to provide a monolithic integrated silicon photonic chip and an optoelectronic integration system, which can realize the precise alignment of the light source and the end-face coupler, effectively improve the coupling accuracy; also make the structure more compact, and there is no need to package the light source and silicon passive devices.
[0005] On one hand, an embodiment of this application provides a monolithic integrated silicon photonic chip, including a silicon photonic passive device and a light source. The light source is located on one side of the silicon photonic passive device along a first direction; a end-face coupler and a coupling groove are arranged in the silicon photonic passive device. The coupling groove and the end-face coupler are arranged side by side along the first direction. In the stacking direction, the top surface of the coupling groove and the top surface of the end-face coupler are coplanar, and the bottom surface of the coupling groove and the bottom surface of the end-face coupler are coplanar. The light-emitting part of the light source is embedded in the coupling groove so that the light-emitting part and the end-face coupler are coupled. The first direction is perpendicular to the stacking direction.
[0006] Optionally, the size of the light source in the second direction gradually increases from the end close to the end-face coupler to the end far from the end-face coupler, so that the light source forms a cone on the top view plane formed by the first direction and the second direction, and the second direction is perpendicular to the first direction and the stacking direction respectively.
[0007] Optionally, the silicon photonic passive device includes a substrate, a first dielectric layer, a waveguide device, a second dielectric layer, the end-face coupler, and a third dielectric layer sequentially arranged along the stacking direction. The second dielectric layer covers the waveguide device and spaces the waveguide device from the end-face coupler. The third dielectric layer covers the end-face coupler and the coupling groove, and laterally spaces the end-face coupler from the coupling groove.
[0008] Optionally, the silicon photonic passive device further includes a trench. The trench communicates with the notch of the coupling groove and is located at the end of the silicon photonic passive device facing the light source along the first direction. The light source further includes a light source body, and the light source body is disposed in the trench.
[0009] Optionally, in the stacking direction, the trench extends from the top surface of the third dielectric layer into or onto the substrate, and the top surface of the light source body in the stacking direction is lower than the top surface of the third dielectric layer.
[0010] Optionally, in the first direction, the width of the substrate is greater than the widths of the first dielectric layer, the second dielectric layer, and the third dielectric layer, and the light source body of the light source contacts the side walls of the first dielectric layer, the second dielectric layer, and the third dielectric layer stacked in sequence.
[0011] Optionally, the silicon photonic passive device includes at least two of the waveguide devices. At least two of the waveguide devices are arranged side by side in the first direction. In the stacking direction, the top surfaces of at least two of the waveguide devices are coplanar, and the bottom surfaces of at least two of the waveguide devices are coplanar.
[0012] Optionally, the substrate at least includes a silicon substrate, the first dielectric layer, the second dielectric layer, and the third dielectric layer all at least include a silicon dioxide dielectric layer, the waveguide device at least includes a silicon waveguide device, and the end-face coupler at least includes a silicon nitride end-face coupler.
[0013] Optionally, the light source at least includes a laser.
[0014] On the other hand, an embodiment of the present application provides an optoelectronic integrated system, including: the monolithic integrated silicon photonic chip described above.
[0015] The monolithic integrated silicon photonic chip and optoelectronic integrated system provided by the embodiments of the present application achieve precise alignment between the light-emitting part of the light source and the end-face coupler by arranging an end-face coupler and a coupling groove side by side in the first direction within the silicon photonic passive device, and in the stacking direction, the top surfaces and bottom surfaces of both the end-face coupler and the coupling groove are coplanar. In this way, when the light source and the silicon photonic passive device are coupled, the optical signal emitted by the light-emitting part can be accurately coupled into the end-face coupler, effectively improving the coupling accuracy between the light source and the silicon photonic passive device. Additionally, it can make the structure more compact and eliminate the need for packaging the light source and the silicon photonic passive device, making it suitable for large-scale optoelectronic integration. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without creative efforts.
[0017] Figure 1a is a schematic structural diagram of the monolithic integrated silicon photonic chip provided in the first embodiment;
[0018] Figure 1b is a schematic structural diagram of the monolithic integrated silicon photonic chip provided in the second embodiment;
[0019] Figure 2 is Figure 1a the top view of;
[0020] Figures 3 to 9 is a schematic diagram of the manufacturing process of the monolithic integrated silicon photonic chip provided in the first embodiment.
[0021] Reference numerals: 10A - silicon photonic passive device; 10 - substrate; 11a - first dielectric layer; 11b - second dielectric layer; 11c - third dielectric layer; 12 - waveguide device; 13 - SiN layer; 13a - end-face coupler; 13b - pseudo-structure; 13c - coupling groove; 14 - trench; 20 - light source; 21 - light-emitting part; 22 - light source body; F1 - first direction; F2 - second direction; D - stacking direction; S - axis; d - thickness. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application.
[0023] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "inner" and "outer" is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of this application is usually placed during use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. In addition, terms such as "first" and "second" are only used for differential description and cannot be construed as indicating or implying relative importance.
[0024] It should also be noted that unless otherwise clearly specified and defined, the terms "arranged" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.
[0025] Aiming at the problems of low coupling accuracy, complex packaging and low integration of traditional off-chip integrated silicon photonic chips, an embodiment of the present application provides a monolithic integrated silicon photonic chip. Please refer to Figure 1a as shown, which includes: a silicon photonic passive device 10A and a light source 20. The light source 20 is located on one side of the silicon photonic passive device 10A along the first direction F1. An end face coupler 13a and a coupling groove 13c are arranged in the silicon photonic passive device 10A. The coupling groove 13c and the end face coupler 13a are arranged side by side along the first direction F1. Along the stacking direction D, the top surface of the coupling groove 13c is coplanar with the top surface of the end face coupler 13a, and at the same time, the bottom surface of the coupling groove 13c is coplanar with the bottom surface of the end face coupler 13a. The light emitting part 21 of the light source 20 is fitted into the coupling groove 13c so that the light emitting part 21 and the end face coupler 13a are coupled; wherein, the first direction F1 is perpendicular to the stacking direction D.
[0026] The silicon photonics passive device 10A and the light source 20 adopt an end-face coupling method. A coupling groove 13c and an end-face coupler 13a are arranged in the silicon photonics passive device 10A, so that in the stacking direction D, the top surface of the coupling groove 13c is flush with the top surface of the end-face coupler 13a, and the bottom surface of the coupling groove 13c is flush with the bottom surface of the end-face coupler 13a. In this way, the light-emitting part 21 of the light source 20 located in the coupling groove 13c and the end-face coupler 13a can be accurately aligned, and the light field is limited in the coupling groove 13c, so that the coupling accuracy between the light source 20 and the end-face coupler 13a is controlled at the nanometer level. When the light source 20 is coupled with the silicon photonics passive device 10A, the optical signal emitted by the light-emitting part 21 can be accurately coupled into the end-face coupler 13a, effectively improving the coupling accuracy between the light source 20 and the silicon photonics passive device 10A. At the same time, the structure can be made more compact, and there is no need to package the light source 20 and the silicon photonics passive device 10A, which is suitable for large-scale optoelectronic integration.
[0027] Since the light-emitting part 21 of the light source 20 is embedded in the coupling groove 13c, in order to accurately align the light-emitting part 21 with the end-face coupler 13a, that is, it is necessary to accurately align the coupling groove 13c with the end-face coupler 13a; Figure 1a 、 Figure 8 It can be seen that the bottom surface and the top surface of the coupling groove 13c are respectively in the same plane as the bottom surface and the top surface of the end-face coupler 13a, that is, in the stacking direction D, the top surface of the coupling groove 13c is coplanar with the top surface of the end-face coupler 13a, and the bottom surface of the coupling groove 13c is coplanar with the bottom surface of the end-face coupler 13a. Thus, the top surface of the coupling groove 13c is aligned with the top surface of the end-face coupler 13a in the first direction F1, and the bottom surface of the coupling groove 13c is aligned with the bottom surface of the end-face coupler 13a in the first direction F1. Correspondingly, in the stacking direction D, the height of the coupling groove 13c is the same as the thickness of the end-face coupler 13a. That is to say, the thickness of the light-emitting part 21 is the same as the thickness of the end-face coupler 13a. In addition, in the top view plane formed by the first direction F1 and the second direction F2, the central axis of the coupling groove 13c and the central axis of the end-face coupler 13a are also coaxial along the first direction F1 (refer to Figure 2 ). In other words, in the Figure 1a side view plane, Figure 2 in the top view plane, the coupling groove 13c and the end-face coupler 13a are both aligned in the first direction F1 to achieve accurate alignment in three-dimensional space.
[0028] In some embodiments, the light source 20 includes a light source body 22 and a light emitting portion 21 connected to the light source body 22. In the first direction F1, the light emitting portion 21 is located between the light source body 22 and the end face coupler 13a. In some embodiments, the light source body 22 of the light source 20 is located on one side of the silicon photonic passive device 10A along the first direction F1, and the light emitting portion 21 of the light source 20 is fitted in the coupling groove 13c. In Figure 1a the illustrated embodiment, the light source body 22 and the light emitting portion 21 are integrally formed. In some embodiments, the light source 20 may be a laser, such as a quantum dot laser or other lasers.
[0029] Figure 2 is Figure 1a a top plan view, and the top plane where the top plan view is located is formed by the first direction F1 and the second direction F2. The dimension of the light source 20 along the second direction F2 gradually increases from the end close to the end face coupler 13a to the end far from the end face coupler 13a, so that the light source 20 forms a cone on the top plane; wherein, the second direction F2 is perpendicular to the first direction F1 and the stacking direction D respectively.
[0030] The light source 20 forms Figure 2 the cone shown in the figure. Correspondingly, the end face coupler 13a also forms a cone by reducing the width of the waveguide tip to match the incident mode of the light source 20, thereby expanding the mode distribution outside the waveguide core (or called the mode field distribution). It is not difficult to understand that a waveguide (not shown) is connected to the end of the end face coupler 13a far from the light source 20 to further transmit the optical signal coupled into the end face coupler 13a.
[0031] Exemplarily, Figure 2 on the top plane shown in the figure and along the second direction F2, the end with a smaller width of the light emitting portion 21 of the light source 20 (i.e., the end close to the end face coupler 13a) corresponds to the end with a smaller width of the end face coupler 13a (i.e., the end close to the light source 20) and the dimensions are equal or substantially equal, so as to facilitate the matching of the light source 20 and the end face coupler 13a, and thus it is convenient to couple the optical signal into the end face coupler 13a. In addition, the tapers of the cones formed by the light source 20 and the end face coupler 13a on the top plane are also equal or substantially equal.
[0032] Still referring to Figure 1a, for the silicon photonics passive device 10A, it specifically includes a substrate 10, a first dielectric layer 11a, a waveguide device 12, a second dielectric layer 11b, an end face coupler 13a, and a third dielectric layer 11c arranged in sequence along the stacking direction D; among them, the second dielectric layer 11b also covers the waveguide device 12 and separates the waveguide device 12 from the end face coupler 13a, and the third dielectric layer 11c also covers the end face coupler 13a and the light-emitting part 21 in the coupling groove 13c and laterally separates the end face coupler 13a and the coupling groove 13c. That is to say, the substrate 10 is located at the bottom layer, the first dielectric layer 11a is arranged above the substrate 10, and the waveguide device 12 is formed above the first dielectric layer 11a. Figure 1a In Figure 1a , the waveguide device 12 does not completely cover the first dielectric layer 11a in the first direction F1, that is, a part of the first dielectric layer 11a is exposed; the second dielectric layer 11b is arranged on the waveguide device 12, and the second dielectric layer 11b completely covers the waveguide device 12 to facilitate isolation of the waveguide device 12, and the second dielectric layer 11b is also connected to the exposed part of the first dielectric layer 11a; the end face coupler 13a and the light-emitting part 21 in the coupling groove 13c are arranged on the second dielectric layer 11b with a lateral spacing. It is not difficult to understand that in order to ensure the precise alignment of the end face coupler 13a and the light-emitting part 21 in the coupling groove 13c, the top surface of the second dielectric layer 11b is flat, so that the bottom surface of the end face coupler 13a and the bottom surface of the light-emitting part 21 are coplanar, and the end face coupler 13a and the pseudo-structure 13b (see, for example, Figure 5 ) mentioned later have the same thickness. Figure 1a In Figure 1a , the end face coupler 13a and the light-emitting part 21 do not completely cover the second dielectric layer 11b in the first direction F1 (that is, a part of the second dielectric layer 11b is exposed), but are located on the side of the second dielectric layer 11b close to the light source 20. The third dielectric layer 11c is formed on the end face coupler 13a and the light-emitting part 21 in the coupling groove 13c. The third dielectric layer 11c completely covers the end face coupler 13a and the light-emitting part 21 in the coupling groove 13c, and the third dielectric layer 11c also fills the gap between the end face coupler 13a and the coupling groove 13c to isolate the light-emitting part 21 in the end face coupler 13a and the coupling groove 13c. The third dielectric layer 11c is also connected to the exposed part of the second dielectric layer 11b below. In this way, the first dielectric layer 11a, the second dielectric layer 11b, and the third dielectric layer 11c are sequentially stacked and connected; while the waveguide device 12 is formed between the first dielectric layer 11a and the second dielectric layer 11b, and the end face coupler 13a and the light-emitting part 21 in the coupling groove 13c are formed between the second dielectric layer 11b and the third dielectric layer 11c. Through the above settings, a hierarchical stacking structure of the silicon photonics passive device 10A along the stacking direction D is formed.
[0033] As can be seen from the above, since both the end face coupler 13a and the coupling groove 13c are provided on the flat top surface of the second dielectric layer 11b, the bottom surfaces and top surfaces of the coupling groove 13c and the end face coupler 13a are coplanar. In this way, the light emitting part 21 in the coupling groove 13c can be accurately aligned with the end face coupler 13a, so the coupling accuracy is high, and the technical problem of low coupling accuracy caused by vertically aligning an external optical fiber with the end face coupler as in the prior art is avoided.
[0034] Furthermore, in the stacking direction D, the waveguide device 12 and the end face coupler 13a are isolated by the second dielectric layer 11b, which can ensure the normal operation of the waveguide device 12 and the end face coupler 13a without interference; in the first direction F1, the end face coupler 13a and the light emitting part 21 in the coupling groove 13c are isolated by the third dielectric layer 11c to ensure the normal operation of the end face coupler 13a and the light emitting part 21 embedded in the coupling groove 13c respectively and avoid interference.
[0035] Exemplarily, please refer to Figure 1a , in the first direction F1, the widths (dimensions in the first direction F1) of the third dielectric layer 11c, the second dielectric layer 11b, and the first dielectric layer 11a are equal, and the width of the substrate 10 is greater than the widths of the first dielectric layer 11a to the third dielectric layer 11c to facilitate the setting of the light source 20 on the substrate 10.
[0036] In the second direction F2, the width of the first dielectric layer 11a can be equal to the width of the substrate 10, which is specifically set according to actual needs; similarly, in the second direction F2, the width of the waveguide device 12 can be equal to or less than the width of the first dielectric layer 11a; the second dielectric layer 11b needs to completely cover the waveguide device 12 for isolation, and the width of the second dielectric layer 11b can be equal to or less than the width of the first dielectric layer 11a; the same applies to other upper structures. In the example of the present application, please refer to Figure 2 , in the second direction F2, the dimensions of the third dielectric layer 11c, the second dielectric layer 11b, the first dielectric layer 11a, and the substrate 10 are equal.
[0037] In some embodiments, the silicon photonic passive device 10A includes at least two waveguide devices 12. The at least two waveguide devices 12 are located on the same layer in the stacking direction D. In the stacking direction D, the top surfaces of the at least two waveguide devices 12 are coplanar, and the bottom surfaces of the at least two waveguide devices 12 are coplanar. The at least two waveguide devices 12 are arranged side by side in the first direction F1.
[0038] Exemplarily, the present application is provided with at least two waveguide devices 12. In the stacking direction D, one of the waveguide devices 12 forms a strip waveguide and the other waveguide device 12 forms a ridge waveguide; along the stacking direction D, the thickness of the strip waveguide is equal to the thickness of the thickest part of the ridge waveguide, and the strip waveguide and the ridge waveguide are on the same layer, and their top and bottom surfaces are flush and coplanar. The setting of at least two waveguide devices 12 realizes an efficient, scalable and multifunctional optical path.
[0039] In some embodiments, taking Figure 1a as an example, the substrate 10 can be a silicon substrate, the first dielectric layer 11a, the second dielectric layer 11b and the third dielectric layer 11c can all be prepared from silicon dioxide (SiO2), the waveguide device 12 can be prepared from silicon (Si), and the end face coupler 13a can be prepared from silicon nitride (SiN).
[0040] In addition, the above-mentioned substrate 10, first dielectric layer 11a, second dielectric layer 11b, third dielectric layer 11c, end face coupler 13a, waveguide device 12 and laser can also be made of other materials or in other forms, which are specifically set according to actual needs.
[0041] Furthermore, the silicon optical passive device 10A further includes a trench 14. The trench 14 communicates with the notch of the coupling groove 13c and is located at the end of the silicon optical passive device 10A along the first direction F1 facing the light source 20, so that the light source body 22 of the light source 20 is arranged in the trench 14, and the light emitting part 21 is fitted into the coupling groove 13c through the notch, and the light source 20 and the end face coupler 13a form end face coupling (see Figure 6 and Figure 1a ). As mentioned above, in the first direction F1, the width of the substrate 10 is greater than the widths of the first dielectric layer 11a to the third dielectric layer 11c. Therefore, a part of the substrate 10 is exposed compared to the first dielectric layer 11a to the third dielectric layer 11c, the light source body 22 of the light source 20 is arranged on the exposed part of the substrate 10, and the light source body 22 is in direct contact with the side walls of the first dielectric layer 11a to the third dielectric layer 11c stacked in sequence. In some embodiments, as Figure 1a shown, in the stacking direction D, the side walls of the first dielectric layer 11a to the third dielectric layer 11c in contact with the light source body 22 are aligned with each other. In addition, the side walls of the first dielectric layer 11a to the third dielectric layer 11c away from the light source body 22 are aligned with each other and with the side wall of the substrate 10.
[0042] In the stacking direction D, the bottom of the light source body 22 is in contact with the substrate 10, and the substrate 10 provides support for the light source body 22; the side wall of the light source body 22 extends upward from the substrate 10 through the first dielectric layer 11a, the second dielectric layer 11b, and the third dielectric layer 11c in sequence, and the top surface of the light source body 22 (the dimension in the stacking direction D) is higher than the coupling groove 13c and lower than the top surface of the third dielectric layer 11c. The light emitting portion 21 is connected to one side of the light source body 22 facing the silicon optical passive device 10A and extends into the coupling groove 13c.
[0043] Still referring to Figure 6 , in the stacking direction D, the trench 14 extends from the top surface of the third dielectric layer 11c into the substrate 10, causing the substrate 10 to form a step. At this time, the top surface of the light source body 22 in the stacking direction D is lower than the top surface of the third dielectric layer 11c, obtaining Figure 1a the monolithic integrated silicon optical chip shown; since the light source 20 requires a certain thickness, by etching the trench 14 in the substrate 10 and then growing the light source 20, the height of the light source 20 in the overall structure of the monolithic integrated silicon optical chip can be reduced, thereby reducing the thickness of the monolithic integrated silicon optical chip as a whole in the stacking direction and reducing the risk of warping of the overall structure of the monolithic integrated silicon optical chip.
[0044] In the embodiment of the present application, since the light source 20 itself requires a certain thickness, by arranging the waveguide device 12 below the layer where the end face coupler 13a is located, the space utilization rate can be improved in this way, and the thickness of the monolithic integrated silicon optical chip as a whole in the stacking direction D can be reduced. However, the present application is not limited to this. In some other embodiments, the end face coupler 13a can be located below the waveguide device 12, and a corresponding dielectric layer is still provided between the two for isolation.
[0045] In addition, generally speaking, the height of the light source 20 (i.e., the dimension in the stacking direction D) is relatively high. The embodiment of the present application can adjust the thickness (the dimension in the stacking direction D) of the second dielectric layer 11b located between the waveguide device 12 and the end face coupler 13a to control the height of the light source 20, thereby further improving the coupling accuracy between the light source 20 and the end face coupler 13a.
[0046] In some other embodiments, the trench 14 extends from the top surface of the third dielectric layer 11c to the substrate 10 in the stacking direction D, and the bottom surface of the trench 14 coincides with the top surface of the substrate 10. At this time, the top surface of the light source body 22 in the stacking direction D is still lower than the top surface of the third dielectric layer 11c and higher than the coupling groove 13c, but the thickness of the second dielectric layer 11b in the stacking direction D increases, and the Figure 1b monolithic integrated silicon optical chip shown can be obtained. Since the light source 20 itself requires a certain thickness, therefore Figure 1b the thickness of the second dielectric layer 11b in the stacking direction D in Figure 1aThe thickness of the second dielectric layer 11b in the stacking direction D can thus maintain the height of the light source 20.
[0047] Based on this, an embodiment of the present application further provides a method for manufacturing a monolithic integrated silicon photonic chip, which will be introduced below by taking the SOI substrate platform as an example. However, the silicon photonic chip provided by the present application can also be applied to other different substrate platforms.
[0048] The manufacturing method includes:
[0049] As Figure 3 shown, S200: Form an Si waveguide device 12 on an SOI (silicon-on-insulator) substrate, then deposit an SiO2 layer as the second dielectric layer 11b, and then deposit an SiN layer 13 on the SiO2 second dielectric layer 11b;
[0050] Generally, the SOI substrate includes a substrate 10, a first dielectric layer 11a, and a single-crystalline silicon layer (not shown in the figure) stacked in sequence. The single-crystalline silicon layer is etched to form a waveguide device 12. Then, a second dielectric layer 11b is deposited on the formed waveguide device 12, and the second dielectric layer 11b is planarized (such as chemical mechanical polishing) so that the top surface of the second dielectric layer 11b is flat. After the planarization process, the top surface of the second dielectric layer 11b is higher than the top surface of the waveguide device 12, that is, the second dielectric layer 11b still covers the waveguide device 12. Then, an SiN layer 13 is deposited on the second dielectric layer 11b. Since the top surface of the second dielectric layer 11b is flat, the SiN layer 13 has a uniform thickness and a flat top surface.
[0051] As Figure 4 shown, S201: Perform a first photolithography on the SiN layer 13 to form an SiN end face coupler 13a and a dummy structure 13b.
[0052] Among them, since both the SiN end face coupler 13a and the dummy structure 13b are formed by performing a single photolithography on the SiN layer 13, they have the same characteristics in this step, such as the same material, thickness, etc. They are located on the same layer in the stacking direction D, and the end face coupler 13a and the dummy structure 13b share the same top surface, the same bottom surface, and have the same thickness d in the stacking direction D; they are also arranged side by side in the first direction F1 and share the same axis S (see Figure 2 ). The dummy structure 13b is used to form a coupling groove 13c in a subsequent step to fit the light-emitting part 21 of the light source 20.
[0053] After the end face coupler 13a and the dummy structure 13b are formed, the second dielectric layer 11b also separates the waveguide device 12 from the end face coupler 13a and the dummy structure 13b.
[0054] As Figure 5 shown, S202: Deposit an SiO2 layer as the third dielectric layer 11c. The third dielectric layer 11c covers the end face coupler 13a and the dummy structure 13b, and laterally spaces apart the end face coupler 13a and the dummy structure 13b. After that, the third dielectric layer 11c can also be planarized (e.g., chemical mechanical polishing) so that the top surface of the third dielectric layer 11c is flat;
[0055] As Figure 6 , Figure 7 shown, S203: Perform a second photolithography on the third dielectric layer 11c. After that, etch the third dielectric layer 11c, the second dielectric layer 11b, the first dielectric layer 11a, and etch the Si substrate 10. After two etches, a trench 14 is formed; The trench 14 is located at the end of the silicon optical passive device 10A along the first direction F1 facing the light source 20, so that in the first direction F1, the end of the dummy structure 13b is exposed from the silicon optical passive device 10A to facilitate subsequent removal of the dummy structure 13b to form a coupling groove 13c.
[0056] As Figure 8 , Figure 9 shown, S204: Remove the dummy structure 13b;
[0057] Exemplarily, the dummy structure 13b can be removed by wet etching with a hot phosphoric acid solution to form a coupling groove 13c reserved for the light emitting part 21 of the light source 20 in the layer where the end face coupler 13a is located.
[0058] S205: Form the light emitting part 21 of the light source 20 in the coupling groove 13c, thereby forming Figure 1a , Figure 2 the monolithic integrated silicon optical chip shown.
[0059] Figure 1b For the monolithic integrated silicon optical chip shown, its manufacturing method can be referred to the above implementation. The difference is that when forming the trench 14, only the third dielectric layer 11c, the second dielectric layer 11b, and the first dielectric layer 11a need to be etched.
[0060] In summary, the light emitting part 21 of the light source 20 is fitted in the coupling groove 13c of the silicon optical passive device 10A, so that the light emitting part 21 and the end face coupler 13a are in the same layer in the stacking direction D and have the same thickness, and their top surfaces and bottom surfaces are coplanar. Thus, the light emitting part 21 of the light source 20 and the SiN end face coupler 13a are precisely aligned in the coupling groove 13c, so that the coupling accuracy can be controlled at the nanometer level, effectively improving the end face coupling efficiency. And, compared with the external light source in the prior art, the present application utilizes the advantages of a monolithic integrated laser and has an ultra-high alignment accuracy at the in-plane photolithography level, and can provide a high-density integrated light source 20 for the silicon optical passive device 10A.
[0061] On the other hand, an embodiment of the present application also discloses an optoelectronic integrated system, including the monolithic integrated silicon photonic chip of any one of the above.
[0062] This optoelectronic integrated system has the same structure and beneficial effects as the monolithic integrated silicon photonic chip in the foregoing embodiment. The structure and beneficial effects of the monolithic integrated silicon photonic chip have been described in detail in the foregoing embodiment and will not be elaborated herein.
[0063] The above are only the embodiments of the present application and are not intended to limit the protection scope of the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A monolithically integrated silicon photonic chip, characterized in that: include: A silicon photonic passive device (10A) and a light source (20), wherein the light source (20) is located on one side of the silicon photonic passive device (10A) along a first direction (F1); an end face coupler (13a) and a coupling groove (13c) are arranged in the silicon photonic passive device (10A); the coupling groove (13c) and the end face coupler (13a) are arranged side by side along the first direction (F1); along a stacking direction (D), the top surface of the coupling groove (13c) is coplanar with the top surface of the end face coupler (13a), and the bottom surface of the coupling groove (13c) is coplanar with the bottom surface of the end face coupler (13a); a light emitting portion (21) of the light source (20) is embedded in the coupling groove (13c) so that the light emitting portion (21) and the end face coupler (13a) are coupled; the first direction (F1) and the stacking direction (D) are perpendicular.
2. The monolithically integrated silicon photonic chip according to claim 1, characterized in that: The size of the light source (20) along the second direction (F2) gradually increases from an end close to the end face coupler (13a) to an end away from the end face coupler (13a), so that the light source (20) forms a cone on the top-view plane formed by the first direction (F1) and the second direction (F2), and the second direction (F2) is perpendicular to the first direction (F1) and the stacking direction (D).
3. The monolithically integrated silicon photonic chip according to claim 1, characterized in that: The silicon photonic passive device (10A) comprises a substrate (10), a first dielectric layer (11a), a waveguide device (12), a second dielectric layer (11b), the end face coupler (13a) and a third dielectric layer (11c) which are sequentially arranged along the stacking direction (D); the second dielectric layer (11b) covers the waveguide device (12) and separates the waveguide device (12) from the end face coupler (13a); the third dielectric layer (11c) covers the end face coupler (13a) and the coupling groove (13c), and laterally separates the end face coupler (13a) from the coupling groove (13c).
4. The monolithically integrated silicon photonic chip according to claim 3, characterized in that: The silicon photonic passive device (10A) further comprises a groove (14), wherein the groove (14) and the notch of the coupling groove (13c) are connected and are both located at the end of the silicon photonic passive device (10A) along the first direction (F1) toward the light source (20), and the light source (20) further comprises a light source body, which is arranged in the groove (14).
5. The monolithically integrated silicon photonic chip according to claim 4, characterized in that: The groove (14) extends from the top surface of the third dielectric layer (11c) to the substrate (10) or on the substrate (10) in the stacking direction (D), and the top surface of the light source body in the stacking direction (D) is lower than the top surface of the third dielectric layer (11c).
6. The monolithically integrated silicon photonic chip according to claim 4, characterized in that: In the first direction (F1), the width of the substrate (10) is greater than the widths of the first dielectric layer (11a), the second dielectric layer (11b) and the third dielectric layer (11c), and the light source body (22) of the light source (20) is in contact with the side walls of the first dielectric layer (11a), the second dielectric layer (11b) and the third dielectric layer (11c) stacked in sequence.
7. The monolithically integrated silicon photonic chip according to claim 3, characterized in that: The silicon photonic passive device (10A) comprises at least two waveguide devices (12), wherein the at least two waveguide devices (12) are arranged side by side in the first direction (F1), and in the stacking direction (D), the top surfaces of the at least two waveguide devices (12) are coplanar, and the bottom surfaces of the at least two waveguide devices (12) are coplanar.
8. The monolithically integrated silicon photonic chip according to any one of claims 3 to 7, characterized in that: The substrate (10) comprises at least a silicon substrate, the first dielectric layer (11a), the second dielectric layer (11b) and the third dielectric layer (11c) all comprise at least a silicon dioxide dielectric layer, the waveguide device (12) comprises at least a silicon waveguide device, and the end face coupler (13a) comprises at least a silicon nitride end face coupler.
9. The monolithically integrated silicon photonic chip according to any one of claims 1 to 7, characterized in that: The light source (20) comprises at least a laser.
10. An optoelectronic integrated system, characterized in that: A monolithically integrated silicon photonic chip comprising any one of claims 1 to 9.