Full adder circuit
By designing a full adder circuit, using an inverter and a small number of MOS tubes, the full drive function is achieved, which solves the problem of large number of transistors and non-full swing in the existing full adder circuit, saving chip area and improving connection flexibility.
Patent Information
- Application Number
- CN202422162876.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-04
- Publication Date
- 2025-07-04
- Estimated Expiration
- 2034-09-04
Smart Images
Figure CN223065729U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to circuit technology, and particularly relates to a full adder circuit. Background Art
[0002] With the rapid development of integrated circuit technology, the physical size reduction of semiconductor devices in the post-Moore era has reached its limit, which has greatly restricted the development of digital integrated circuits. Therefore, how to optimize the circuit structure and improve the integration of digital integrated circuits has become particularly important.
[0003] The full adder is one of the basic units of digital logic operations and has a wide range of applications in fields such as logic control and numerical operations. Currently, the number of transistors used in the transistor circuit design inside the full adder is usually large. For example, the 28-transistor complementary static full adder and the 22-transistor full-swing with drive full adder (see Paper: Zhuang, N., Wu, H.M., 1992. A new design of the CMOS full adder. IEEE J. Sol.-State Circ., 27(5): 840-844. [doi:10.1109 / 4.133177]). In addition, there are also some full adders with fewer MOS transistors, but they are all non-full-swing and non-driven full adders.
[0004] There is a conventional 22-transistor full-swing, with drive full adder as Figure 1 shown. According to the Karnaugh map:
[0005]
[0006] After taking the inverse of SUMb, we get:
[0007] COUTb = Ab·Bb + CINb·(A⊙B);
[0008] After transformation:
[0009] Then take the inverse of COUTb to get COUT.
[0010] Where: A is the input of the full adder; Ab is the inverse of A; B is the other input of the full adder; Bb is the inverse of B; CIN is the carry signal of the full adder, CINb is the inverse of CIN; SUM is the sum output of the full adder, SUMb is the inverse of SUM, COUT is the sum carry output of the full adder, and COUTb is the inverse of COUT.
[0011] Symbols: represents exclusive OR, and ⊙ represents equivalence. Summary of the Utility Model
[0012] The technical problem to be solved by the present utility model is to provide a full adder circuit, which is a full adder with full drive and all positive input and output, and can reduce MOS transistors and save chip area.
[0013] To solve the above technical problem, the full adder circuit provided by the present invention includes a first inverter, a second inverter, 8 PMOS transistors and 8 NMOS transistors;
[0014] The gates of the first PMOS transistor MP1, the first NMOS transistor MN1, the second PMOS transistor MP2 and the source of the third PMOS transistor MP3 are short-circuited to the first pin Pin1 of the full adder;
[0015] The gate of the third NMOS transistor MN3, the gate of the third PMOS transistor MP3, the source of the second PMOS transistor MP2 and the source of the second NMOS transistor MN2 are short-circuited to the second pin Pin2 of the full adder;
[0016] The drains of the first PMOS transistor MP1, the first NMOS transistor MN1, the source of the third NMOS transistor MN3, the gate of the second NMOS transistor MN2, the source of the ninth NMOS transistor MN9 and the source of the ninth PMOS transistor MP9 are short-circuited;
[0017] The drains of the third NMOS transistor MN3, the third PMOS transistor MP3, the second PMOS transistor MP2 and the second NMOS transistor MN2, the gate of the fourth NMOS transistor MN4, the gate of the fourth PMOS transistor MP4, the gate of the fifth NMOS transistor MN5, the source of the sixth NMOS transistor MN6, the gate of the eighth NMOS transistor MN8 and the gate of the ninth PMOS transistor MP9 are short-circuited;
[0018] The drains of the fourth NMOS transistor MN4, the fourth PMOS transistor MP4, the gate of the fifth PMOS transistor MP5, the source of the sixth PMOS transistor MP6, the gate of the eighth PMOS transistor MP8 and the gate of the ninth NMOS transistor MN9 are short-circuited;
[0019] The source of the fifth PMOS transistor MP5, the gate of the sixth PMOS transistor MP6, the source of the fifth NMOS transistor MN5 and the gate of the sixth NMOS transistor MN6 are short-circuited to the third pin Pin3;
[0020] The drains of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are short-circuited to the input end of the first inverter;
[0021] The drains of the eighth NMOS transistor MN8, the eighth PMOS transistor MP8, the ninth NMOS transistor MN9 and the ninth PMOS transistor MP9 are short-circuited to the input end of the second inverter;
[0022] The source electrodes of the eighth NMOS transistor MN8 and the eighth PMOS transistor MP8 are short - connected to the output terminal of the first inverter;
[0023] The output terminal of the first inverter is short - connected to the fourth pin Pin4, serving as the sum output SUM of the full - adder;
[0024] The output terminal of the second inverter is short - connected to the fifth pin Pin5, serving as the carry - out output COUT of the full - adder;
[0025] The source electrodes of the first PMOS transistor MP1 and the fourth PMOS transistor MP4 are connected to the working voltage source;
[0026] The source electrodes of the first NMOS transistor MN1 and the fourth NMOS transistor MN4 are grounded.
[0027] Preferably, the first inverter includes a seventh NMOS transistor MN7 and a seventh PMOS transistor MP7;
[0028] The gate electrodes of the seventh NMOS transistor MN7 and the seventh PMOS transistor MP7 are short - connected as the input terminal of the first inverter;
[0029] The drain electrodes of the seventh NMOS transistor MN7 and the seventh PMOS transistor MP7 are short - connected as the output terminal of the first inverter;
[0030] The source electrode of the seventh PMOS transistor MP7 is connected to the working voltage source;
[0031] The source electrode of the seventh NMOS transistor MN7 is grounded.
[0032] Preferably, the second inverter includes a tenth NMOS transistor MN10 and a tenth PMOS transistor MP10;
[0033] The gate electrodes of the tenth NMOS transistor MN10 and the tenth PMOS transistor MP10 are short - connected as the input terminal of the second inverter;
[0034] The drain electrodes of the tenth NMOS transistor MN10 and the tenth PMOS transistor MP10 are short - connected as the output terminal of the second inverter;
[0035] The source electrode of the tenth PMOS transistor MP10 is connected to the working voltage source;
[0036] The source electrode of the tenth NMOS transistor MN10 is grounded.
[0037] Preferably, the first pin Pin1 is used to connect the input A, the second pin Pin2 is used to connect the input B, and the third pin Pin3 is used to connect the carry - in signal CIN.
[0038] Preferably, the first pin Pin1 is used to connect to input A, the second pin Pin2 is used to connect to the carry signal CIN, and the third pin Pin3 is used to connect to input B.
[0039] Preferably, the first pin Pin1 is used to connect to input B, the second pin Pin2 is used to connect to input A, and the third pin Pin3 is used to connect to the carry signal CIN.
[0040] Preferably, the first pin Pin1 is used to connect to input B, the second pin Pin2 is used to connect to the carry signal CIN, and the third pin Pin3 is used to connect to input A.
[0041] Preferably, the first pin Pin1 is used to connect to the carry signal CIN, the second pin Pin2 is used to connect to input A, and the third pin Pin3 is used to connect to input B.
[0042] Preferably, the first pin Pin1 is used to connect to the carry signal CIN, the second pin Pin2 is used to connect to input B, and the third pin Pin3 is used to connect to input A.
[0043] The full adder circuit of the present invention uses the sum output SUM of the full adder as an input signal for one path of the sum carry output COUT of the full adder. It is a full adder with full drive and all positive input and output, and does not require an inverter for the carry signal CIN of the full adder. It can not only avoid the disadvantages of non-full swing and non-full drive full adders, but also save the MOS transistors that make up the inverter, saving chip area. Moreover, the connection of the three pins Pin1 / Pin2 / Pin3 of the full adder circuit to the two inputs and the carry signal of the full adder can be interchanged. Description of the Drawings
[0044] In order to more clearly illustrate the technical solutions of the present invention, the following briefly introduces the drawings required for the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0045] Figure 1 It is a circuit diagram of an existing 22-transistor full swing and drive full adder;
[0046] Figure 2 It is a circuit diagram of an embodiment of the full adder circuit of the present invention;
[0047] Figure 3 It is an external signal diagram of an embodiment of the full adder circuit of the present invention. Detailed Embodiments
[0048] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0049] The "first", "second" and similar terms used in this application do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", "right", "front", "rear", etc. are only used to represent relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.
[0050] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other.
[0051] Embodiment 1
[0052] As Figure 2 shown, it includes a first inverter, a second inverter, 8 PMOS transistors and 8 NMOS transistors;
[0053] The gates of the first PMOS transistor MP1, the first NMOS transistor MN1, the gate of the second PMOS transistor MP2, and the source of the third PMOS transistor MP3 are shorted to the first pin Pin1 of the full adder;
[0054] The gate of the third NMOS transistor MN3, the gate of the third PMOS transistor MP3, the source of the second PMOS transistor MP2, and the source of the second NMOS transistor MN2 are shorted to the second pin Pin2 of the full adder;
[0055] The drains of the first PMOS transistor MP1, the first NMOS transistor MN1, the source of the third NMOS transistor MN3, the gate of the second NMOS transistor MN2, the source of the ninth NMOS transistor MN9, and the source of the ninth PMOS transistor MP9 are shorted;
[0056] The drains of the third NMOS transistor MN3, the third PMOS transistor MP3, the second PMOS transistor MP2, and the second NMOS transistor MN2, the gates of the fourth NMOS transistor MN4, the fourth PMOS transistor MP4, the fifth NMOS transistor MN5, the source of the sixth NMOS transistor MN6, the gate of the eighth NMOS transistor MN8, and the gate of the ninth PMOS transistor MP9 are shorted together;
[0057] The drains of the fourth NMOS transistor MN4, the fourth PMOS transistor MP4, the gate of the fifth PMOS transistor MP5, the source of the sixth PMOS transistor MP6, the gate of the eighth PMOS transistor MP8, and the gate of the ninth NMOS transistor MN9 are shorted together;
[0058] The sources of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the source of the fifth NMOS transistor MN5, and the gate of the sixth NMOS transistor MN6 are shorted to the third pin Pin3;
[0059] The drains of the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the drain of the fifth NMOS transistor MN5, and the drain of the sixth NMOS transistor MN6 are shorted to the input terminal of the first inverter;
[0060] The drains of the eighth NMOS transistor MN8, the eighth PMOS transistor MP8, the drain of the ninth NMOS transistor MN9, and the drain of the ninth PMOS transistor MP9 are shorted to the input terminal of the second inverter;
[0061] The sources of the eighth NMOS transistor MN8 and the eighth PMOS transistor MP8 are shorted to the output terminal of the first inverter;
[0062] The output terminal of the first inverter is shorted to the fourth pin Pin4 to serve as the sum output SUM of the full adder;
[0063] The output terminal of the second inverter is shorted to the fifth pin Pin5 to serve as the carry output COUT of the sum of the full adder;
[0064] The sources of the first PMOS transistor MP1 and the fourth PMOS transistor MP4 are connected to the working voltage source;
[0065] The sources of the first NMOS transistor MN1 and the fourth NMOS transistor MN4 are grounded.
[0066] The full adder circuit of the first embodiment is based on the existing Figure 1 As shown in the 22-transistor full adder, continue to transform COUTb, such as COUTb = Ab·Bb + CINb·(A⊙B). After the transformation Then, take the inverse of COUTb to obtain the sum carry output COUT of the full adder. Here, A is the input of the full adder; Ab is the inverse of A; B is the other input of the full adder; Bb is the inverse of B; CIN is the carry signal of the full adder, and CINb is the inverse of CIN; SUM is the sum output of the full adder, SUMb is the inverse of SUM, COUT is the sum carry output of the full adder, and COUTb is the inverse of COUT. ⊕ represents exclusive OR, and ⊙ represents equivalence.
[0067] For the full adder circuit of Embodiment 1, using the sum output SUM of the full adder as one input signal of the sum carry output COUT of the full adder, it is a full adder with full drive and all positive input and output, and does not require an inverter for the carry signal CIN of the full adder. It can not only avoid the disadvantages of non-full swing and non-full drive full adders, but also save the MOS transistors that make up the inverter, saving chip area. Moreover, the connection of the three pins Pin1 / Pin2 / Pin3 of this full adder circuit to the two inputs and the carry signal of the full adder can be interchanged.
[0068] Embodiment 2
[0069] Based on the full adder circuit of Embodiment 1, the first inverter includes a seventh NMOS transistor MN7 and a seventh PMOS transistor MP7;
[0070] The gates of the seventh NMOS transistor MN7 and the seventh PMOS transistor MP7 are short-circuited as the input end of the first inverter;
[0071] The drains of the seventh NMOS transistor MN7 and the seventh PMOS transistor MP7 are short-circuited as the output end of the first inverter;
[0072] The source of the seventh PMOS transistor MP7 is connected to the working voltage source;
[0073] The source of the seventh NMOS transistor MN7 is grounded.
[0074] Embodiment 3
[0075] Based on the full adder circuit of Embodiment 1, the second inverter includes a tenth NMOS transistor MN10 and a tenth PMOS transistor MP10;
[0076] The gates of the tenth NMOS transistor MN10 and the tenth PMOS transistor MP10 are short-circuited as the input end of the second inverter;
[0077] The drains of the tenth NMOS transistor MN10 and the tenth PMOS transistor MP10 are short-circuited as the output end of the second inverter;
[0078] The source of the tenth PMOS transistor MP10 is connected to the working voltage source;
[0079] The source electrode of the tenth NMOS transistor MN10 is grounded.
[0080] Embodiment 4
[0081] Based on the full adder circuit of Embodiment 1, the first pin Pin1 is used to connect to input A, the second pin Pin2 is used to connect to input B, and the third pin Pin3 is used to connect to the carry signal CIN.
[0082] Or it can be:
[0083] The first pin Pin1 is used to connect to input A, the second pin Pin2 is used to connect to the carry signal CIN, and the third pin Pin3 is used to connect to input B. Or
[0084] The first pin Pin1 is used to connect to input B, the second pin Pin2 is used to connect to input A, and the third pin Pin3 is used to connect to the carry signal CIN. Or
[0085] The first pin Pin1 is used to connect to input B, the second pin Pin2 is used to connect to the carry signal CIN, and the third pin Pin3 is used to connect to input A. Or
[0086] The first pin Pin1 is used to connect to the carry signal CIN, the second pin Pin2 is used to connect to input A, and the third pin Pin3 is used to connect to input B. Or
[0087] The first pin Pin1 is used to connect to the carry signal CIN, the second pin Pin2 is used to connect to input B, and the third pin Pin3 is used to connect to input A.
[0088] For the full adder circuit of Embodiment 4, the connection between the full adder input signals A / B / CIN and the three pins Pin1 / Pin2 / Pin3 can be interchanged, and there are a total of six interchangeable connection methods, as shown in the following table.
[0089] case Pin1 Pin2 Pin3 Pin4 Pin5 1 A B CIN SUM COUT 2 A CIN B SUM COUT 3 B A CIN SUM COUT 4 B CIN A SUM COUT 5 CIN A B SUM COUT 6 CIN B A SUM COUT
[0090] The general writing methods of SUMb and COUTb are as follows:
[0091] SUMb is inverted:
[0092] Then reverse COUTb to obtain COUT.
[0093] Among them, Pin1b is the inversion of Pin1; Pin2b is the inversion of Pin2; Pin3b is the inversion of Pin3.
[0094] The above are only the preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present utility model shall be included within the scope of protection of the present utility model.
Claims
1. A full adder circuit, characterized in that, It includes a first inverter, a second inverter, eight PMOS transistors and eight NMOS transistors; The gates of the first PMOS transistor (MP1), the first NMOS transistor (MN1), the second PMOS transistor (MP2) and the source of the third PMOS transistor (MP3) are shorted to the first pin (Pin1) of the full adder; The gate of the third NMOS transistor (MN3), the gate of the third PMOS transistor (MP3), the source of the second PMOS transistor (MP2) and the source of the second NMOS transistor (MN2) are shorted to the second pin (Pin2) of the full adder; The drains of the first PMOS transistor (MP1), the first NMOS transistor (MN1), the source of the third NMOS transistor (MN3), the gate of the second NMOS transistor (MN2), the source of the ninth NMOS transistor (MN9) and the source of the ninth PMOS transistor (MP9) are shorted; The drains of the third NMOS transistor (MN3), the third PMOS transistor (MP3), the second PMOS transistor (MP2) and the second NMOS transistor (MN2), the gate of the fourth NMOS transistor (MN4), the gate of the fourth PMOS transistor (MP4), the gate of the fifth NMOS transistor (MN5), the source of the sixth NMOS transistor (MN6), the gate of the eighth NMOS transistor (MN8) and the gate of the ninth PMOS transistor (MP9) are shorted; The drains of the fourth NMOS transistor (MN4), the fourth PMOS transistor (MP4), the gate of the fifth PMOS transistor (MP5), the source of the sixth PMOS transistor (MP6), the gate of the eighth PMOS transistor (MP8) and the gate of the ninth NMOS transistor (MN9) are shorted; The source of the fifth PMOS transistor (MP5), the gate of the sixth PMOS transistor (MP6), the source of the fifth NMOS transistor (MN5) and the gate of the sixth NMOS transistor (MN6) are shorted to the third pin (Pin3); The drains of the fifth PMOS transistor (MP5), the sixth PMOS transistor (MP6), the fifth NMOS transistor (MN5) and the sixth NMOS transistor (MN6) are shorted to the input terminal of the first inverter; The drains of the eighth NMOS transistor (MN8), the eighth PMOS transistor (MP8), the ninth NMOS transistor (MN9) and the ninth PMOS transistor (MP9) are shorted to the input terminal of the second inverter; The source of the eighth NMOS transistor (MN8) and the source of the eighth PMOS transistor (MP8) are shorted to the output terminal of the first inverter; The output terminal of the first inverter is shorted to the fourth pin (Pin4) as the sum output SUM of the full adder; The output terminal of the second inverter is shorted to the fifth pin (Pin5) as the sum carry output COUT of the full adder; The sources of the first PMOS transistor (MP1) and the fourth PMOS transistor (MP4) are connected to the working voltage source; The sources of the first NMOS transistor (MN1) and the fourth NMOS transistor (MN4) are grounded.
2. The full adder circuit according to claim 1, wherein The first inverter includes a seventh NMOS transistor (MN7) and a seventh PMOS transistor (MP7); The gates of the seventh NMOS transistor (MN7) and the seventh PMOS transistor (MP7) are shorted and used as the input terminal of the first inverter; The drains of the seventh NMOS transistor (MN7) and the seventh PMOS transistor (MP7) are shorted and used as the output terminal of the first inverter; The source of the seventh PMOS transistor (MP7) is connected to the working voltage source; The source of the seventh NMOS transistor (MN7) is grounded.
3. The full adder circuit according to claim 1, wherein The second inverter includes a tenth NMOS transistor (MN10) and a tenth PMOS transistor (MP10); The gates of the tenth NMOS transistor (MN10) and the tenth PMOS transistor (MP10) are shorted and used as the input terminal of the second inverter; The drains of the tenth NMOS transistor (MN10) and the tenth PMOS transistor (MP10) are shorted and used as the output terminal of the second inverter; The source of the tenth PMOS transistor (MP10) is connected to the working voltage source; The source of the tenth NMOS transistor (MN10) is grounded.
4. The full adder circuit according to claim 1, wherein The first pin (Pin1) is used to connect to input A, the second pin (Pin2) is used to connect to input B, and the third pin (Pin3) is used to connect to the carry signal CIN.
5. The full adder circuit according to claim 1, wherein The first pin (Pin1) is used to connect to input A, the second pin (Pin2) is used to connect to the carry signal CIN, and the third pin (Pin3) is used to connect to input B.
6. The full adder circuit according to claim 1, wherein The first pin (Pin1) is used to connect to input B, the second pin (Pin2) is used to connect to input A, and the third pin (Pin3) is used to connect to the carry signal CIN.
7. The full adder circuit according to claim 1, wherein The first pin (Pin1) is used to connect to input B, the second pin (Pin2) is used to connect to the carry signal CIN, and the third pin (Pin3) is used to connect to input A.
8. The full adder circuit according to claim 1, wherein The first pin (Pin1) is used to connect to the carry signal CIN, the second pin (Pin2) is used to connect to input A, and the third pin (Pin3) is used to connect to input B.
9. The full adder circuit according to claim 1, wherein The first pin (Pin1) is used to connect to the carry signal CIN, the second pin (Pin2) is used to connect to input B, and the third pin (Pin3) is used to connect to input A.