VDMOS transistor

Abstract

The utility model relates to the technical field of MOS semiconductors, and discloses a VDMOS transistor, which comprises a VDMOS structure formed by a plurality of VDMOS cells arranged in parallel, and each VDMOS cell comprises a drain electrode, a source electrode, a grid electrode and a semiconductor epitaxial layer. The semiconductor epitaxial layer comprises a sinking layer, a diffusion layer, a P well layer and an N well layer; wherein an intermediate layer is formed between a diffusion layer and a substrate layer in a single VDMOS cell through ion implantation; a drift layer is formed in the diffusion layer of the single VDMOS cell close to the gate region through ion implantation, and the drift layer is divided into a lightly doped drift layer and a heavily doped drift layer; and the P well layer comprises a heavily doped P well layer II, a heavily doped P well layer I, a low heavily doped P well layer I and a low doped P well layer II. The intermediate layer is formed between the substrate layer and the diffusion layer through ion implantation, and the doping concentration of the intermediate layer is lower than that of the diffusion layer, so that the pulse voltage tolerance of the semiconductor can be improved, and the avalanche tolerance of the VDMOS device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS semiconductors, and more specifically to a VDMOS transistor. Background Art

[0002] A VDMOS (Vertical Double-diffused MOS) device is a vertical double-diffused MOS (Metal Oxide Semiconductor) device, usually referring to a VDMOSFET (Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect Transistor). This device is known for its structural characteristics and is mainly used in power electronics applications. VDMOS devices have advantages such as low on-resistance, high breakdown voltage, and high-speed switching, and are suitable for applications that require high-performance power switches, such as power management, electric vehicle control, frequency converters, etc.

[0003] A prior patent discloses a super-high-voltage VDMOS transistor (publication number CN207009440U), which includes a substrate wafer of a first conductivity type, a doped layer of the first conductivity type located on the back surface of the substrate wafer, a first metal electrode located below the doped layer, a gate structure located on the front surface of the substrate wafer, and a second metal electrode located on the gate structure. The first metal electrode serves as the drain of the VDMOS transistor, and the second metal electrode serves as the source of the VDMOS transistor; the gate structure includes a well region of a second conductivity type, a contact region of the second conductivity type located in the well region, and source regions of the first conductivity type located on both sides of the contact region. In the technology disclosed in this patent, when a voltage is applied to the gate instantaneously and a pulsed voltage or a peak voltage is generated, since the semiconductor epitaxial layer lacks the ability to reduce the attraction of the strong electric field generated by the peak voltage and pulsed voltage to charges, the charges at the drain are extremely likely to directly break through the gate oxide layer and flow into the gate. Summary of the Invention

[0004] The main technical problem to be solved by the utility model is to provide a VDMOS transistor, which solves the problems in the above background art.

[0005] To solve the above technical problem, according to one aspect of the utility model, more specifically, a VDMOS transistor includes a VDMOS structure formed by a plurality of VDMOS cells arranged side by side. Each VDMOS cell includes a drain, a source, a gate, and a semiconductor epitaxial layer;

[0006] The semiconductor epitaxial layer includes a sinker layer, a diffusion layer, a P-well layer, and an N-well layer;

[0007] Among them, an intermediate layer is formed between the diffusion layer and the substrate layer in a single VDMOS cell by ion implantation;

[0008] A drift layer is formed by ion implantation inside the diffusion layer of a single VDMOS cell near the gate region, and the drift layer is divided into a lightly doped drift layer and a heavily doped drift layer;

[0009] The P-well layer includes a heavily doped P-well layer two, a heavily doped P-well layer one, a low-heavily doped P-well layer one, and a lightly doped P-well layer two;

[0010] The N-well layer includes a lightly doped N-well layer one, a heavily doped N-well layer one, and a lightly doped N-well layer two;

[0011] Among them, when the gate is connected to the gate voltage, a charge channel is formed inside the low-heavily doped P-well layer one near the gate position.

[0012] Furthermore, an oxide layer is deposited between the surface of the gate and the source and the semiconductor epitaxial layer.

[0013] Furthermore, the heavily doped P-well layer twos between adjacent VDMOS cells are integrated into one body.

[0014] Furthermore, the cross-sectional profile thicknesses of the heavily doped P-well layer one, the low-heavily doped P-well layer one, and the lightly doped P-well layer two are the same.

[0015] Furthermore, the low-heavily doped P-well layer one is in ohmic contact with the heavily doped drift layer, and the lightly doped P-well layer two is in ohmic contact with the lightly doped drift layer.

[0016] Furthermore, the heavily doped N-well layer one is located between the lightly doped N-well layer one and the lightly doped N-well layer two.

[0017] Furthermore, the lightly doped N-well layer one, the heavily doped N-well layer one, and the lightly doped N-well layer two are all in ohmic contact with the source.

[0018] Furthermore, the heavily doped N-well layer one is in ohmic contact with the low-heavily doped P-well layer one, and the lightly doped N-well layer two is in ohmic contact with both the heavily doped P-well layer one and the lightly doped P-well layer two.

[0019] Furthermore, the substrate layer, the intermediate layer, the lightly doped drift layer, and the diffusion layer are doped with low-concentration phosphorus ions;

[0020] Among them, the heavily doped N-well layer one and the heavily doped drift layer are doped with high-concentration phosphorus ions;

[0021] The lightly doped N-well layer one and the lightly doped N-well layer two are doped with low-concentration phosphorus ions.

[0022] Further, the second heavily doped P-well layer and the first heavily doped P-well layer are doped with high-concentration boron ions; the first low-heavily doped P-well layer and the second lightly doped P-well layer are doped with low-concentration boron ions.

[0023] The beneficial effects of a VDMOS transistor of the present utility model are as follows:

[0024] 1. In the present utility model, an intermediate layer is formed by ion implantation between the substrate layer and the diffusion layer. Since the doping concentration of the intermediate layer is lower than that of the diffusion layer, the pulse voltage tolerance of the semiconductor can be improved, and the avalanche tolerance of the VDMOS device can be enhanced.

[0025] 2. In the present utility model, a drift layer is formed by ion implantation in the area near the P-well layer. Due to the double-layer design of the drift layer, the influence of the peak voltage can be effectively reduced. Moreover, the doping concentration of the heavily doped drift layer is the same as that of the first heavily doped N-well layer, so that the on-resistance between the drain and the source can be reduced after the charge channel is formed.

[0026] 3. In the present utility model, the N-well layer is divided into three levels, and the first heavily doped N-well layer with a high doping concentration and good conductivity is located in the intermediate layer and is in ohmic contact with the first low-heavily doped P-well layer. This not only ensures the conductivity of the N-well layer but also reduces the lateral interference of the gate electric field on the internal charges of the N-well layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The following further describes the present utility model in detail with reference to the drawings and specific implementation methods.

[0028] Figure 1 It is a schematic diagram of a silicon carbide VDMOS device;

[0029] Figure 2 is Figure 1 a partial enlarged detail schematic diagram;

[0030] Figure 3 It is a schematic diagram of the dual-cell juxtaposed structure of the present utility model.

[0031] In the figure: 1. Drain; 2. Source; 3. Gate; 4. Oxide layer; 5. First lightly doped N-well layer; 6. First heavily doped N-well layer; 7. Second lightly doped N-well layer; 8. First heavily doped P-well layer; 9. Second heavily doped P-well layer; 10. Diffusion layer; 11. Intermediate layer; 12. Substrate layer; 13. Lightly doped drift layer; 14. Heavily doped drift layer; 15. First low-heavily doped P-well layer; 16. Second lightly doped P-well layer; 17. Charge channel. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] The present utility model will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0033] As Figures 1-3 shown, according to one aspect of the present utility model, a VDMOS transistor is provided, which includes a VDMOS structure formed by arranging a plurality of VDMOS cells in parallel. Each VDMOS cell includes a drain 1, a source 2, a gate 3, and a semiconductor epitaxial layer. The semiconductor epitaxial layer includes a sinker layer 12, a diffusion layer 10, a P-well layer, and an N-well layer (as Figure 2 shown). The N-well layer is isolated from the diffusion layer 10 by the P-well layer. After the gate 3 is connected to a gate voltage, a charge channel 17 will be formed inside the P-well layer, and this charge channel connects the N-well layer and the diffusion layer 10, thereby realizing the conduction between the drain 1 and the source 2. Among them, by controlling the magnitude of the gate voltage, the magnitude of the conduction current between the drain 1 and the source 2 can be controlled.

[0034] Among them, in a single VDMOS cell, an intermediate layer 11 is formed between the diffusion layer 10 and the substrate layer 12 by ion implantation. The intermediate layer 11 is formed by ion implantation between the substrate layer 12 and the diffusion layer 10. And because the doping concentration of the intermediate layer 11 is lower than that of the diffusion layer 10, the tolerance of the semiconductor to pulsed voltage can be improved in this way.

[0035] A drift layer is formed by ion implantation in the region of the diffusion layer 10 of a single VDMOS cell near the gate 3. The drift layer is divided into a lightly doped drift layer 13 and a heavily doped drift layer 14. And because the drift layer adopts a double-layer design, the influence of the peak voltage can be effectively reduced in this way. The doping concentration of the heavily doped drift layer 14 is the same as the concentration of the heavily doped N-well layer -6. In this way, the on-resistance between the drain and the source can be reduced after the charge channel is formed.

[0036] In this embodiment, the P-well layer includes a heavily doped P-well layer two 9, a heavily doped P-well layer one 8, a low-heavily doped P-well layer one 15, and a low-doped P-well layer two 16.

[0037] Among them, the doping concentration of the heavily doped P-well layer two 9 is 4 - 6.4×10 18 mol / cm 3 .

[0038] The doping concentration of the heavily doped P-well layer one 8 is 2 - 5.7×10 18 mol / cm 3 .

[0039] The doping concentration of the low-heavily doped P-well layer one 15 is 6 - 9.4×10 16 mol / cm 3 .

[0040] The doping concentration of the low-doped P-well layer 16 is 4 - 7×10 16 mol / cm 3 .

[0041] And the elements for doping are all boron elements.

[0042] In this embodiment, the N-well layer includes a low-doped N-well layer 5, a heavily-doped N-well layer 6, and a low-doped N-well layer 7.

[0043] Among them, the doping concentration of the substrate layer 12 is 3 - 5.4×10 18 mol / cm 3 .

[0044] The doping concentrations of the intermediate layer 11 and the lightly-doped drift layer 13 are both 2 - 3.5×10 16 mol / cm 3 .

[0045] The doping concentration of the diffusion layer 10 is 3 - 6.4×10 16 mol / cm 3 .

[0046] Among them, the doping concentrations of the heavily-doped N-well layer 6 and the heavily-doped drift layer 14 are both 5 - 7.3×10 18 mol / cm 3 .

[0047] The doping concentrations of the low-doped N-well layer 5 and the low-doped N-well layer 7 are both 6 - 8.4×10 16 mol / cm 3 .

[0048] The elements for doping and ion implantation are all phosphorus elements.

[0049] Among them, when the gate 3 is connected to the gate voltage, a charge channel 17 is formed at a position near the gate 3 inside the low-heavily-doped P-well layer 15.

[0050] In this embodiment, an oxide layer 4 is deposited between the surface of the gate 3, the source 2, and the semiconductor epitaxial layer. The oxide layer 4 can ensure the formation of the gate electric field and prevent charges from directly entering the inside of the gate 3. The heavily-doped P-well layers 9 of adjacent VDMOS cells are integrated together (as Figure 1 shown), so that the heavily-doped P-well layer 9 can isolate the mutual diffusion of charges in the N-well layers of adjacent VDMOS cells.

[0051] In this embodiment, the cross-sectional profile thicknesses of the heavily doped P-well layer 1-8, the lightly doped P-well layer 1-15, and the lightly doped P-well layer 2-16 are the same. The lightly doped P-well layer 1-15 is in ohmic contact with the heavily doped drift layer 14, and the lightly doped P-well layer 2-16 is in ohmic contact with the lightly doped drift layer 13. Among them, the heavily doped P-well layer 1-8, the lightly doped P-well layer 1-15, and the lightly doped P-well layer 2-16 are arranged at intervals, which can effectively reduce the lateral penetration of the gate electric field into the P-well layer and reduce the influence of the gate electric field on adjacent VDMOS cells.

[0052] In this embodiment, the heavily doped N-well layer 1-6 is located between the lightly doped N-well layer 1-5 and the lightly doped N-well layer 2-7. The lightly doped N-well layer 1-5, the heavily doped N-well layer 1-6, and the lightly doped N-well layer 2-7 are all in ohmic contact with the source electrode 2. The heavily doped N-well layer 1-6 is in ohmic contact with the lightly doped P-well layer 1-15, and the lightly doped N-well layer 2-7 is in ohmic contact with both the heavily doped P-well layer 1-8 and the lightly doped P-well layer 2-16 (as Figure 2 shown). The N-well layer is also designed with three levels, which can reduce the excessive lateral penetration of the gate electric field into the charges inside the N-well layer.

[0053] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions, or substitutions made by those of ordinary skill in the art within the scope of the essence of the present invention also belong to the protection scope of the present invention.

Claims

1. A VDMOS transistor, characterized in that, It includes a VDMOS structure composed of a number of VDMOS cells arranged side by side. Each VDMOS cell includes a drain (1), a source (2), a gate (3), and a semiconductor epitaxial layer; The semiconductor epitaxial layer includes a substrate layer (12), a diffusion layer (10), a P-well layer, and an N-well layer; Among them, in a single VDMOS cell, an intermediate layer (11) is formed between the diffusion layer (10) and the substrate layer (12) by ion implantation; Inside the diffusion layer (10) of a single VDMOS cell, a drift layer is formed by ion implantation near the gate (3) region, and the drift layer is divided into a lightly doped drift layer (13) and a heavily doped drift layer (14); The P-well layer includes a heavily doped P-well layer two (9), a heavily doped P-well layer one (8), a lowly heavily doped P-well layer one (15), and a lowly doped P-well layer two (16); The N-well layer includes a lowly doped N-well layer one (5), a heavily doped N-well layer one (6), and a lowly doped N-well layer two (7); Among them, when the gate (3) is connected to a gate voltage, a charge channel (17) is formed inside the lowly heavily doped P-well layer one (15) near the gate (3); 2. The VDMOS transistor according to claim 1, wherein: An oxide layer (4) is deposited between the surface of the gate (3), the source (2), and the semiconductor epitaxial layer; 3. The VDMOS transistor according to claim 1, wherein: The heavily doped P-well layer two (9) between adjacent VDMOS cells is integrated together; 4. The VDMOS transistor according to claim 1, wherein: The cross-sectional profile thicknesses of the heavily doped P-well layer one (8), the lowly heavily doped P-well layer one (15), and the lowly doped P-well layer two (16) are the same; 5. The VDMOS transistor according to claim 4, characterized in that: The lowly heavily doped P-well layer one (15) is in ohmic contact with the heavily doped drift layer (14), and the lowly doped P-well layer two (16) is in ohmic contact with the lightly doped drift layer (13); 6. The VDMOS transistor according to claim 1, wherein: The heavily doped N-well layer one (6) is located between the lowly doped N-well layer one (5) and the lowly doped N-well layer two (7); 7. The VDMOS transistor according to claim 6, characterized in that: The lowly doped N-well layer one (5), the heavily doped N-well layer one (6), and the lowly doped N-well layer two (7) are all in ohmic contact with the source (2); 8. The VDMOS transistor according to claim 7, wherein: The heavily doped N-well layer one (6) is in ohmic contact with the lowly heavily doped P-well layer one (15), and the lowly doped N-well layer two (7) is in ohmic contact with both the heavily doped P-well layer one (8) and the lowly doped P-well layer two (16);

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