Multilayer micro-display chip based on highlight display

Abstract

The utility model relates to a micro display chip based on highlight display, comprising a driving wafer and at least two pixel layers, the driving wafer is provided with an anode contact and a cathode contact; all the pixel layers are sequentially stacked on the driving wafer in the Z direction, a common cathode layer and at least one sub-pixel are arranged in each pixel layer, a metal mesh layer is arranged on the upper portion of each common cathode layer, the sub-pixels are wrapped in the common cathode layers, the upper portions of the sub-pixels are electrically connected with the cathode contacts through the common cathode layers, and the metal mesh layers are arranged on the upper portions of the sub-pixels. The lower parts of the sub-pixels are electrically connected with the corresponding anode contacts through bonding metal pieces; wherein light emitted by sub-pixels in the lower pixel layer is emitted through a first gap in the upper pixel layer, and the first gap is formed in the metal mesh layer. According to the utility model, the light loss can be effectively reduced, and the light extraction efficiency is higher, so that the brightness of the micro-display chip is effectively improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a multi-layer micro-display chip based on high-brightness display. Background Art

[0002] In the field of LED display, micro-display technology has been widely developed in recent years, especially Micro-LED display technology, which has the advantages of high efficiency, low power consumption, high integration and high stability, and is considered to be one of the most promising next-generation new display and light-emitting devices. Micro-LED display technology has now been widely applied to near-eye display terminal products, including virtual reality (VR), augmented reality (AR), mixed reality (MR), etc. In the existing micro-display chip, a plurality of pixel units arranged in an array are usually arranged in the display area. In order to further reduce the horizontal size of the micro-display chip and increase the pixel density, in the prior art, the chip can be set into a vertically stacked multi-layer structure, and each layer is provided with light-emitting pixel units. Generally, a common cathode layer is arranged outside the pixel units to realize the cathode connection of the pixel units. In order to increase the cathode current, a metal enhancement layer is also arranged on the common cathode layer. However, the metal enhancement layer is likely to affect the light emission of the lower-layer pixel units. When the light emitted by the lower-layer pixel units shoots upward, it needs to pass through the metal enhancement layer, thereby generating certain light loss and reducing the brightness of the finally emitted light, which cannot meet the use requirements. Summary of the Utility Model

[0003] Therefore, the technical problem to be solved by the utility model is to overcome the defect that the brightness of the multi-layer micro-display chip in the prior art is relatively low.

[0004] To solve the above technical problem, the utility model provides a micro-display chip based on high-brightness display, including,

[0005] A driving wafer, on which an anode contact and a cathode contact are arranged;

[0006] At least two pixel layers, and all the pixel layers are sequentially stacked on the driving wafer along the Z direction. A common cathode layer and at least one sub-pixel are arranged in each pixel layer. A metal mesh grid layer is arranged on the upper part of the common cathode layer. The sub-pixels are all coated in the common cathode layer. The upper part of the sub-pixels is electrically connected to the cathode contact through the common cathode layer, and the lower part of the sub-pixels is electrically connected to the corresponding anode contact through bonding metal parts;

[0007] Wherein, the light emitted by the sub-pixels in the lower pixel layer exits through a first notch in the upper pixel layer, and the first notch is opened on the metal mesh grid layer.

[0008] In an embodiment of the present utility model, the length of the first notch in the upper pixel layer in the X direction is greater than the top surface length of the corresponding sub-pixel in the lower layer, where the X direction is perpendicular to the Z direction.

[0009] In an embodiment of the present utility model, the light emitted by the sub-pixels in the lower pixel layer sequentially exits through the second notch and the first notch in the upper pixel layer. The second notch is formed on the common cathode layer, and the length of the second notch in the X direction is greater than the top surface length of the corresponding sub-pixel in the lower layer.

[0010] In an embodiment of the present utility model, the thickness of the metal mesh grid layer is 100 nm to 5000 nm.

[0011] In an embodiment of the present utility model, an insulating passivation layer is provided in each pixel layer. The sub-pixels are all coated in the insulating passivation layer. The common cathode layer is coated outside the insulating passivation layer. The upper part of the insulating passivation layer has an opening. The upper part of the sub-pixel is electrically connected to the common cathode layer through the opening. A bonding metal part is provided on one side of each sub-pixel close to the driving wafer. The bonding metal part is electrically connected to the corresponding anode contact, and the bonding metal part is located inside the insulating passivation layer.

[0012] In an embodiment of the present utility model, each sub-pixel includes a P-type semiconductor layer, an active layer, and an N-type semiconductor layer sequentially arranged in the Z direction. A bonding metal part is provided on one side of the P-type semiconductor layer close to the driving wafer. The N-type semiconductor layer is electrically connected to the common cathode layer through the opening.

[0013] In an embodiment of the present utility model, the bonding metal part of the sub-pixel in the upper pixel layer is electrically connected to the corresponding anode contact by an anode connecting part passing through the lower pixel layer.

[0014] In an embodiment of the present utility model, the sub-pixels are trapezoidal or cylindrical.

[0015] In an embodiment of the present utility model, the thickness of the common cathode layer is 50 nm to 500 nm.

[0016] In an embodiment of the present utility model, a color conversion member is further included. The color conversion member is provided in one pixel layer. An excitation pixel is provided in the pixel layer adjacent to the lower layer of the pixel layer where the color conversion member is located. Each color conversion member and the excitation pixel correspond one by one, and the color conversion member is located on the light output path of the corresponding excitation pixel.

[0017] The above technical solution of the present utility model has the following advantages compared with the prior art:

[0018] The multi-layer micro-display chip based on high-brightness display described in the present utility model can effectively reduce light loss and has a higher light extraction efficiency, thereby effectively improving the brightness of the micro-display chip and achieving high-brightness display. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to make the content of the present utility model easier to be clearly understood, the following further describes the present utility model in detail according to the specific embodiments of the present utility model in conjunction with the accompanying drawings.

[0020] Figure 1 is a comparison schematic diagram of trapezoidal pixels and hemispherical pixels;

[0021] Figure 2 is a schematic internal structure diagram of the multi-layer micro-display chip based on high-brightness display of the present utility model;

[0022] Figure 3 is Figure 2 a partial enlarged view at Q in

[0023] Figure 4 is Figure 2 a partial enlarged view at U in

[0024] Figure 5 is a schematic internal structure diagram of the second micro-display chip of the present utility model;

[0025] Figure 6 is Figure 5 a partial enlarged view at S in

[0026] Figure 7 is a schematic internal structure diagram of the third micro-display chip of the present utility model;

[0027] DESCRIPTION OF THE REFERENCE NUMERALS IN THE DRAWINGS:

[0028] 10. Driving wafer; 101. Anode contact; 102. Cathode contact;

[0029] 20. Sub-pixel; 201. P-type ohmic contact layer; 202. P-type semiconductor layer; 203. Active layer; 204. N-type semiconductor layer; 205. N-type ohmic contact layer;

[0030] 30. Pixel layer; 301. Insulating body; 302. Bonding metal part; 303. Insulating passivation layer; 3031. Opening; 304. Common cathode layer; 3041. Second notch; 305. Metal mesh grid layer; 3051. First notch; 306. Anode connecting part; 307. Cathode connecting part; 308. Filling hole; 309. Isolation layer;

[0031] 40. Exciting pixel;

[0032] 50. Color conversion part;

[0033] 60. Lens. Specific Embodiment

[0034] The present utility model will be further described below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present utility model and be able to implement it. However, the embodiments cited are not intended to limit the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and in no way limits the present disclosure, its application or use.

[0035] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "vertical", "upper", "lower", "top", "side", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present utility model. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present utility model, unless otherwise specified, the meaning of "plurality" is two or more.

[0036] In the description of the present utility model, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected" and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0037] The following will be combined with Figures 1-7 to further describe the structure of this embodiment.

[0038] It should be noted that for convenience of description, in the present invention, the microdisplay chip has a Z direction and an X direction perpendicular to each other, where the Z direction is generally the direction away from the driving wafer. In the present invention, "up" and "down" are relative in the Z direction. Similarly, "top", "bottom", "high", and "low" are also relative in the Z direction. The top pixel layer refers to the uppermost pixel layer, and the bottom pixel layer refers to the lowermost pixel layer. Among them, the bottom pixel layer is also referred to as the first pixel layer, and the pixel layers stacked in sequence above are the second layer, the third layer, and so on in sequence.

[0039] Embodiment 1

[0040] Refer to Figures 2-4 , this embodiment discloses a microdisplay chip based on high-brightness display, including a driving wafer 10 and at least two layers of pixel layers 30; wherein, the driving wafer 10 has a driving circuit inside for controlling the sub-pixels 20 in the pixel layer 30 to emit light, and the driving wafer 10 can adopt a CMOS driving wafer;

[0041] An anode contact 101 and a cathode contact 102 are arranged on the driving wafer 10;

[0042] All the pixel layers 30 are sequentially stacked on the driving wafer 10 along the Z direction;

[0043] In each pixel layer 30: a common cathode layer 304 and at least one sub-pixel 20 are arranged in the pixel layer 30. A metal mesh layer 305 is arranged above the common cathode layer 304 to achieve the effect of enhancing the cathode current through the metal mesh layer 305; the sub-pixels 20 are all coated in the common cathode layer 304. The upper part of the sub-pixel 20 is electrically connected to the cathode contact 102 through the common cathode layer 304, and the lower part of the sub-pixel 20 is electrically connected to the corresponding anode contact 101 through a bonding metal part 302;

[0044] Among them, the light emitted by the sub-pixels 20 in the lower pixel layer is emitted through the first notch 3051 in the upper pixel layer. The first notch 3051 is opened on the metal mesh layer 305 of this layer (upper layer), so that the light emitted by the lower sub-pixels 20 can be emitted through the first notch 3051 to the greatest extent, improving the light extraction efficiency of the pixels.

[0045] In the above structure, by opening the first notch 3051 on the metal mesh layer 305 of the upper pixel layer, that is, removing the metal mesh material in the first notch 3051, the shielding of the light emitted by the lower sub-pixels 20 by the metal mesh material in the original notch is reduced, so that the light emitted by the sub-pixels 20 in the lower pixel layer does not have to be emitted through the metal mesh layer 305, reducing light loss, having a higher light extraction efficiency for the lower sub-pixels 20, and thus improving the light output brightness of the microdisplay chip.

[0046] It can be understood that, during specific setting, a first notch 3051 can be set on the metal mesh layer 305 of at least one pixel layer among all the upper pixel layers through which the light-emitting path of the sub-pixel 20 passes, or the first notch 3051 can be set on the metal mesh layers of all the upper pixel layers through which the light-emitting path of the sub-pixel 20 passes.

[0047] In some embodiments, the length L1 of the first notch 3051 in the X direction in the upper pixel layer is greater than the top surface length L2 of the corresponding sub-pixel 20 in the lower layer, where the X direction is perpendicular to the Z direction.

[0048] It can be understood that the "corresponding sub-pixel" here refers to the sub-pixel 20 in the lower layer whose emitted light passes through the first notch 3051; if the sizes of all the sub-pixels in the lower layer are the same, then the length of the first notch 3051 in the X direction is greater than the top surface length of each sub-pixel in the lower layer.

[0049] The opening quantity of the above-mentioned first notch 3051 can be determined according to the quantity of the sub-pixels in the lower layer.

[0050] Among them, the metal mesh layer 305 in each pixel layer 30 is an integral body, and the first notch 3051 is equivalent to a hole opened on the metal mesh layer 305.

[0051] In some embodiments, the thickness of the common cathode layer 304 is 50 nm to 500 nm, so as to increase its transmittance as much as possible while ensuring the current spreading ability. The thicker the thickness of the common cathode layer 304, the better the current spreading, but the lower the transmittance, which will cause greater light loss and increase the processing difficulty at the same time. If the thickness is too thin, it will affect the metal current spreading ability.

[0052] The above method can set notches only on the metal mesh layer 305, and not on the common cathode layer 304.

[0053] In some embodiments, an insulating and passivating layer 303 is provided in each pixel layer 30. The sub-pixels 20 are all coated in the insulating and passivating layer 303. The outside of the insulating and passivating layer 303 is coated with a common cathode layer 304. The upper part of the insulating and passivating layer 303 has an opening 3031. The upper part of the sub-pixel 20 is electrically connected to the common cathode layer 304 through the opening 3031. A bonding metal part 302 is provided on one side of the sub-pixel 20 close to the driving wafer 10. The bonding metal part 302 is electrically connected to the corresponding anode contact 101, and the bonding metal part 302 is located inside the insulating and passivating layer 303.

[0054] Among them, each pixel layer 30 includes an insulating body 301, and the sub-pixels 20 in the pixel layer 30 are all coated inside the insulating body 301;

[0055] Furthermore, each sub-pixel 20 includes a P-type semiconductor layer 202, an active layer 203, and an N-type semiconductor layer 204 that are sequentially arranged along the Z direction. The active layer 203 is used for emitting light. Bonding metal parts 302 are arranged on the side of the P-type semiconductor layer 202 close to the driving wafer 10. The N-type semiconductor layer of the sub-pixel 20 is electrically connected to the common cathode layer 304 through the opening 3031 of the external insulating and passivating layer 303, and the common cathode layer 304 is used for electrically connecting to the cathode contact 102. The P-type semiconductor layer 202 of the sub-pixel 20 is used for electrically connecting to the anode contact 101 through the bonding metal part 302. The insulating and passivating layer 303 is used for insulating and isolating the N-type semiconductor layer 204 and the P-type semiconductor layer 202 in the sub-pixel 20 to avoid short circuit.

[0056] The bonding metal parts 302 can correspond to the anode contacts 101 one by one, or multiple anode contacts 101 can correspond to one bonding metal part 302.

[0057] In some embodiments, the pixel body includes a P-type ohmic contact layer 201, a P-type semiconductor layer 202, an active layer 203, and an N-type semiconductor layer 204 that are sequentially arranged along the Z direction;

[0058] Among them, the active layer 203 is used for emitting light. Bonding metal parts 302 are arranged on the side of the P-type semiconductor layer 202 close to the driving wafer 10. A P-type ohmic contact layer 201 is arranged between the P-type semiconductor layer 202 and the bonding metal part 302 to better achieve ohmic contact between the P-type semiconductor layer 202 and the bonding metal part 302. Thus, finally, the P-type semiconductor layer 202 of the sub-pixel 20 is electrically connected to the corresponding anode contact 101 through the bonding metal part 302 to achieve anode connection; the N-type semiconductor layer of the sub-pixel 20 is exposed at the opening 3031, and the exposed part is electrically connected to the common cathode layer 304. The common cathode layer 304 is used for connecting to the cathode contact 102 of the driving wafer 10 to achieve cathode connection.

[0059] Furthermore, an N-type ohmic contact layer 205 can also be arranged on the upper surface of the N-type semiconductor layer 204. It can be understood that at this time, the opening 3031 of the insulating and passivating layer 303 only needs to expose the N-type ohmic contact layer 205.

[0060] Furthermore, the thickness of the N-type ohmic contact layer 205 is 10 nm to 300 nm, and its material can be a transparent conductive thin film such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or a metal alloy thin film such as gold germanium alloy (AuGe), gold nickel alloy (AuNi),

[0061] Preferably, the thickness of the N-type ohmic contact layer 205 is 10 nm to 100 nm to ensure ohmic contact while also having a high transmittance, thereby reducing optical loss.

[0062] In some embodiments, the thickness of the P-type ohmic contact layer 201 is 10 nm to 300 nm, and its material can be a transparent conductive thin film such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., or a metal alloy thin film such as AuBe, AnZn, etc.

[0063] In some embodiments, the thickness of the insulating and passivating layer 303 is 30 nm to 500 nm to preferably ensure the insulation and passivation capabilities.

[0064] In some embodiments, the bonding metal part 302 of the sub-pixel 20 in the upper pixel layer is electrically connected to the corresponding anode contact 101 by the anode connecting part 306 passing through the lower pixel layer, so as to conveniently realize anode connection.

[0065] The above-mentioned anode connecting part 306 can penetrate all the lower pixel layers 30, or only penetrate one or more pixel layers 30.

[0066] In one of the embodiments, the length of the top end of the anode connecting part 306 in the X direction is greater than the length of the bottom end, that is, it has a structure form of wider at the top and narrower at the bottom. When the length of the bottom end is the same, compared with the structure of narrower at the top and wider at the bottom, this shape of structure can obtain a thicker anode connecting part 306, thereby enhancing the anode electrical transmission ability.

[0067] In some embodiments, the common cathode layer 304 in the upper pixel layer is electrically connected to the cathode contact 102 by the cathode connecting part passing through the lower pixel layer, so as to conveniently realize cathode connection.

[0068] The structure of the cathode connecting part 307 can be the same as that of the anode connecting part 306, and will not be elaborated here.

[0069] In some embodiments, the thickness d of the metal mesh layer 305 is 100 nm to 5000 nm. This thickness is relatively thin, which increases the distance between the metal mesh layer 305 and the upper bonding metal part 302, so that there is enough space between the metal mesh layer 305 and the upper bonding metal part 302 to fill the insulating body 301, thereby effectively avoiding the risk of short circuit between the metal mesh layer 305 and the upper bonding metal part 302, making the insulation better and the safety higher.

[0070] Furthermore, the metal mesh layer 305 can be made of one or more of Cr, Pt, Ti, Au, Al, Cu, TiN, and TaN.

[0071] In some embodiments, both the P-type semiconductor layer 202 and the N-type semiconductor layer 204 can be made of materials such as gallium nitride (GaN), and the active layer 203 can be made of materials such as indium gallium nitride (InGaN).

[0072] In one embodiment, the insulating and passivating layer 303 can be made of one or more of aluminum oxide, silicon dioxide, and silicon nitride.

[0073] In one embodiment, the insulating body 301 can be made of one or more of silicon oxide, silicon nitride, silicon carbide (SiC), silicon carbonitride (SiCN), phosphosilicate glass (PSG), and borophosphosilicate glass (BPSG).

[0074] In one embodiment, the common cathode layer 304 includes one or more of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), aluminum-doped indium tin oxide, silver-doped indium tin oxide, and gold-doped indium tin oxide;

[0075] In one embodiment, the material of the anode connecting member 306 can be one or more of aluminum, copper, and tungsten.

[0076] Further, the material of the cathode connecting member 307 can be the same as that of the anode connecting member 306, and it can be a conductive material.

[0077] In one embodiment, the material of the bonding metal member 302 can be one of Al, Au, and Cu, or a laminated structure of Ni, Au, Cu, etc. and Sn, or a bonding laminate of Au and In, Ge, or a bonding laminate of Au and Si.

[0078] Further, the above-mentioned bonding metal member 302 can adopt the following structural form: Cr 2nm / Pt 50nm / Ti 10nm / Pt 50nm / Au 100nm / Sn 150nm / Au 50nm, where Cr is an adhesion layer, and Pt / Ti / Pt is a barrier layer.

[0079] In some solutions, the sub-pixel 20 is trapezoidal or cylindrical.

[0080] As Figure 1 shown, the sub-pixel 20 is trapezoidal or cylindrical. Compared with pixels having a hemispherical structure or a semi-ellipsoidal structure, the trapezoidal or cylindrical pixels can effectively increase the pixel light-emitting area, thereby increasing the light-emitting intensity; generally, an active layer 203 is provided in the pixel to emit light. From Figure 1It can be seen that when the bottom size of the pixels is the same, the area of the active layer in the trapezoidal pixels (the entire shaded part) is larger than the area of the active layer in the hemispherical pixels (the shaded part inside the hemisphere), thus effectively increasing the light emission intensity. Similarly, compared with the hemispherical pixels, the cylindrical pixels can also increase the area of the active layer, thereby effectively increasing the light emission intensity.

[0081] In some embodiments, the height D of the sub-pixel 20 in the Z direction is 0.3um to 5um; preferably, D is 0.3um to 1.5um; wherein, the height of the sub-pixel 20 is the distance between the P-type semiconductor layer 202 and the N-type semiconductor layer 204 (including the thicknesses of the P-type semiconductor layer and the N-type semiconductor layer itself).

[0082] Furthermore, the inclination angle θ of the side wall of the sub-pixel 20 relative to the driving wafer 10 is 45° to 135°; it can be understood that the side wall of the sub-pixel 20 here refers to the wall surface between the top surface and the bottom surface of the sub-pixel 20;

[0083] The above inclination angle can reduce total internal reflection and is more conducive to light extraction. Beyond this range, the light extraction efficiency will be reduced; in addition, due to limited horizontal space, a certain space needs to be reserved for subsequent processes. When the inclination angle is too small, the bottom surface of the pixel occupies too much horizontal space, which will increase the difficulty of pixel pitch arrangement.

[0084] Preferably, the inclination angle θ of the side wall of the sub-pixel 20 relative to the driving wafer 10 is 75° to 105°, which has the best light extraction efficiency and the best pixel pitch design.

[0085] In one of the embodiments, at least one lens 60 is connected to the upper part of the pixel layer 30 located at the top layer. When arranging the lens 60, the following two methods can be adopted. One is that multiple sub-pixels 20 correspond to one lens 60, and the other is that each lens 60 corresponds to one sub-pixel 20 one by one. This method can better collimate the outgoing light of each sub-pixel 20 and further reduce light interference.

[0086] In some embodiments, the outgoing light colors of the sub-pixels 20 in each layer of the pixel layer 30 can be different to achieve multi-color configuration, or the outgoing light colors of the sub-pixels 20 in each layer of the pixel layer 30 can be the same to achieve multi-layer monochromatic configuration.

[0087] Embodiment 2

[0088] Refer to Figures 5-6, the main difference between this embodiment and the first embodiment is that: the light emitted from the sub-pixel 20 in the lower pixel layer is sequentially emitted after passing through the second notch 3041 and the first notch 3051 in the upper pixel layer. The second notch 3041 in the upper pixel layer is opened on the common cathode layer 304, and the length L3 of the second notch 3041 in the X direction is greater than the top surface length L2 of the corresponding sub-pixel 20 in the lower layer.

[0089] It can be understood that the "corresponding sub-pixel" here refers to the sub-pixel 20 whose emitted light sequentially passes through the second notch 3041 and the first notch 3051. If the sizes of all sub-pixels in the lower layer are the same, then the length of the second notch 3041 in the X direction is greater than the top surface length of each sub-pixel in this layer.

[0090] By opening the second notch 3041 on the common cathode layer 304 of the upper pixel layer in the above manner, that is, removing the common cathode material in the second notch 3041, the light emitted from the sub-pixel 20 in the lower pixel layer does not have to be emitted through the common cathode, further reducing light loss, having a higher light extraction efficiency for the lower sub-pixel 20, and thus improving the light output brightness of the microdisplay chip.

[0091] The number of the above-mentioned second notches 3041 can be determined according to the number of sub-pixels 20 in the lower layer, and the second notches 3041 and the first notches 3051 can correspond one by one.

[0092] It can be understood that the common cathode layer 304 in each pixel layer 30 is an integral body, and the second notch 3041 is equivalent to a hole opened on the common cathode layer 304.

[0093] Embodiment Three

[0094] Refer to Figure 7 , the main difference between this embodiment and the first and second embodiments is that: the microdisplay chip further includes a color conversion component 50. The color conversion component 50 is disposed in a pixel layer 30. An excitation pixel 40 is disposed in the adjacent pixel layer below the pixel layer where the color conversion component 50 is located. Each color conversion component 50 and the excitation pixel 40 correspond one by one. The color conversion component 50 is located on the light output path of the corresponding excitation pixel 40, so that the light emitted by the excitation pixel 40 irradiates the color conversion component 50 to excite the color conversion component 50 to emit light of a specific color;

[0095] It can be understood that the excitation pixel 40 can also be electrically connected to the driving wafer 10 to control the excitation pixel 40 to emit light by using the driving wafer 10.

[0096] The material of the color conversion component 50 can be a quantum dot material or a phosphor material.

[0097] Among them, the structure of the excitation pixel 40 is the same as that of the sub-pixel 20. Bonding metal parts 302 are provided on one side of the excitation pixel 40 close to the driving wafer 10. The bonding metal parts 302 of the excitation pixel 40 are electrically connected to the anode contacts 101 of the driving wafer 10; an insulating passivation layer 303 is coated outside each excitation pixel 40. The bonding metal parts 302 are located inside the insulating passivation layer 303. An opening 3031 is provided at the upper part of the insulating passivation layer 303. A common cathode layer 304 is coated outside the insulating passivation layer 303. The excitation pixel 40 is electrically connected to the common cathode layer 304 through the opening 3031. The common cathode layer 304 is used to be electrically connected to the cathode contact 102 to realize the connection between the excitation pixel 40 and the cathode of the driving wafer 10.

[0098] In some embodiments, the light emission color of the sub-pixel 20 in the pixel layer where the color conversion member 50 is located is different from the light emission color of the color conversion member 50.

[0099] For example, the light emission color of the sub-pixel 20 in the pixel layer where the color conversion member 50 is located is green, and the color of the light finally emitted by the color conversion member 50 excited by the excitation pixel 40 is red; the light emission color of the excitation pixel 40 is also blue;

[0100] It should be noted that the light emission wavelength of the excitation pixel 40 needs to be less than the red light wavelength, so as to use the light with a shorter wavelength to excite the color conversion member 50 to perform color conversion and emit red light. The red light color conversion member 50 is made of a quantum dot material or a red phosphor material.

[0101] In some embodiments, the red light color conversion member 50 can be made of a quantum dot material, such as indium phosphide (InP); it can also be made of a phosphor material, such as fluoride-based phosphor-KSF red phosphor (K2SiF6:Mn4+), or nitride Eu2+-doped CaAlSiN3-based red phosphor, etc.

[0102] In some embodiments, filling holes 308 are provided in the pixel layer 30 where the color conversion member 50 is located. Each filling hole 308 is filled with a color conversion material to form the color conversion member 50.

[0103] Furthermore, the filling holes 308 are opened in the insulating body 301 of the pixel layer 30.

[0104] In some embodiments, the length Ls of the filling hole 308 in the X direction is not less than the maximum length of the excitation pixel 40 in the X direction, and the X direction is perpendicular to the Z direction. In this way, a good light channel can be provided for the underlying excitation pixel 40 and light crosstalk is not likely to occur, so as to ensure the color conversion effect to the greatest extent.

[0105] Furthermore, the inner wall of the filling hole 308 is inclined relative to the driving wafer 10, and the inclination angle C is 60° to 90°, which is more convenient for etching and can also ensure the filling effect.

[0106] In some embodiments, an isolation layer 309 is formed on the inner wall of the filling hole 308; the isolation layer 309 is used to shield the light interference from the pixels below the non-filling space, so that the color conversion member 50 inside the filling hole 308 can have a better color conversion effect.

[0107] Among them, the isolation layer 309 is a metal reflection layer or a light absorption layer.

[0108] The material of the metal reflection layer can be one or more of metals Al, Ti, Pt, Au, Cr, and Ni to shield light interference through metal reflection; the material of the light absorption layer can be light-absorbing materials such as carbon film, black glue, and polysilicon to shield light interference through light absorption.

[0109] Furthermore, the thickness of the isolation layer 309 is 50 nm to 2 μm. If the thickness is too thin, it is easy to leak electricity, and if it is too thick, the cost will increase.

[0110] Specifically, it can be carried out according to the thickness required to achieve light interference shielding for different materials. For example, Al ≥ 50 nm and black glue ≥ 1 μm.

[0111] In the third embodiment, the color conversion of the sub-pixel light emission is realized through the color conversion member 50.

[0112] The microdisplay chip of the above embodiments can reduce light loss and has a higher light extraction efficiency, thereby effectively improving the brightness of the microdisplay chip and realizing high-brightness display.

[0113] All the above optional technical solutions can be combined arbitrarily to form optional embodiments of the present invention, that is, any multiple embodiments can be combined to meet the requirements of different application scenarios, and all are within the protection scope of this application, and will not be elaborated here one by one.

[0114] It should be noted that the above embodiments are only examples for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

1. A microdisplay chip based on highlighting, characterized in that: Including, a driving wafer, on which an anode contact and a cathode contact are provided; at least two pixel layers, all the pixel layers are sequentially stacked on the driving wafer in the Z direction, a common cathode layer and at least one sub-pixel are provided in each pixel layer, a metal mesh layer is provided on the upper part of the common cathode layer, the sub-pixels are all coated in the common cathode layer, the upper part of the sub-pixels is electrically connected to the cathode contact through the common cathode layer, and the lower part of the sub-pixels is electrically connected to the corresponding anode contact through bonding metal parts; wherein, the light emitted by the sub-pixels in the lower pixel layer is emitted through a first notch in the upper pixel layer, and the first notch is formed in the metal mesh layer.

2. The microdisplay chip based on highlighting according to claim 1, wherein: The length of the first notch in the upper pixel layer in the X direction is greater than the top surface length of the corresponding sub-pixel in the lower layer, wherein the X direction is perpendicular to the Z direction.

3. The microdisplay chip based on highlighting according to claim 1, wherein: The light emitted by the sub-pixels in the lower pixel layer is sequentially emitted through a second notch and a first notch in the upper pixel layer, the second notch is formed in the common cathode layer, and the length of the second notch in the X direction is greater than the top surface length of the corresponding sub-pixel in the lower layer.

4. The microdisplay chip based on highlighting according to claim 1, wherein: The thickness of the metal mesh layer is 100 nm to 5000 nm.

5. The microdisplay chip based on highlighting according to claim 1, wherein: An insulating and passivating layer is provided in each pixel layer, the sub-pixels are all coated in the insulating and passivating layer, the common cathode layer is coated outside the insulating and passivating layer, the upper part of the insulating and passivating layer has an opening, the upper part of the sub-pixels is electrically connected to the common cathode layer through the opening, a bonding metal part is provided on one side of each sub-pixel close to the driving wafer, the bonding metal part is electrically connected to the corresponding anode contact, and the bonding metal part is located inside the insulating and passivating layer.

6. The microdisplay chip based on highlighting according to claim 5, wherein: Each sub-pixel includes a P-type semiconductor layer, an active layer and an N-type semiconductor layer sequentially arranged in the Z direction, a bonding metal part is provided on one side of the P-type semiconductor layer close to the driving wafer, and the N-type semiconductor layer is electrically connected to the common cathode layer through the opening.

7. The highlighted microdisplay chip according to claim 5, wherein: The bonding metal parts of the sub-pixels in the upper pixel layer are electrically connected to the corresponding anode contacts by anode connecting parts passing through the anode contacts of the lower pixel layer.

8. The microdisplay chip based on highlighting according to claim 1, characterized in that: The sub-pixels are trapezoidal or cylindrical.

9. The microdisplay chip based on highlighting according to claim 1, wherein: The thickness of the common cathode layer is 50 nm to 500 nm.

10. The microdisplay chip based on highlighting according to claim 1, characterized in that: It further includes a color conversion member, the color conversion member is provided in one pixel layer, an excitation pixel is provided in the adjacent pixel layer below the pixel layer where the color conversion member is located, each color conversion member and the excitation pixel correspond to each other, and the color conversion member is located on the light output path of the corresponding excitation pixel.

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