Wafer structure
By setting a barrier in the cutting channel of the wafer structure, the problem of protective film adhesion and acid infiltration is solved by using a protective film with weak adhesion, which improves product yield and reduces production costs.
Patent Information
- Application Number
- CN202420391789.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-29
- Publication Date
- 2025-07-11
- Estimated Expiration
- 2034-02-28
AI Technical Summary
In the prior art, the gap between the wafer structure between the cutting channel and the protective film causes the protective film with strong adhesion to be easily adhered to and broken, the protective film with weak adhesion is poor in coating effect, the acid liquid is prone to penetrate into the chip area and corrosion, the process requirements are high and the cost is increased.
A barrier is provided in the cutting path to fill part of the cutting path and coated with a protective film with weak adhesion to prevent acid infiltration, avoid corrosion and reduce production costs.
It improves product yield, reduces process requirements and production costs, simplifies operating procedures, and avoids corrosion of the chip by acid.
Smart Images
Figure CN223092863U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the technical field of electronic devices, and particularly relates to a wafer structure. Background Art
[0002] The wafer structure can be applied to the motor drive system of a vehicle and plays an important role.
[0003] In the prior art, the wafer structure includes a base layer, and a plurality of scribe lines arranged vertically and horizontally are provided on the base layer to divide the base layer into a plurality of chip areas, and the chip areas are used to arrange chips. In the subsequent processing of the wafer structure, a protective film is usually used to bond and cover the scribe lines and chip areas of the wafer structure, and then an acid solution is used to corrode and clean the back part of the wafer structure.
[0004] However, since there is a gap between the scribe line and the protective film, if a protective film with strong adhesion, such as a UV (Ultraviolet ray) film, is used, it is easy to adhere to the film sticking tool and cause fragmentation when the protective film is torn off, reducing the yield. And the protective film needs to be torn off in a short time, otherwise it is easy to leave the adhesive on the protective film, which has high process requirements and increases the production cost. If a protective film with weak adhesion, such as a blue film, is used, the covering effect of the protective film on the scribe line and chip area is not good, resulting in the acid solution being easily infiltrated into the scribe line and reaching the chip area to corrode the chip. Summary of the Utility Model
[0005] In view of the above problems, the present utility model is proposed to provide a wafer structure that overcomes or at least partially solves the above problems.
[0006] In order to solve the above technical problems, the present application is implemented as follows:
[0007] An embodiment of the present application provides a wafer structure, which includes a base layer, and at least one scribe line is provided on the base layer to divide the base layer into chip areas;
[0008] A blocking portion is provided in the scribe line, and the blocking portion fills at least part of the scribe line.
[0009] Optionally, the number of the scribe lines is multiple, at least two of the scribe lines intersect, the intersection position of the scribe lines is an intersection, and the blocking portion is provided at the intersection.
[0010] Optionally, the blocking portion is further provided at the end of the scribe line to block the end of the scribe line.
[0011] Optionally, the base layer includes a metal layer, a crystalline silicon layer, and an oxide layer stacked in sequence;
[0012] The intersection where the scribe lines intersect on the metal layer is the first intersection, and the blocking portion includes a first blocking portion disposed at the first intersection, and the first blocking portion is configured to prevent the scribe lines from communicating at the first intersection of the metal layer.
[0013] Optionally, the intersection where the scribe lines intersect on the oxide layer is the second intersection, and the blocking portion further includes a second blocking portion disposed at the second intersection, the second blocking portion is spaced apart from the first blocking portion, and the second blocking portion is configured to prevent the scribe lines from communicating at the second intersection of the oxide layer.
[0014] Optionally, the intersection where the scribe lines intersect on the crystalline silicon layer is the third intersection, and the blocking portion further includes a third blocking portion disposed at the third intersection, the third blocking portion is connected to the first blocking portion, and the third blocking portion is configured to prevent the scribe lines from communicating at the third intersection of the crystalline silicon layer.
[0015] Optionally, the wafer structure further includes a blocking ring, and the blocking ring is connected to the outer periphery of the metal layer.
[0016] Optionally, the blocking portion extends along the scribe line, and the blocking portion fills the scribe line.
[0017] Optionally, the blocking portion is a cross-shaped blocking portion.
[0018] Optionally, the cross-shaped blocking portion includes a first blocking edge and a second blocking edge, the first blocking portion and the second blocking portion are located within the scribe line, and the first blocking edge and the second blocking edge are perpendicularly connected.
[0019] Optionally, the length of the first blocking edge is any value in the range of 300 - 800 microns, and the width of the first blocking edge is any value in the range of 60 - 80 microns.
[0020] Optionally, the length of the second blocking edge is any value in the range of 300 - 800 microns, and the width of the second blocking edge is any value in the range of 60 - 80 microns.
[0021] Optionally, the scribe line includes a first scribe line and a second scribe line;
[0022] The first scribe line extends in a first direction, the second scribe line extends in a second direction, and the position where the first scribe line intersects the second scribe line is the intersection;
[0023] Wherein, the first direction is perpendicular to the second direction.
[0024] Optionally, the number of the first cutting channels includes a plurality, and the plurality of first cutting channels are arranged at intervals along the second direction;
[0025] The number of the second cutting channels includes a plurality, and the plurality of second cutting channels are arranged at intervals along the first direction.
[0026] In an embodiment of the present application, the wafer structure includes a base layer, and at least one cutting channel is provided on the base layer to separate a chip area from the base layer; a blocking portion is provided in the cutting channel, and the blocking portion fills at least a part of the cutting channel. In this way, in the subsequent process of cleaning with acid solution, a protective film with relatively weak adhesion, such as a blue film, can be used to cover the base layer of the wafer structure. Since the blocking portion fills at least a part of the cutting channel and has a blocking effect on the cutting channel, it can prevent the acid solution from penetrating into the chip area from the cutting channel and spreading along the intersection, avoiding the problem of acid corrosion to the chips and improving the acid drilling situation of the product. Moreover, there is no need to use a protective film with relatively strong adhesion, such as a UV film, avoiding the problem of easy adhesion to the film sticking tool when removing the protective film, resulting in chip breakage, improving the yield rate of the product. There is also no need to remove the protective film in a short time, reducing the process requirements and production costs.
[0027] Additional aspects and advantages of the present utility model will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the present utility model. Description of the Drawings
[0028] The above and / or additional aspects and advantages of the present utility model will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, wherein:
[0029] Figure 1 is a schematic structural diagram of a wafer structure according to an embodiment of the present application;
[0030] Figure 2 is another schematic structural diagram of a wafer structure according to an embodiment of the present application;
[0031] Figure 3 is a cross-sectional schematic diagram of a wafer structure according to an embodiment of the present application.
[0032] Reference numerals: 10 - base layer; 20 - cutting channel; 30 - chip area; 40 - blocking portion; 41 - first blocking edge; 42 - second blocking edge; 21 - first cutting channel; 22 - second cutting channel; 11 - metal layer; 12 - crystalline silicon layer; 13 - oxide layer; 23 - first intersection; 24 - second intersection; 25 - third intersection; X - first direction; Y - second direction. Detailed Embodiments
[0033] Embodiments of the present utility model will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present utility model, and should not be construed as a limitation to the present utility model. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without making creative efforts belong to the scope of protection of this application.
[0034] The terms "first" and "second" in the description and claims of this application may explicitly or implicitly include one or more of such features. In the description of the present utility model, unless otherwise specified, the meaning of "a plurality" is two or more. In addition, "and / or" in the description and claims means at least one of the connected objects. The character " / " generally indicates an "or" relationship between the related objects before and after.
[0035] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present utility model.
[0036] In the description of the present utility model, it should be noted that unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific situations.
[0037] Referring to Figures 1 to 3 , a schematic structural diagram of a wafer structure according to an embodiment of this application is shown, which may specifically include: a base layer 10, and at least one dicing channel 20 is provided on the base layer 10 to separate a chip area 30 from the base layer 10;
[0038] A blocking portion 40 is provided in the dicing channel 20, and the blocking portion 40 fills at least part of the dicing channel 20.
[0039] In the embodiments of the present application, in the subsequent process of cleaning with acid solution, a protective film with relatively weak adhesion, such as a blue film, can be used to cover the base layer 10 of the wafer structure. Due to the blocking effect of the blocking portion 40 on the scribe line 20, it can prevent the acid solution from penetrating into the scribe line 20 and spreading to the chip area 30 along the intersection, avoiding the problem of acid solution corroding the chip and improving the acid drilling situation of the product. Moreover, there is no need to use a protective film with relatively strong adhesion, such as a UV film, avoiding the problem of being easily adhered to the film-applying tool when removing the protective film, which may cause chip breakage, and improving the yield rate of the product. There is also no need to remove the protective film in a short time, reducing the process requirements and production costs.
[0040] Specifically, in the embodiments of the present application, after the acid solution cleaning process of the wafer structure is completed, the time to remove the blue film can be 72 hours, with relatively low requirements for the process production line and simple operation. While the UV film needs to be removed within 24 hours, with relatively high requirements for the process production line, otherwise it is easy to leave the glue residue of the UV film on the wafer structure, affecting its appearance and performance. Moreover, due to the relatively strong adhesion of the UV film, manual operation is required, and a UV lamp needs to be introduced for irradiation operation, resulting in low work efficiency, high production costs, and easy chip breakage. In addition, the cost price of the UV film is ten times that of the blue film, and using the blue film can also greatly reduce the production cost.
[0041] In the embodiments of the present application, by way of example, the wafer structure can be applied to the VDMOS (Vertical Diffused Metal Oxide Semiconductor) process. A layer of N-type epitaxial layer is grown using a highly doped N-type substrate, and a channel is formed by the difference in the lateral diffusion junction depth between the P-type base region and the N-type source region. The wafer structure includes a front side and a back side disposed opposite to each other. Then, the back side is thinned to the required thickness of the product using a grinding process, and then wet cleaning and metal evaporation processes are performed on the back side. Among them, in the back side process of the wafer structure, a blue film needs to be pasted on the base layer 10 of the wafer before thinning the back side to protect the front side pattern of the wafer structure from being scratched and avoid being corroded and contaminated by acid solution, etc.
[0042] In the actual production process, specifically, a scribe line 20 photomask is used to perform pattern design on the base layer 10 of the wafer structure. Therefore, the blocking portion 40 can be set by setting the shape structure of the scribe line 20 photomask.
[0043] In an embodiment of the present application, optionally, the number of scribe lanes 20 is multiple, at least two scribe lanes 20 intersect, and the intersection position of the scribe lanes 20 is the intersection, and the blocking portion 40 is disposed at the intersection. In this way, the blocking portion 40 prevents the scribe lanes 20 from communicating at the intersection, so that the blocking portion 40 blocks the acid solution at the intersection where at least two scribe lanes intersect, and prevents the acid solution from infiltrating into the chip area 30 along the intersection of at least two scribe lanes 20.
[0044] Exemplarily, as Figure 1 shown, a cross-shaped blocking portion 40 can be disposed at the intersection formed by the intersection of two scribe lanes 20. In this way, on the basis of not affecting the cutting process of the wafer structure, the blocking portion 40 can effectively block the acid solution from infiltrating into the chip area 30 along the scribe lane 20. The structure of the embodiment of the present application is simple, easy to operate, does not affect the cutting and packaging of the wafer structure, and does not require additional equipment and manual operations, etc., and can better improve the product appearance and reduce the production cost.
[0045] In an embodiment of the present application, exemplarily, the chip area 30 is rectangular. Taking the chip area 30 located in the middle area as an example, a plurality of scribe lanes 20 are arranged in a staggered manner, so that intersections of scribe lanes are formed at the four corners of the chip area 30. Blocking portions 40 are respectively disposed at the four intersections, which can block the four corners of the chip area 30 and have a good effect on preventing the acid solution from infiltrating into the chip area 30. In addition, the chip area 30 can also be trapezoidal, rhombic or triangular, etc., and the specific shape of the chip area 30 in the embodiment of the present application may not be limited.
[0046] Optionally, in an embodiment of the present application, the blocking portion 40 is also disposed at the end of the scribe lane 20 to block the end of the scribe lane 20. In this way, the blocking portion 40 can also block the acid solution at the end of the scribe lane 20, block the acid solution from infiltrating into the scribe lane 20 from the end, further improve the blocking effect of the blocking portion 40 on the acid solution, and improve the anti-corrosion effect of the chips in the chip area 30.
[0047] In an embodiment of the present application, optionally, the base layer 10 includes a metal layer, a crystalline silicon layer, and an oxide layer that are stacked in sequence; the intersection where the scribe lane 20 intersects on the metal layer is the first intersection, and the blocking portion 40 includes a first blocking portion disposed at the first intersection, and the first blocking portion is used to prevent the scribe lane 20 from communicating at the first intersection on the metal layer. In this way, the first blocking portion blocks the first intersection where the scribe lane 20 intersects on the metal layer, and prevents the acid solution from infiltrating from the first intersection on the metal layer and spreading to the chip area 30 along the first intersection.
[0048] Optionally, in the embodiments of the present application, the intersection where the scribe line 20 intersects on the oxide layer is the second intersection. The blocking portion 40 further includes a second blocking portion disposed at the second intersection. The second blocking portion is spaced apart from the first blocking portion, and the second blocking portion is used to prevent the scribe line 20 from communicating at the second intersection of the oxide layer. In this way, the second blocking portion blocks the second intersection where the scribe line 20 intersects on the oxide layer, preventing the acid solution from infiltrating from the second intersection on the oxide layer and spreading along the second intersection to the chip region 30. Moreover, the first blocking portion and the second blocking portion act together, making it difficult for the acid solution to infiltrate into the front wafer structure, further improving the avoidance effect of preventing the acid solution from infiltrating into the chip region 30.
[0049] Specifically, in the embodiments of the present application, the oxide layer of the wafer structure may be an isolation oxide layer, also known as an active layer, abbreviated as an OD (Oxide Diff) layer. The crystalline silicon layer may be a polysilicon layer (also called a Poly layer). In addition, the crystalline silicon layer may also be a single crystal silicon layer. The embodiments of the present application may not limit the specific type of the crystalline silicon layer. In the prior art, the metal layer, the polysilicon layer, and the isolation oxide layer are all etched in the scribe line 20 region, resulting in the scribe line 20 being at least 60000 Å (angstrom, 1 Å = 10−10 m) lower than the height of the chip region 30. Among them, the metal layer and the isolation oxide layer have a relatively large thickness, which is a major factor causing the large height difference of the scribe line 20. For example, the height difference between the scribe line 20 and the chip region 30 of the metal layer may be 40000 Å, and the height difference between the scribe line 20 and the chip region 30 of the isolation oxide layer may be 20000 Å. The embodiments of the present application eliminate the above height difference between the scribe line 20 and the chip region 30 through the first blocking portion and the second blocking portion, effectively preventing the acid solution from infiltrating from the scribe line 20 and spreading to the chip region 30.
[0050] Optionally, in the embodiments of the present application, the intersection where the scribe line 20 intersects on the crystalline silicon layer is the third intersection. The blocking portion 40 further includes a third blocking portion disposed at the third intersection. The third blocking portion is connected to the first blocking portion, and the third blocking portion is used to prevent the scribe line 20 from communicating at the third intersection of the crystalline silicon layer. In this way, the third blocking portion blocks the third intersection where the scribe line 20 intersects on the crystalline silicon layer, preventing the acid solution from infiltrating from the third intersection on the crystalline silicon layer and spreading along the third intersection to the chip region 30. Moreover, the first blocking portion, the second blocking portion, and the third blocking portion act together, making it difficult for the acid solution to infiltrate into the front wafer structure, further improving the avoidance effect of preventing the acid solution from infiltrating into the chip region 30.
[0051] In the embodiments of the present application, the first blocking portion can be provided only on the metal layer, or the second blocking portion can be provided only on the oxide layer. It is also possible to provide the first blocking portion on the metal layer and the second blocking portion on the oxide layer, and the blocking effect is achieved jointly by the first blocking portion and the second blocking portion. It is further possible to provide the first blocking portion on the metal layer, the second blocking portion on the oxide layer, and the third blocking portion on the crystalline silicon layer, and the blocking effect is achieved jointly by the first blocking portion, the second blocking portion, and the third blocking portion. In addition, it is also possible to provide the first blocking portion on the metal layer and the third blocking portion on the crystalline silicon layer, and the blocking effect is achieved jointly by the first blocking portion and the third blocking portion. The embodiments of the present application do not limit the above specific implementation manners.
[0052] Optionally, in the embodiments of the present application, the wafer structure further includes a blocking ring, and the blocking ring is connected to the outer periphery of the metal layer. In this way, the outer periphery of the metal layer is blocked by the blocking ring to prevent the acid solution from infiltrating from the metal layer and improve the acid drilling situation of the product. In the manufacturing process, the blocking ring can be formed by changing the yellow light exposure mode of the metal layer. Specifically, it can be set that the metal layer is not exposed at the edge of the wafer structure, that is, the metal layer at the edge is retained to form the blocking ring.
[0053] In the embodiments of the present application, optionally, as Figure 2 shown, the blocking portion 40 extends along the dicing channel 20, and the blocking portion 40 fills the dicing channel 20. In this way, the blocking portion 40 covers the entire area where the dicing channel 20 is located, further increasing the setting range and setting area of the blocking portion 40, eliminating the height difference between the dicing channel 20 and the chip area 30, and improving the blocking effect of the blocking portion 40 on the acid solution.
[0054] Optionally, in the embodiments of the present application, the blocking portion 40 is a cross-shaped blocking portion 40. In this way, the cross-shaped blocking portion 40 can achieve a good blocking effect on the areas extending in four directions at the intersection, and has good structural stability.
[0055] In the embodiments of the present application, optionally, the cross-shaped blocking portion 40 includes a first blocking edge 41 and a second blocking edge 42. The first blocking edge 41 and the second blocking edge 42 are located in the dicing channel 20, and the first blocking edge 41 and the second blocking edge 42 are perpendicularly connected. In this way, the area extending in the first direction X at the intersection is blocked by the first blocking edge 41, and the area extending in the second direction Y at the intersection is blocked by the second blocking edge 42.
[0056] Optionally, in the embodiments of the present application, the length of the first blocking edge 41 is any value between 300 and 800 micrometers, and the width of the first blocking edge 41 is any value between 60 and 80 micrometers. In this way, the first blocking edge 41 has an appropriate width to have a good blocking effect on the width position of the cutting channel 20. Moreover, the first blocking edge 41 has an appropriate length to avoid the first blocking edge 41 being too long and save materials.
[0057] Exemplarily, in the embodiments of the present application, the length of the first blocking edge 41 can be 300 micrometers, 400 micrometers, 600 micrometers, 800 micrometers, etc., and can be set according to the specific dimensions of the wafer structure and actual needs. The embodiments of the present application do not limit the specific length value of the first blocking edge 41. The width of the first blocking edge 41 can be 60 micrometers, 70 micrometers, 80 micrometers, etc., and can be set according to the specific dimensions of the wafer structure and actual needs. The embodiments of the present application do not limit the specific width value of the first blocking edge 41 either.
[0058] In the embodiments of the present application, optionally, the length of the second blocking edge 42 is any two values between 300 and 800 micrometers, and the width of the second blocking edge 42 is any two values between 60 and 80 micrometers. In this way, the second blocking edge 42 has an appropriate width to have a good blocking effect on the width position of the cutting channel 20. Moreover, the second blocking edge 42 has an appropriate length to avoid the second blocking edge 42 being too long and save materials. The dimensions of the second blocking edge 42 and the first blocking edge 41 can be the same or different, and can be set according to actual needs. The embodiments of the present application do not limit this.
[0059] Exemplarily, in the embodiments of the present application, the length of the second blocking edge 42 can be 300 micrometers, 400 micrometers, 600 micrometers, 800 micrometers, etc., and can be set according to the specific dimensions of the wafer structure and actual needs. The embodiments of the present application do not limit the specific length value of the second blocking edge 42. The width of the second blocking edge 42 can be 60 micrometers, 70 micrometers, 80 micrometers, etc., and can be set according to the specific dimensions of the wafer structure and actual needs. The embodiments of the present application do not limit the specific width value of the second blocking edge 42 either.
[0060] Optionally, in the embodiments of the present application, the cutting channel 20 includes a first cutting channel 21 and a second cutting channel 22; the first cutting channel 21 extends along the first direction X, the second cutting channel 22 extends along the second direction Y, and the intersection position of the first cutting channel 21 and the second cutting channel 22 is the intersection; wherein, the first direction X is perpendicular to the second direction Y. In this way, the intersection is formed by the first cutting channel 21 and the second cutting channel 22 intersecting vertically and horizontally, with a simple structure and convenient for process operations.
[0061] In an embodiment of the present application, optionally, the number of the first scribe lines 21 includes a plurality, and the plurality of first scribe lines 21 are arranged at intervals along the second direction Y; the number of the second scribe lines 22 includes a plurality, and the plurality of second scribe lines 22 are arranged at intervals along the first direction X. In this way, the base layer 10 of the wafer structure can be separated into a plurality of chip regions 30 by the plurality of first scribe lines 21 and the plurality of second scribe lines 22, and a plurality of chip structures can be provided, improving the performance of the wafer structure.
[0062] In summary, the wafer structure described in the embodiments of the present application can at least have the following advantages:
[0063] In an embodiment of the present application, the wafer structure includes a base layer, and at least one scribe line is provided on the base layer to separate chip regions from the base layer; a blocking portion is provided in the scribe line, and the blocking portion fills at least part of the scribe line. In this way, in the subsequent process of cleaning with acid solution, a protective film with relatively weak adhesion, such as a blue film, can be used to cover the base layer of the wafer structure. Since the blocking portion fills at least part of the scribe line and has a blocking effect on the scribe line, it can prevent the acid solution from penetrating into the chip region from the scribe line and spreading along the intersection, avoiding the problem of acid solution corroding the chip and improving the acid drilling situation of the product. Moreover, there is no need to use a protective film with relatively strong adhesion, such as a UV film, avoiding the problem of being easily adhered to the film-applying tool when tearing off the protective film and causing chip breakage, improving the yield of the product. There is also no need to tear off the protective film in a short time, reducing the process requirements and production costs.
[0064] In the description of this specification, the descriptions referring to terms such as "an embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.
[0065] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principle and spirit of the present invention, and the scope of the present invention is defined by the claims and their equivalents.
Claims
1. A wafer structure, characterized in that, The wafer structure includes a base layer, and at least one scribe line is disposed on the base layer to divide the base layer into chip areas; A blocking portion is disposed in the scribe line, and the blocking portion fills at least part of the scribe line; The number of the scribe lines is multiple, at least two of the scribe lines intersect, and the intersection position of the scribe lines is an intersection, and the blocking portion is disposed at the intersection; 2. The wafer structure according to claim 1, wherein The blocking portion is further disposed at the end of the scribe line to block the end of the scribe line; 3. The wafer structure according to claim 1, wherein, The base layer includes a metal layer, a crystalline silicon layer, and an oxide layer stacked in sequence; The intersection where the scribe line intersects on the metal layer is a first intersection, and the blocking portion includes a first blocking portion disposed at the first intersection, and the first blocking portion is used to prevent the scribe line from communicating at the first intersection on the metal layer; 4. The wafer structure according to claim 3, wherein, The intersection where the scribe line intersects on the oxide layer is a second intersection, and the blocking portion further includes a second blocking portion disposed at the second intersection, and the second blocking portion is spaced from the first blocking portion, and the second blocking portion is used to prevent the scribe line from communicating at the second intersection on the oxide layer; 5. The wafer structure according to any one of claims 3-4, characterized in that, The intersection where the scribe line intersects on the crystalline silicon layer is a third intersection, and the blocking portion further includes a third blocking portion disposed at the third intersection, and the third blocking portion is connected to the first blocking portion, and the third blocking portion is used to prevent the scribe line from communicating at the third intersection on the crystalline silicon layer; 6. The wafer structure according to claim 3, wherein The wafer structure further includes a blocking ring, and the blocking ring is connected to the outer periphery of the metal layer; 7. The wafer structure according to claim 1, wherein The blocking portion extends along the scribe line, and the blocking portion fills the scribe line; 8. The wafer structure according to claim 1, wherein The blocking portion is a cross-shaped blocking portion; 9. The wafer structure according to claim 8, wherein The cross-shaped blocking portion includes a first blocking edge and a second blocking edge, the first blocking edge and the second blocking edge are located in the scribe line, and the first blocking edge and the second blocking edge are perpendicularly connected; 10. The wafer structure according to claim 9, wherein The length of the first blocking edge is any value between 300 and 800 microns, and the width of the first blocking edge is any value between 60 and 80 microns; 11. The wafer structure according to claim 9, wherein, The length of the second blocking edge is any value between 300 and 800 microns, and the width of the second blocking edge is any value between 60 and 80 microns; 12. The wafer structure according to claim 1, characterized in that, The scribe line includes a first scribe line and a second scribe line; The first scribe line extends along a first direction, the second scribe line extends along a second direction, and the intersection position of the first scribe line and the second scribe line is the intersection; Wherein, the first direction is perpendicular to the second direction; 13. The wafer structure according to claim 12, wherein, The number of the first scribe lines includes multiple, and the multiple first scribe lines are spaced along the second direction; The number of the second scribe lines includes multiple, and the multiple second scribe lines are spaced along the first direction.