Layout structure capable of improving signal impedance change of DDR (Double Data Rate) chip
By improving the hole drilling method of the DDR pad group, the fan-out holes are arranged in a misaligned manner to increase the spacing, the problem of impedance changes in DDR chip processing is solved, and the processing yield and signal quality are improved.
Patent Information
- Application Number
- CN202421892695.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-06
- Publication Date
- 2025-07-11
- Estimated Expiration
- 2034-08-06
AI Technical Summary
During the processing of the DDR chip, due to the small spacing between the two holes and the 0.1mm line width trace required, the impedance changes, which affects the processing yield and signal quality.
By improving the hole punching method of the DDR pad group, multiple arrays of DDR pad groups are set up, and fan-out holes are arranged in the outer and inner sides, expanding the holes and disk spacing, so that the inner layer traces maintain a 40Ω impedance signal connection, and reducing line width changes.
It effectively improves the processing difficulty of DDR chips, improves the yield rate, and maintains the stability and integrity of signal quality.
Smart Images
Figure CN223093947U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of circuit boards, and more specifically, to a layout structure that can improve the signal impedance change of DDR chips. Background Art
[0002] A printed circuit board (PCB) is also called a printed wiring board, which is an important part of the physical support and signal transmission of electronic products. As an important part of DDR electronic products, DDR (Double Data Rate) chips are widely used in PCB boards. DDR (Double Data Rate SDRAM) is called double data rate synchronous dynamic random access memory. In current PCB boards, the routing speed is getting higher and higher. DDR has been widely applied to PCB design. In order to meet the speed requirements, DDR traces usually need to be controlled with a 40Ω impedance.
[0003] In conventional designs, DDR chips (such as MT53E256 series chips) are widely used in automotive-grade PCB boards. When the traces are connected to the DDR chips, since the pitch between the device pads of the DDR chips is only 0.65mm (vertical pad-to-pad) and 0.8mm (horizontal pad-to-pad), the normal practice is to drill holes between the pads of the DDR chips to connect to the inner-layer traces. After drilling, the pitch between the via pads on the inner layer can only pass a trace width of 0.1mm. Therefore, the trace width of DDR will change at this point, and impedance changes will occur when the trace width changes. In this way, the trace width of DDR cannot be completely controlled at 40Ω, resulting in impedance changes, which has a great impact on the DDR traces.
[0004] In the traditional processing of DDR chips, because the pitch between the two holes is very small, the pitch between the centers of the two holes is only 0.8mm, and a 0.1mm trace width needs to pass between the two holes, it is difficult to process. The high processing difficulty will lead to a low processing yield of DDR chips. Summary of the Utility Model
[0005] In order to overcome the problem that in the existing DDR chips, when drilling holes between the pads to connect to the inner-layer traces, after drilling, the pitch between the two holes is small, and the pitch between the via pads on the inner layer can only pass a trace width of 0.1mm. Therefore, the trace width of DDR will change between the via pads, and impedance changes will occur when the trace width changes. Moreover, it is difficult to process a 0.1mm trace width, which will lead to a low processing yield of DDR chips, the utility model provides a layout structure that can improve the signal impedance change of DDR chips.
[0006] The technical solution of the present utility model is described as follows:
[0007] A layout structure that can improve the signal impedance change of DDR chips, including a plurality of DDR pad groups arranged in an array on the circuit board body. Each DDR pad group includes a plurality of surface-mounted pads arranged in an array. The first fan-out holes of the outer surface-mounted pads are located outside the DDR pad group, and the second fan-out holes of the inner surface-mounted pads are located inside the DDR pad group. Moreover, the second fan-out holes of the inner surface-mounted pads are arranged in a staggered manner, such that the center distance between adjacent second fan-out holes is not less than 1.3 mm.
[0008] In the present utility model according to the above solution, the second fan-out holes of adjacent surface-mounted pads in the horizontal row are staggered left and right, and the second fan-out holes of adjacent surface-mounted pads in the vertical row are staggered up and down.
[0009] In the present utility model according to the above solution, the outer surface-mounted pads are connected to the first fan-out holes through the first surface-mounted traces.
[0010] In the present utility model according to the above solution, the inner surface-mounted pads are connected to the second fan-out holes through the second surface-mounted traces.
[0011] In the present utility model according to the above solution, the diameter of the second fan-out holes is 0.2 mm.
[0012] In the present utility model according to the above solution, the distance between the inner layer traces of the circuit board body and the hole walls of the second fan-out holes is not less than 0.25 mm.
[0013] In the present utility model according to the above solution, the distance between the inner layer traces and the second pad discs of the second fan-out holes is not less than 0.1 mm.
[0014] In the present utility model according to the above solution, the impedance of the inner layer traces is 40 Ω.
[0015] In the present utility model according to the above solution, the surface-mounted pads corresponding in position in two adjacent DDR pad groups share one first fan-out hole.
[0016] In the present utility model according to the above solution, the number of surface-mounted pads in the DDR pad group is 50.
[0017] The beneficial effects of the present utility model according to the above scheme are as follows: for a DDR pad group of the present utility model, the first fan-out holes of the surface-mounted pads on the outer side are arranged outside the DDR pad group, and the second fan-out holes of the surface-mounted pads inside are arranged in a staggered manner. By improving the drilling method of the DDR pad group of the DDR chip, the distance between the pad disks of the adjacent first fan-out holes and the second fan-out holes of the DDR chip group is increased. After the distance becomes larger, the inner-layer traces between the two holes can maintain a 40Ω impedance signal connection to the DDR chip, and the DDR trace signal quality is optimal.
[0018] After changing the drilling method, without changing the line width of 0.1mm, there is no need to make closely spaced traces between the two holes, which can effectively improve the processing difficulty of the DDR chip. By reducing the processing difficulty, the processing yield of the DDR chip can be increased. Description of the Drawings
[0019] Figure 1 It is a schematic diagram of the layout structure of an existing DDR chip;
[0020] Figure 2 Schematic diagram of the structure of the present utility model;
[0021] Figure 3 is Figure 2 An enlarged schematic diagram of part A in
[0022] In the figure, the reference numerals of each part are as follows:
[0023] 100, circuit board body; 10, DDR pad group; 11, surface-mounted pad; 12, first fan-out hole; 13, second fan-out hole; 14, first surface-mounted trace; 15, second surface-mounted trace. Detailed Embodiment
[0024] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments.
[0025] It should be noted that the terms "including" and "having" and any variations thereof in the description and claims of the present utility model are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally further include steps or units not listed, or may optionally further include other steps or units inherent to these processes, methods, products, or devices. Terms such as "arranged" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and can be the communication inside two components or the interaction relationship between two components, unless otherwise clearly defined. The orientations or positions indicated by terms such as "upper", "lower", "left", "right", "front", "rear", "bottom", etc. are based on the orientations or positions shown in the drawings, and are only for convenience of description and should not be construed as a limitation to the technical solution of the present application.
[0026] In conventional designs, DDR chips (such as MT53E256 series chips) are widely used in automotive-grade PCB boards. When the traces are connected to the DDR chips, since the pitch between the device pads of the DDR chips is only 0.65 mm (vertical row pad to pad) and 0.8 mm (horizontal row pad to pad), as Figure 1 shown, the normal conventional practice is to drill holes between the pads of the DDR chips to connect to the inner-layer traces. The holes drilled between the device pads are very dense, and the pitch between the hole pads on the inner layer can only accommodate a trace width of 0.1 mm. Therefore, the trace width of the DDR will change here, and impedance changes will occur when the trace width changes. In this way, the trace width of the DDR cannot all be controlled to be 40Ω impedance traces, resulting in impedance changes, which have a great impact on the traces of the DDR.
[0027] In the processing of traditional DDR chips, since the pitch between the two holes is very small, the pitch between the centers of the two holes is only 0.8 mm, and a 0.1 mm trace width needs to pass between the two holes. There are difficulties in processing, and the high processing difficulty will lead to a low yield rate of the DDR chip processing.
[0028] In addition, taking the DDR chip (such as MT53E256 series chips) as an example, there are 4 groups of data lines and 2 groups of address lines. In the design, the two groups of address lines need to correspond according to the T-point trace method. The pitch between the holes is not widened, and the impedance trace width still needs to change after entering the BGA. Also because of the reason of changing the signal, in order to stagger the pitch between the signal lines, usually three inner layers are used to correspond to the traces of the DDR in the design. Using too many inner layers can be optimized.
[0029] As Figures 2 - 3As shown in the figure, a layout structure that can improve the signal impedance variation of DDR chips. The first fan-out holes 12 of the outer surface-mount pads 11 are arranged outside the DDR pad group 10, and the second fan-out holes 13 of the inner surface-mount pads 11 are arranged in a staggered manner. By improving the drilling method of the DDR pad group 10 of the DDR chip, the distance between the pad disks of the first fan-out holes 12 and the second fan-out holes 13 of the surface-mount pads 11 of the DDR chip group is increased. After the distance becomes larger, the inner-layer trace between the two holes can maintain a 40Ω impedance signal connection to the DDR chip. Without changing the 0.1mm line width, the impedance variation of the DDR signal will not be introduced, and thus the integrity of the DDR signal can be ensured, making the DDR trace signal quality optimal.
[0030] After changing the drilling method, without changing the 0.1mm line width, the trace with a close pitch does not need to be made between the two holes, which can effectively improve the processing difficulty of the DDR chip. By reducing the processing difficulty, the processing yield of the DDR chip can be increased.
[0031] Specifically, it includes a plurality of DDR pad groups 10 arranged in an array on the circuit board body 100. Each DDR pad group 10 includes a plurality of surface-mount pads 11 arranged in an array. The first fan-out holes 12 of the outer surface-mount pads 11 are located outside the DDR pad group 10, and the second fan-out holes 13 of the inner surface-mount pads 11 are located inside the DDR pad group 10, and the second fan-out holes 13 of the inner surface-mount pads 11 are arranged in a staggered manner, such that the center distance between adjacent second fan-out holes 13 is not less than 1.3mm.
[0032] The trace led out by the outer surface-mount pad 11 is connected through the first fan-out hole 12, and the trace is directly led out through the first fan-out hole 12 for signal connection, so that the outer surface-mount pad 11 can not use the inner-layer trace. The surface-mount pads 11 between adjacent DDR pad groups 10 can be directly connected by the T-point between adjacent DDR pad groups 10. One is that the number of holes of the first fan-out hole 12 can be reduced, and the other is that the wiring layer can be saved. This enables the DDR trace to be connected with 2 inner layers, while the conventional design requires at least 3 inner layers for wiring, thus reducing the use of inner layers.
[0033] In one embodiment, the second fan-out holes 13 of the internal surface mount pads 11 are arranged in a staggered manner: the second fan-out holes 13 of the adjacent surface mount pads 11 in a horizontal row are staggered left and right, and the second fan-out holes 13 of the adjacent surface mount pads 11 in a vertical row are staggered up and down. This arrangement makes it possible for the second fan-out holes 13 of the surface mount pads 11 arranged left and right to be staggered with each other, and the second fan-out holes 13 of the surface mount pads 11 arranged up and down to be staggered with each other. In this way, the staggered punching at the densest part in the middle of the DDR pad group 10 is staggered as a whole, which increases the spacing between the second fan-out holes 13, ensures that the spacing between adjacent second fan-out holes 13 is greater than 1.3 mm, and ensures that there is enough spacing between the second fan-out holes 13 when routing internally, without changing the line width of the internal routing.
[0034] It should be noted that in the actual drilling process, the second fan-out holes 13 of some internal surface mount pads 11 can be set outside the DDR pad group 10, and the two internal surface mount pads 11 can use the same second fan-out hole 13 as needed.
[0035] In one embodiment, the outer surface mount pad 11 is connected to the first fan-out hole 12 via a first surface mount trace 14. The inner surface mount pad 11 is connected to the second fan-out hole 13 via a second surface mount trace 15 to optimize signal transmission quality.
[0036] The diameter of the second fan-out hole 13 is 0.2 mm, and the purpose of setting it is to ensure that the spacing between the hole walls of adjacent second fan-out holes 13 is greater than 1.1 mm, so that the inner layer routing can maintain a 40Ω impedance signal connection to the DDR chip.
[0037] Considering the ease of factory processing, the spacing between the inner layer wiring of the circuit board body 100 and the hole wall of the second fan-out hole 13 is not less than 0.25 mm, and the spacing between the inner layer wiring and the second hole plate of the second fan-out hole 13 is not less than 0.1 mm. This ensures smooth processing and further improves processing reliability and yield.
[0038] In one embodiment, the surface mount pads 11 corresponding to each other in two adjacent DDR pad groups 10 share a first fan-out hole, thereby reducing the number of first fan-out holes 12, simplifying the wiring layout, and making the design of the entire circuit board more compact and efficient.
[0039] The number of surface mount pads 11 in the DDR pad group 10 is 50. The number of 50 surface mount pads 11 can meet the pin connection requirements of the DDR chip.
[0040] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the claims attached to the utility model.
[0041] The above has given an exemplary description of the patent of the present utility model in conjunction with the accompanying drawings. Obviously, the implementation of the patent of the present utility model is not limited by the above-mentioned manner. Any improvements made by adopting the method concept and technical solution of the patent of the present utility model, or directly applying the concept and technical solution of the patent of the present utility model to other occasions without improvement, are within the protection scope of the present utility model.
Claims
1. A layout structure capable of improving the signal impedance variation of a DDR chip, characterized in that It includes a plurality of DDR pad groups arranged in an array on the circuit board body. Each DDR pad group includes a plurality of surface-mount pads arranged in an array. The first fan-out holes of the outer surface-mount pads are located outside the DDR pad group, and the second fan-out holes of the inner surface-mount pads are located inside the DDR pad group. Moreover, the second fan-out holes of the inner surface-mount pads are arranged in a staggered manner, so that the center distance between adjacent second fan-out holes is not less than 1.3 mm.
2. The layout structure according to claim 1 that can improve the signal impedance variation of the DDR chip, characterized in that, The second fan-out holes of adjacent horizontally arranged surface-mount pads are staggered left and right, and the second fan-out holes of adjacent vertically arranged surface-mount pads are staggered up and down.
3. A layout structure capable of improving the signal impedance variation of a DDR chip according to claim 1 or 2, characterized in that The outer surface-mount pads are connected to the first fan-out holes through first surface-mount traces.
4. A layout structure capable of improving the signal impedance change of a DDR chip according to claim 3, characterized in that, The inner surface-mount pads are connected to the second fan-out holes through second surface-mount traces.
5. A layout structure capable of improving the signal impedance variation of a DDR chip according to claim 1, 2 or 4, characterized in that The diameter of the second fan-out holes is 0.2 mm.
6. The layout structure for improving the signal impedance variation of a DDR chip according to claim 5, characterized in that The distance between the inner layer traces of the circuit board body and the hole walls of the second fan-out holes is not less than 0.25 mm.
7. A layout structure capable of improving the signal impedance variation of a DDR chip according to claim 6, characterized in that The distance between the inner layer traces and the second pad discs of the second fan-out holes is not less than 0.1 mm.
8. A layout structure capable of improving the signal impedance variation of a DDR chip according to claim 6 or 7, characterized in that The impedance of the inner layer traces is 40 Ω.
9. A layout structure capable of improving the signal impedance variation of a DDR chip according to claim 1, characterized in that The surface-mount pads corresponding in position in two adjacent DDR pad groups share one first fan-out hole.
10. A layout structure capable of improving the signal impedance variation of a DDR chip according to claim 1 or 9, characterized in that, The number of surface-mount pads in the DDR pad group is 50.