High-power low-density silicon carbide MOSFET device

Abstract

The utility model discloses a high-power low-density silicon carbide MOSFET device, which relates to the technical field of semiconductor power devices and comprises a drain electrode, a silicon carbide substrate arranged above the drain electrode, a silicon carbide epitaxial layer arranged above the silicon carbide substrate and a conductive base region arranged on the silicon carbide epitaxial layer. A conductive contact layer and a P well region are arranged on the two sides of the upper end of the conductive base region respectively, a conductive shielding layer and an N-drift region are arranged above the P well region and the conductive contact layer respectively, conductor regions are arranged above the N-drift region and the conductive shielding layer respectively, and conductive metal layers are arranged above the two conductor regions respectively. According to the high-power and low-density silicon carbide MOSFET device, better radiation tolerance and electrical performance can be provided for the silicon carbide MOSFET device, the anti-radiation intensity of the silicon carbide MOSFET device is improved, the conduction efficiency, the safety and the reliability of the silicon carbide MOSFET device are improved, and the high-power and low-density characteristics are achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor power devices, and particularly relates to a silicon carbide MOSFET device with high power and low density. Background Technique

[0002] The silicon carbide MOSFET device is a silicon carbide power semiconductor device. Using the new semiconductor material silicon carbide and relying on various electrical properties of the material itself, it has extremely promising prospects in the application fields of high-voltage, high-temperature and high-power devices. The specific manifestations include high breakdown voltage, wide bandgap, high temperature resistance, high electron mobility, etc. Therefore, as one of the most advanced power devices, with the rapid development of science and technology, the application of silicon carbide MOSFET power devices is becoming more and more extensive, and corresponding research is carried out and has great scientific research significance.

[0003] At present, the transmission efficiency and reliability of silicon carbide MOSFET devices during use are crucial. Usually, reducing the cell size is an effective means to improve the efficiency of silicon carbide MOSFETs. However, due to the registration deviation between each lithography layer, the width of the JFET region at a medium depth is relatively narrow, which further hinders the expansion of electrons in the JFET region, increases the on-resistance of the JFET region, and at the same time, when the device is turned on, the generated electric field is prone to electric field breakdown, affecting the conduction efficiency and safety reliability of the silicon carbide MOSFET device. At the same time, when the device is conducting, it may generate high radiation, which can cause the threshold voltage degradation and changes in other electrical parameters of the silicon carbide MOSFET device. These changes are mainly due to the increase in oxide trap charges and changes in interface states caused by radiation, which directly affect the switching behavior and efficiency of the device.

[0004] Therefore, a new type of silicon carbide MOSFET device with high power and low density is proposed. Summary of the Invention

[0005] The purpose of the utility model is to provide a silicon carbide MOSFET device with high power and low density to solve the problems raised in the above background technique:

[0006] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0007] A high-power and low-density silicon carbide MOSFET device includes a drain, above which a silicon carbide substrate is provided, above which a silicon carbide epitaxial layer is provided, on which a conductive base region is provided, on both upper ends of the conductive base region, a conductive contact layer and a P-well region are respectively provided, above the P-well region and the conductive contact layer, a conductive shielding layer and an N-drift region are respectively provided, above the N-drift region and the conductive shielding layer, a conductive body region is provided, above both of the conductive body regions, a conductive metal layer is provided, above both of the conductive metal layers, a conductive source region is provided, between the two conductive source regions, a dielectric layer is commonly provided, in the dielectric layer, a gate oxide layer and a radiation-resistant layer are provided, between the dielectric layer and the conductive base region, a conductive channel region is provided, at both ends of the conductive channel region, a triangular groove region is provided, and on the two conductive source regions and the dielectric layer, a metal source electrode is commonly provided.

[0008] Preferably, the gate oxide layer and the radiation-resistant layer are in contact with each other;

[0009] The radiation-resistant layer is made of hafnium dioxide,

[0010] By adopting the above technical solution, the radiation-resistant layer is made of hafnium dioxide. As a gate dielectric, hafnium dioxide will provide better radiation tolerance and electrical performance to the silicon carbide MOSFET device, increasing the radiation resistance of the silicon carbide MOSFET device.

[0011] Preferably, the metal source electrode is located above the conductive source region and the dielectric layer;

[0012] The interfaces between the metal source electrode and the conductive source region and the dielectric layer are both ohmic contacts;

[0013] The interface between the drain and the silicon carbide substrate is an ohmic contact,

[0014] By adopting the above technical solution, by providing a triangular groove region and a triangular extension region between the radiation-resistant layer and the conductive base region, when the silicon carbide MOSFET device is in use, the silicon carbide MOSFET device can form longitudinal multiple conductive channels, and when an electric field enters the silicon carbide MOSFET device, double buffering is achieved through the triangular groove region and the triangular extension region.

[0015] Preferably, a first buffer trench and a second buffer trench are provided in the conductive shielding layer;

[0016] The first buffer trench and the second buffer trench are connected and communicate with each other, and after the first buffer trench and the second buffer trench are combined, a special-shaped buffer region is formed;

[0017] The doping ions of the first buffer trench and the second buffer trench are both one or more of phosphorus ions, arsenic ions or antimony ions,

[0018] By adopting the above technical solutions, the electric field intensity borne by the gate dielectric of the silicon carbide MOSFET device can be effectively reduced, so that the device can avoid the phenomenon of gate oxide breakdown.

[0019] Preferably, the surface doping concentration of the P-well region is 2.5×1037 cm-3 -3 ;

[0020] The doping concentration of the bottom of the P-well region near the boundary of the N-drift region is 1×1036 cm-3 -3 ,

[0021] By adopting the above technical solutions, through the fully self-aligned anti-radiation layer, the conductive base region, the conductive source region, the conductive body region and the conductive channel region can effectively improve the anti-radiation performance of the silicon carbide MOSFET device and reduce the density of the silicon carbide MOSFET device.

[0022] Preferably, the doping concentrations of the N-drift region and the conductive contact layer are both 5×1028 cm-3 -3 ;

[0023] The doping concentration of the conductive contact layer is 7×1027 cm-3 -3 ;

[0024] The doping concentration of the conductive source region is 6×1028 cm-3 -3 ;

[0025] The thickness of the N-drift region is 40 - 70 μm.

[0026] By adopting the above technical solutions, the first buffer trench and the second buffer trench are connected, so that when the silicon carbide MOSFET device needs high-energy well region ion implantation, the electric field can achieve buffer epitaxy through the first buffer trench and the second buffer trench.

[0027] Preferably, at one end of each of the two triangular groove regions far from the conductive channel region, a triangular extension region is provided, and the two triangular extension regions are respectively connected to the P-well region and the conductive contact layer.

[0028] By adopting the above technical solutions, the shaped upper trench and the shaped lower trench are distributed in an interleaved and connected manner, so that the buffer epitaxy time of the silicon carbide MOSFET device is further prolonged, and the electric field intensity can be reduced when the electric field is transmitted here.

[0029] Preferably, the doping concentration of the silicon carbide substrate is 5×1028 cm-3 -3 ;

[0030] The metal source is made of N-type polysilicon material, with a doping concentration of 1×1020 cm-3, -3 and the doping ions are phosphorus ions and carbon ions;

[0031] The distance between the two triangular groove areas is not greater than 5.0 μm.

[0032] By adopting the above technical solution, the on-resistance of the JFET region is reduced, and the on-state efficiency and safety reliability of the silicon carbide MOSFET device are improved.

[0033] Preferably, two special-shaped upper grooves and special-shaped lower grooves are arranged between the silicon carbide epitaxial layer and the conductive base region;

[0034] The two special-shaped upper grooves and the two special-shaped lower grooves are alternately distributed;

[0035] The depth of the special-shaped upper groove is greater than that of the special-shaped lower groove, and the depth of the special-shaped upper groove is greater than 3.0 μm, and the depth-to-width ratio is greater than 2:1.

[0036] By adopting the above technical solution, the on-state efficiency and safety reliability of the silicon carbide MOSFET device are improved, and the ability of the device to conduct current is enhanced.

[0037] Preferably, the P-well region, the conductive contact layer, the N-drift region, and the conductive base region are all made of P-type silicon carbide material, and the doping ions are one or more of boron ions, copper ions, carbon ions, or aluminum ions;

[0038] The silicon carbide substrate, the N-drift region, and the conductive source region are all made of N-type silicon carbide material;

[0039] The doping ions of the N-type silicon carbide material are nitrogen ions, carbon ions, or phosphorus ions;

[0040] The thickness of the P-well region is not greater than 2.5 μm, and after the power transmission ends, the special-shaped upper grooves and the special-shaped lower grooves are completely filled.

[0041] By adopting the above technical solution, the special-shaped upper grooves and the special-shaped lower grooves are alternately and communicatively distributed, so that the buffer epitaxial time of the silicon carbide MOSFET device is further extended, and the electric field strength can be reduced when the electric field is transmitted here, thereby reducing the on-resistance of the JFET region.

[0042] Compared with the prior art, the beneficial effects of the present utility model are:

[0043] 1. In the present utility model, by providing a radiation-resistant layer between the dielectric layer and the gate oxide layer, when the silicon carbide MOSFET device is in use, hafnium dioxide, as the gate dielectric, can provide better radiation tolerance and electrical performance for the silicon carbide MOSFET device, increasing the radiation resistance of the silicon carbide MOSFET device. At the same time, the triangular groove region and the triangular extension region enable the silicon carbide MOSFET device to form a longitudinal multiple conductive channel, achieving double buffering, which can effectively reduce the electric field intensity borne by the gate dielectric of the silicon carbide MOSFET device, preventing the device from experiencing gate oxide breakdown. Moreover, through the fully self-aligned radiation-resistant layer, the radiation resistance of the silicon carbide MOSFET device can be effectively increased, and the density of the silicon carbide MOSFET device can be reduced, ensuring the switching behavior and efficiency of the silicon carbide MOSFET device;

[0044] 2. In the present utility model, by providing a first buffer trench and a second buffer trench in the conductive shielding layer, and the first buffer trench and the second buffer trench are connected, when the silicon carbide MOSFET device requires high-energy well region ion implantation, the electric field can be buffered and epitaxied through the first buffer trench and the second buffer trench. At the same time, the shaped upper trench and the shaped lower trench are distributed in an interleaved and connected manner, further lengthening the buffer epitaxy time of the silicon carbide MOSFET device, reducing the electric field intensity when the electric field is transmitted here, thereby reducing the on-resistance of the JFET region, improving the on-efficiency and safety reliability of the silicon carbide MOSFET device, and enhancing the device's ability to conduct current. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 FIG. is a schematic diagram of the overall structure of a high-power and low-density silicon carbide MOSFET device according to the present utility model.

[0046] In the figure: 1: drain; 2: silicon carbide substrate; 3: silicon carbide epitaxial layer; 4: conductive base region; 5: conductive contact layer; 6: N - drift region; 7: conductor region; 8: conductive metal layer; 9: conductive source region; 10: metal source electrode; 11: dielectric layer; 12: gate oxide layer; 14: conductive channel region; 16: conductive shielding layer; 17: P well region; 161: first buffer trench; 162: second buffer trench; 31: shaped upper trench; 32: shaped lower trench. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0047] Embodiment 1

[0048] Please refer to Figure 1, A high-power and low-density silicon carbide MOSFET device, including a drain 1, a silicon carbide substrate 2 is disposed above the drain 1, a silicon carbide epitaxial layer 3 is disposed above the silicon carbide substrate 2, a conductive base region 4 is disposed on the silicon carbide epitaxial layer 3, a conductive contact layer 5 and a P-well region 17 are respectively disposed on both sides of the upper end of the conductive base region 4, a conductive shielding layer 16 and an N-drift region 6 are respectively disposed above the P-well region 17 and the conductive contact layer 5, a conductive body region 7 is disposed above both the N-drift region 6 and the conductive shielding layer 16, a conductive metal layer 8 is disposed above both of the two conductive body regions 7, a conductive source region 9 is disposed above both of the two conductive metal layers 8, a dielectric layer 11 is commonly disposed between the two conductive source regions 9, a gate oxide layer 12 and an anti-radiation layer are disposed in the dielectric layer 11, a conductive channel region 14 is disposed between the dielectric layer 11 and the conductive base region 4, triangular groove regions are disposed at both ends of the conductive channel region 14, and a metal source electrode 10 is commonly disposed on the two conductive source regions 9 and the dielectric layer 11.

[0049] The gate oxide layer 12 is in contact with the anti-radiation layer;

[0050] The anti-radiation layer is made of hafnium dioxide.

[0051] The metal source electrode 10 is located above the conductive source region 9 and the dielectric layer 11;

[0052] The interfaces between the metal source electrode 10 and the conductive source region 9 and the dielectric layer 11 are both ohmic contacts;

[0053] The interface between the drain 1 and the silicon carbide substrate 2 is an ohmic contact.

[0054] A first buffer trench 161 and a second buffer trench 162 are disposed in the conductive shielding layer 16;

[0055] The first buffer trench 161 and the second buffer trench 162 are connected and form a special-shaped buffer region after combination;

[0056] The doping ions of the first buffer trench 161 and the second buffer trench 162 are both one or more of phosphorus ions, arsenic ions or antimony ions.

[0057] The surface doping concentration of the P-well region 17 is 2.5×1037 cm-3; -3 ;

[0058] The doping concentration of the bottom of the P-well region 17 near the boundary of the N-drift region 6 is 1×1036 cm-3; -3 .

[0059] The doping concentrations of the N-drift region 6 and the conductive contact layer 5 are both 5×1028 cm-3; -3 ;

[0060] The doping concentration of the conductive contact layer 5 is 7×10²⁷ cm -3 ;

[0061] The doping concentration of the source region 9 is 6×10²⁸ cm -3 ;

[0062] The thickness of the N-drift region 6 is 40 - 70 μm.

[0063] At one end of the two triangular groove regions away from the conductive channel region 14, triangular extension regions are provided, and the two triangular extension regions are respectively connected to the P-well region 17 and the conductive contact layer 5.

[0064] The using steps of the present utility model: In the present utility model, when the silicon carbide MOSFET device is used, the anti-radiation layer is made of hafnium dioxide. As the gate dielectric, hafnium dioxide will provide better radiation tolerance and electrical performance to the silicon carbide MOSFET device, increasing the anti-radiation intensity of the silicon carbide MOSFET device. At the same time, by setting the triangular groove region and the triangular extension region between the anti-radiation layer and the conductive base region 4, when the silicon carbide MOSFET device is used, the triangular groove region and the triangular extension region enable the silicon carbide MOSFET device to form a longitudinal multiple conductive channel. When the electric field enters the silicon carbide MOSFET device, double buffering is achieved through the triangular groove region and the triangular extension region, which can effectively reduce the electric field intensity borne by the gate dielectric of the silicon carbide MOSFET device, preventing the device from experiencing gate oxide breakdown. Moreover, through the fully self-aligned anti-radiation layer, the conductive base region 4, the source region 9, the conductor region 7, and the conductive channel region 14 can effectively improve the anti-radiation performance of the silicon carbide MOSFET device and reduce the density of the silicon carbide MOSFET device, ensuring the switching behavior and efficiency of the silicon carbide MOSFET device.

[0065] Embodiment 2

[0066] Please refer to Figure 1, A high-power and low-density silicon carbide MOSFET device, including a drain 1, a silicon carbide substrate 2 is arranged above the drain 1, a silicon carbide epitaxial layer 3 is arranged above the silicon carbide substrate 2, a conductive base region 4 is arranged on the silicon carbide epitaxial layer 3, a conductive contact layer 5 and a P-well region 17 are respectively arranged on both sides of the upper end of the conductive base region 4, a conductive shielding layer 16 and an N-drift region 6 are respectively arranged above the P-well region 17 and the conductive contact layer 5, a conductive body region 7 is arranged above both the N-drift region 6 and the conductive shielding layer 16, a conductive metal layer 8 is arranged above both of the two conductive body regions 7, a conductive source region 9 is arranged above both of the two conductive metal layers 8, a dielectric layer 11 is jointly arranged between the two conductive source regions 9, a gate oxide layer 12 and an anti-radiation layer are arranged in the dielectric layer 11, a conductive channel region 14 is arranged between the dielectric layer 11 and the conductive base region 4, triangular groove regions are arranged at both ends of the conductive channel region 14, and a metal source electrode 10 is jointly arranged on the two conductive source regions 9 and the dielectric layer 11.

[0067] The doping concentration of the silicon carbide substrate 2 is 5×10²⁸ cm -3 ;

[0068] The metal source electrode 10 is made of N-type polysilicon material, and the doping concentration is 1×10²⁰ cm -3 , and the doping ions are phosphorus ions and carbon ions;

[0069] The distance between the two triangular groove regions is not greater than 5.0 μm.

[0070] Two special-shaped upper grooves 31 and special-shaped lower grooves 32 are arranged between the silicon carbide epitaxial layer 3 and the conductive base region 4;

[0071] The two special-shaped upper grooves 31 and the two special-shaped lower grooves 32 are staggered;

[0072] The depth of the special-shaped upper groove 31 is greater than the depth of the special-shaped lower groove 32, and the depth of the special-shaped upper groove 31 is greater than 3.0 μm, and the depth-to-width ratio is greater than 2:1.

[0073] The P-well region 17, the conductive contact layer 5, the N-drift region 6 and the conductive base region 4 are all made of P-type silicon carbide material, and the doping ions are one or more of boron ions, copper ions, carbon ions or aluminum ions;

[0074] The silicon carbide substrate 2, the N-drift region 6 and the conductive source region 9 are all made of N-type silicon carbide material;

[0075] The doping ions of the N-type silicon carbide material are nitrogen ions, carbon ions or phosphorus ions;

[0076] The thickness of the P-well region 17 is not greater than 2.5 μm, and the special-shaped upper grooves 31 and the special-shaped lower grooves 32 are completely filled after the power transmission ends.

[0077] Usage steps of the present utility model: In the present utility model, when the silicon carbide MOSFET device is in use, the first buffer trench 161 and the second buffer trench 162 are connected in communication. When high-energy well region ion implantation is required for the silicon carbide MOSFET device, the electric field can achieve buffer epitaxy through the first buffer trench 161 and the second buffer trench 162. At the same time, the shaped upper trench 31 and the shaped lower trench 32 are provided, and the shaped upper trench 31 and the shaped lower trench 32 are distributed in an interleaved and connected manner, so that the buffer epitaxy time of the silicon carbide MOSFET device is further prolonged, and the electric field strength can be reduced when the electric field is transmitted here, thereby reducing the on-resistance of the JFET region, improving the on-efficiency and safety reliability of the silicon carbide MOSFET device, and enhancing the ability of the device to conduct current.

[0078] The above shows and describes the basic principles, main features and advantages of the present utility model. Those skilled in the art should understand that the present utility model is not limited by the above embodiments. The above embodiments and the descriptions in the specification are only preferred examples of the present utility model and are not used to limit the present utility model. Without departing from the spirit and scope of the present utility model, the present utility model will have various changes and improvements, and these changes and improvements all fall within the scope of the present utility model claimed. The scope of protection claimed by the present utility model is defined by the appended claims and their equivalents.

Claims

1. A high-power and low-density silicon carbide MOSFET device, comprising a drain (1), characterized in that: Above the drain (1), a silicon carbide substrate (2) is provided. Above the silicon carbide substrate (2), a silicon carbide epitaxial layer (3) is provided. On the silicon carbide epitaxial layer (3), a conductive base region (4) is provided. On both sides of the upper end of the conductive base region (4), a conductive contact layer (5) and a P-well region (17) are respectively provided. Above the P-well region (17) and the conductive contact layer (5), a conductive shielding layer (16) and an N-drift region (6) are respectively provided. Above the N-drift region (6) and the conductive shielding layer (16), a conductive body region (7) is provided. Above both of the conductive body regions (7), a conductive metal layer (8) is provided. Above both of the conductive metal layers (8), a conductive source region (9) is provided. Between the two conductive source regions (9), a dielectric layer (11) is jointly provided. Inside the dielectric layer (11), a gate oxide layer (12) and an anti-radiation layer are provided. Between the dielectric layer (11) and the conductive base region (4), a conductive channel region (14) is provided. At both ends of the conductive channel region (14), triangular groove regions are provided. Above the two conductive source regions (9) and the dielectric layer (11), a metal source electrode (10) is jointly provided.

2. A high-power and low-density silicon carbide MOSFET device according to claim 1, characterized in that: The gate oxide layer (12) and the anti-radiation layer are in contact. The anti-radiation layer is made of hafnium dioxide.

3. A high-power and low-density silicon carbide MOSFET device according to claim 1, characterized in that: The metal source electrode (10) is located above the conductive source region (9) and the dielectric layer (11). The interfaces between the metal source electrode (10) and the conductive source region (9) and the dielectric layer (11) are both ohmic contacts. The interface between the drain (1) and the silicon carbide substrate (2) is an ohmic contact.

4. A high-power and low-density silicon carbide MOSFET device according to claim 3, characterized in that: Inside the conductive shielding layer (16), a first buffer trench (161) and a second buffer trench (162) are provided. The first buffer trench (161) and the second buffer trench (162) are connected and communicate with each other.

5. A high-power and low-density silicon carbide MOSFET device according to claim 1, characterized in that: The thickness of the N-drift region (6) is 40 - 70 μm.

6. A high-power and low-density silicon carbide MOSFET device according to claim 1, characterized in that: At one end of both of the triangular groove regions away from the conductive channel region (14), triangular extension regions are provided, and the two triangular extension regions are respectively connected and communicate with the P-well region (17) and the conductive contact layer (5).

7. A high-power and low-density silicon carbide MOSFET device according to claim 1, characterized in that: The distance between the two triangular groove regions is not greater than 5.0 μm.

8. A high-power and low-density silicon carbide MOSFET device according to claim 1, characterized in that: The thickness of the P-well region (17) is not greater than 2.5 μm.

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