AVS3-8K video decoding device

Abstract

The utility model discloses an AVS3-8K video decoding device, which comprises an FPGA chip, a network interface, a USB interface, a TF card interface, an HDM I interface and at least two DDR memories, the FPGA chip comprises a high-speed transceiver, an HPS module and a logic module, the HDM I interface is connected with the high-speed transceiver through a link equalization chip, the TF card interface is connected with the HPS module through a level conversion chip, the USB interface is connected with the HPS module, and the logic module is connected with the HPS module through a network interface. The network interface is connected with the HPS module, the at least one DDR memory is connected with the HPS module, and the at least one DDR memory is connected with the logic module.

Description

Technical Field

[0001] The utility model belongs to the field of video signal transmission, and particularly relates to an AVS3-8K video decoding device. Background Art

[0002] The AVS3 decoding device is implemented in a software decoding manner, which requires the high computing power of a high-performance CPU. Generally, a software decoding device is built according to the standard of a multi-core server. This kind of AVS3 decoding device has high construction cost, huge volume, and high energy consumption ratio, and is not suitable for popularizing the AVS3 decoding standard. Content of the Utility Model

[0003] The technical problem to be solved by the utility model is the problem of high energy consumption ratio of the existing decoding device.

[0004] The utility model provides an AVS3-8K video decoding device.

[0005] An AVS3-8K video decoding device includes: an FPGA chip, a network interface, a USB interface, a TF card interface, an HDMI interface, and at least two DDR memories. The FPGA chip includes a high-speed transceiver, an HPS module, and a logic module. The HDMI interface is connected to the high-speed transceiver through a link equalization chip. The TF card interface is connected to the HPS module through a level conversion chip. The USB interface is connected to the HPS module. The network interface is connected to the HPS module. At least one DDR memory is connected to the HPS module, and at least one DDR memory is connected to the logic module.

[0006] Preferably, the network interface includes a PHY chip, and the USB interface includes a PHY chip.

[0007] Preferably, it includes an FPGA power supply for powering the FPGA chip. The FPGA power supply adopts a 2+1 phase power supply. The peak value of the 2-phase power supply does not exceed 65 watts, and the peak value of the 1-phase power supply does not exceed 30 watts.

[0008] Preferably, the FPGA chip includes a timing single-chip microcomputer for controlling the power-on timing.

[0009] Preferably, it includes a high-speed transceiver power supply for powering the high-speed transceiver. The rated current of the high-speed transceiver power supply does not exceed 30A.

[0010] Preferably, the FPGA includes a core and an ERAM. The core is powered by 2 phases, and the ERAM is powered by 1 phase.

[0011] The decoding process of this utility model is as follows: The compressed bitstream enters the HPS end of the S10 SoC from the network port. The ARM side analyzes the division of the bitstream, initializes each thread, separates the HPS audio and video bitstreams, pushes the HPS video bitstream into the AVS3 Decoder to start decoding, stores the decoded data in the DDR, and the HDMI display module transports the data in the DDR and transmits it to the display terminal for playback.

[0012] This utility model has the following advantages and effects compared with the prior art:

[0013] The decoding component of this device is an FPGA, and its price is half of that of the CPU used in existing servers, which can greatly reduce the material cost. The full-load decoding power consumption of this decoding device is only 45 watts, saving energy compared with the power consumption of more than 500 watts of existing servers. Brief Description of the Drawings

[0014] In order to more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of this utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0015] Figure 1 It is the decoding flow chart of the FPGA chip.

[0016] Figure 2 It is the hardware schematic diagram of this device. Detailed Embodiments

[0017] In order to make the purpose, technical solutions and advantages of this utility model clearer, the following further details this utility model in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this utility model and are not used to limit this utility model.

[0018] Embodiment 1:

[0019] An AVS3-8K video decoding device includes: an FPGA chip, a network interface, a USB interface, a TF card interface, an HDMI interface, and at least two DDR memories. The FPGA chip includes a high-speed transceiver, an HPS module, and a logic module. The HDMI interface is connected to the high-speed transceiver through a link equalization chip, the TF card interface is connected to the HPS module through a level conversion chip, the USB interface is connected to the HPS module, the network interface is connected to the HPS module, at least one DDR memory is connected to the HPS module, and at least one DDR memory is connected to the logic module.

[0020] As Figure 1As shown in the figure, the detailed process of AVS3 decoding inside the FPGA chip: The compressed bitstream enters the HPS end of the S10 SoC (i.e., the hard-core ARM processor) from the network port. The ARM processor is responsible for receiving the bitstream and performing preliminary bitstream detection to determine whether the compressed bitstream contains an audio stream and a video stream. By default, the first discovered audio / video stream is selected. For each stream, preliminary parsing is performed. The video stream parses information such as the encoding format, resolution, encoding profile, frame rate, and pixel format, and the audio stream parses information such as the encoding format, sampling rate, sampling precision, and number of channels. Based on the above analysis results, the demultiplexing thread is initialized, the HDMI audio / video playback thread and the output-related configuration are initialized, the audio software decoder is initialized and the audio decoding thread is started, the AVS3 decoding IP is initialized and the video decoding task scheduling thread is started. The HPS demultiplexer separates the audio and video bitstreams and sends them to the audio and video queues respectively; the audio is decoded in the audio decoding thread, and the decoded data is sent to the audio PCM queue; after the video stream buffer has buffered the bitstream of a GOP, an AVS3 Decoder with the status of idle is searched for. After finding it, the status of this AVS3 Decoder module is switched to the busy state. If it is "AVS3 Decoder 0", the ARM side writes a complete GOP bitstream to the DDR4_1 on the FPGA side and configures the relevant registers to start "AVS3 Decoder 0" for decoding; if it is "AVS3 Decoder 1", the ARM side writes a complete GOP bitstream to the DDR4_2 on the FPGA side and configures the relevant registers to start "AVS3 Decoder 1" for decoding. After the decoding module completes decoding, it writes the address of the video frame to be displayed into the display queue (if the current display queue is full, it means that the decoding is faster than the display, and the video frames in the DDR1 / DDR2 memory have not been fully displayed yet. At this time, a waiting state is entered until the display address is successfully written into the queue), and its own status is restored to idle. In the display thread, PCM data can be read from the audio PCM queue, the address of the video frame that can be displayed is obtained from the display queue, the HDMI2.1 display data reading module is controlled to read the decoded video data according to the display frame rate and timing and give it to the HDMI 2.1TX IP, the HDMI2.1 audio data reading module is controlled to read the decoded audio PCM data according to the audio sampling rate and give it to the HDMI 2.1TX IP, and the HDMI2.1 TX IP encodes the audio and video data according to the HDMI 2.1 protocol and converts the parallel data into serial data through the internal high-speed transceiver of the FPGA and outputs it to the HDMI2.1 interface, and outputs the decoded audio and video data to the display terminal through the HDMI2.1 interface for playback.

[0021] A preferred embodiment is as Figure 2As shown in the figure, the FPGA model of this device is 1SX280LN2F43 series. The gigabit Ethernet port part uses the PHY chip RTL8211F to implement functions and is physically connected to the HPS side of the FPGA. The USB interface part uses the PHY chip USB3320 to implement functions and is physically connected to the HPS side of the FPGA. The TF card interface part is connected to the HPS side of the FPGA through a level conversion chip TXS0108E. The HDMI interface part is connected to the high-speed transceiver on the PFGA side through a link equalization chip model DS125BR820. The first group of DDR caches consists of 4 16-bit DDR4 chips connected to the HPS side of the FPGA, with a capacity of 4GB. The second group of DDR caches consists of 4 16-bit DDR4 chips connected to the logic side of the FPGA, with a capacity of 8GB. The third group of DDR caches consists of 4 16-bit DDR4 chips connected to the logic side of the FPGA, with a capacity of 8GB.

[0022] In a preferred embodiment, for the power supply part: the FPGA core power supply adopts a 2+1 phase power supply mode. The 2-phase power supply provides a peak power supply of 65 watts for the FPGA core, and the 1-phase power supply provides a peak power supply of 30 watts for the internal ERAM of the FPGA. The chip models are PXE1410C+TDA21472. The high-speed transceiver power supply uses a DCDC chip model IS6608A with a single power supply capacity of 30A. The FPGA power-on timing is controlled by a single-chip microcomputer STM32F03, and this single-chip microcomputer is also used to drive the infrared reception signal.

[0023] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims

1. An AVS3-8K video decoding device, characterized in that, Including: An FPGA chip, a network interface, a USB interface, a TF card interface, an HDMI interface, and at least two DDR memories. The FPGA chip includes a high-speed transceiver, an HPS module, and a logic module. The HDMI interface is connected to the high-speed transceiver through a link equalization chip. The TF card interface is connected to the HPS module through a level conversion chip. The USB interface is connected to the HPS module. The network interface is connected to the HPS module. At least one DDR memory is connected to the HPS module. At least one DDR memory is connected to the logic module.

2. The AVS3-8K video decoding device according to claim 1, wherein The network interface includes a PHY chip. The USB interface includes a PHY chip.

3. The AVS3-8K video decoding device according to claim 1, wherein Including an FPGA power supply for powering the FPGA chip. The FPGA power supply uses a 2+1 phase power supply. The peak of the 2-phase power supply does not exceed 65 watts. The peak of the 1-phase power supply does not exceed 30 watts.

4. The AVS3-8K video decoding device according to claim 1, characterized in that, The FPGA chip includes a timing single-chip microcomputer for controlling the power-on timing.

5. The AVS3-8K video decoding device according to claim 1, wherein Including a high-speed transceiver power supply for powering the high-speed transceiver. The rated current of the high-speed transceiver power supply does not exceed 30A.

6. The AVS3-8K video decoding device according to claim 3, wherein The FPGA includes a core and an ERAM. The core is powered by 2 phases. The ERAM is powered by 1 phase.

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