Sampling circuit, driving chip and switching power supply

Abstract

The utility model discloses a sampling circuit, a driving chip and a switching power supply, the sampling circuit is applied to the driving chip which outputs a pulse width modulation signal to drive a first switching tube to be switched on or switched off, and the sampling circuit comprises at least two sampling signal generation branches, a signal selection branch and a switching branch. Any sampling signal generation branch is used for sampling a degaussing signal period, and different sampling signal generation branches generate sampling signals based on different positions of the degaussing signal period. And the signal selection branch outputs a sampling signal generated by the sampling signal generation branch based on the first voltage output by the sampling circuit. And the switch branch is switched on and outputs a degaussing signal when receiving the sampling signal. Through the mode, the sampling position can be adjusted according to the load size, so that the sampling precision is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of electronic circuits, and in particular to a sampling circuit, a driver chip, and a switching power supply. Background Art

[0002] Primary-Side Regulation (PSR) switching power supplies are an advanced power supply design technology used to simplify power supply circuits and improve efficiency. Compared to traditional secondary-side feedback (SSR) switching power supplies, PSR switching power supplies directly detect and control the output voltage on the primary side (input side), eliminating the need for secondary-side feedback circuitry. This simplifies design, reduces costs, and improves system reliability.

[0003] PSR switching power supplies typically require sampling a demagnetization signal to adjust their output voltage. However, the current method of sampling at a fixed position in the demagnetization signal cycle has poor sampling accuracy. Utility Model Content

[0004] The embodiments of the present application provide a sampling circuit, a driver chip, and a switching power supply, which can adjust the sampling position according to the load size to improve the sampling accuracy.

[0005] In a first aspect, an embodiment of the present application provides a sampling circuit, which is applied to a driver chip that outputs a pulse width modulation signal to drive a first switch tube to turn on or off. The sampling circuit includes:

[0006] At least two sampling signal generating branches, each sampling signal generating branch is used to sample a degaussing signal period, and different sampling signal generating branches generate sampling signals based on different positions of the degaussing signal period;

[0007] a signal selection branch connected to the at least two sampling signal generation branches and the first voltage output by the sampling circuit, and configured to output a sampling signal generated by one of the at least two sampling signal generation branches based on the first voltage;

[0008] The switch branch is connected to the signal selection branch and inputs a demagnetization signal, and is used to be turned on and output the demagnetization signal when receiving the sampling signal.

[0009] In one or more embodiments, the sampling circuit further includes:

[0010] a first filtering branch, connected to the switch branch, and configured to filter the demagnetization signal output by the switch branch;

[0011] a signal following branch, connected to the first filtering branch, and configured to output a sampling voltage that is the same as the voltage of the filtered demagnetization signal;

[0012] a signal amplifying branch connected to the signal following branch and inputting a reference voltage, for amplifying the difference between the reference voltage and the sampling voltage and then outputting an amplified signal;

[0013] The second filtering branch is connected to the signal amplifying branch, and is used to filter the amplified signal and output the first voltage.

[0014] In one or more embodiments, the at least two sampling signal generating branches include a first sampling signal generating branch, a second sampling signal generating branch, and a third sampling signal generating branch, wherein the first sampling signal generating branch is configured to generate a first sampling signal at a moment after a first preset time length has elapsed from the start of the demagnetization signal period, the second sampling signal generating branch is configured to generate a second sampling signal at a middle moment of the demagnetization signal period, and the third sampling signal generating branch is configured to generate a third sampling signal at a moment 2 / 3 of the demagnetization signal period;

[0015] The signal selection branch is further used to output the first sampling signal when the first voltage is less than a first preset voltage, and to output the second sampling signal when the first voltage is greater than or equal to the first preset voltage and less than or equal to a second preset voltage, and to output the third sampling signal when the first voltage is greater than the second preset voltage, wherein the first preset voltage is less than the second preset voltage.

[0016] In one or more embodiments, the signal selection branch includes a first comparator, a second comparator, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, and a selector;

[0017] The first voltage is input to the non-inverting input of the first comparator, the first preset voltage is input to the inverting input of the first comparator, the output of the first comparator is connected to the input of the first NOT gate, the output of the first NOT gate is connected to the input of the second NOT gate, and the output of the second NOT gate outputs a first selection signal to the selector;

[0018] The first voltage is input to the non-inverting input of the second comparator, the second preset voltage is input to the inverting input of the second comparator, the output of the second comparator is connected to the input of the third NOT gate, the output of the third NOT gate is connected to the input of the fourth NOT gate, and the output of the fourth NOT gate outputs a second selection signal to the selector;

[0019] The first input terminal of the selector inputs the first sampling signal, the second input terminal of the selector inputs the second sampling signal, and the third input terminal of the selector inputs the third sampling signal. The first sampling signal is output when the first selection signal is low and the second selection signal is low, the second sampling signal is output when the first selection signal is high and the second selection signal is low, and the third sampling signal is output when the first selection signal is high and the second selection signal is high.

[0020] In one or more embodiments, the switch branch includes a second switch tube;

[0021] The first end of the second switch tube is connected to the signal selection branch, the second end of the second switch tube inputs the demagnetization signal, and the third end of the second switch tube is used to output the demagnetization signal.

[0022] In one or more embodiments, the first filtering branch includes a first resistor and a first capacitor, and the second filtering branch includes a fourth resistor and a second capacitor;

[0023] The first resistor and the first capacitor are connected in series between the switch branch and the ground, and a connection point between the first resistor and the first capacitor is connected to the signal follower branch;

[0024] The fourth resistor and the second capacitor are connected in series between the signal amplifying branch and the ground.

[0025] In one or more embodiments, the signal follower branch includes an operational amplifier;

[0026] The non-inverting input terminal of the operational amplifier is connected to the first filtering branch, and the inverting input terminal of the operational amplifier is connected to the output terminal and the signal amplifying branch.

[0027] In one or more embodiments, the signal amplification branch includes a second resistor, a third resistor, and a third comparator;

[0028] The second resistor and the third resistor are connected in series between the signal follower branch and the output end of the third comparator. The output end of the third comparator is also connected to the second filter branch. The connection point between the second resistor and the third resistor is connected to the inverting input end of the third comparator. The reference voltage is input to the non-inverting input end of the third comparator.

[0029] In a second aspect, an embodiment of the present application provides a driver chip comprising the sampling circuit as described above.

[0030] In a third aspect, an embodiment of the present application provides a switching power supply, comprising a first switching tube and the driver chip as described above, wherein the driver chip is configured to output a pulse width modulation signal to drive the first switching tube to be turned on or off.

[0031] The beneficial effects of the present application are as follows: the sampling circuit of the embodiment of the present application is applied to a driver chip in a switching power supply, wherein the switching power supply further includes a first switching tube, and the driver chip is used to output a pulse width modulation signal to drive the first switching tube to turn on or off. The sampling circuit includes at least two sampling signal generation branches, a signal selection branch, and a switch branch. Among them, any sampling signal generation branch is used to sample the demagnetization signal cycle, and different sampling signal generation branches generate sampling signals based on different positions of the demagnetization signal cycle. When performing signal sampling, the signal selection branch outputs the sampling signal generated by at least one of the two sampling signal generation branches to the switch branch based on the first voltage output by the sampling circuit, so that the switch branch is turned on and outputs the demagnetization signal. It can be seen that the signal selection branch can determine the load size based on the first voltage, and then determine the sampling signal to be output, and the sampling position is determined by determining the sampling signal. In summary, the sampling position is adjusted according to the load size, which is conducive to improving the sampling accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] One or more embodiments are exemplarily described by the figures in the accompanying drawings, which are not intended to limit the embodiments. Elements with the same reference numerals in the drawings represent similar elements.

[0033] Figure 1 It is a schematic diagram of a block diagram of a switching power supply provided in an embodiment of the present application;

[0034] Figure 2 Schematic diagram of the circuit structure of the switching power supply provided in an embodiment of the present application;

[0035] Figure 3 This is a schematic diagram of the composition block diagram of the sampling circuit provided in the embodiment of the present application. Figure 1 ;

[0036] Figure 4 This is a schematic diagram of the composition block diagram of the sampling circuit provided in the embodiment of the present application. Figure 2 ;

[0037] Figure 5 This is a schematic diagram of the composition block diagram of the sampling circuit provided in the embodiment of the present application. Figure 3 ;

[0038] Figure 6 is with Figure 5 Schematic diagram of circuit structure corresponding to the structure shown;

[0039] Figure 7 yes Figure 6 Schematic diagram of each signal in the circuit structure shown. DETAILED DESCRIPTION

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of them. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0041] It should be noted that, when an element is described as being “connected to” another element, it may be directly connected to the other element, or one or more intervening elements may exist therebetween.

[0042] In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as there is no structural conflict between them.

[0043] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the composition block diagram of the switching power supply provided in the embodiment of the present application. Figure 1 As shown, the switching power supply 10000 includes a first switch tube Q1 and a driver chip 1000. The driver chip 1000 is used to output a pulse width modulation signal PWM1 to drive the first switch tube Q1 to be turned on or off. In some embodiments, the first switch tube Q1 is turned on in response to a high level of the pulse width modulation signal PWM1, and is turned off in response to a low level of the pulse width modulation signal PWM1. Pulse width modulation (PWM) is a technology that controls the effective value of the output signal by changing the width of a series of fixed frequency pulses, that is, adjusting the duty cycle of these pulses (the ratio of the high level time to the entire cycle time). The first switch tube Q1 is an electronic component that is mainly used to control the flow of current in the circuit and can quickly switch between the on and off states. The first switch tube Q1 can be any controllable switch, such as a MOS tube or a transistor.

[0044] In some embodiments, the switching power supply 10000 may be an AC-DC converter, a DC-DC converter, or a linear power supply. In other embodiments, the switching power supply 10000 may be a primary-side regulation (PSR) switching power supply.

[0045] Please refer to Figure 2 , Figure 2 The circuit structure of the switching power supply 10000 when it is a PSR switching power supply is shown as an example. Figure 2As shown, the switching power supply 10000 further includes resistors RA1, RA2, RA3, RA4, a primary winding LP, a secondary winding LS1, an auxiliary winding LS2, diodes DA1, DA2, capacitors CA1, and CA2. In this embodiment, the first switching transistor Q1 is an NMOS transistor. The first terminal of the first switching transistor Q1 serves as the gate of the NMOS transistor, the second terminal of the first switching transistor Q1 serves as the source of the NMOS transistor, and the third terminal of the first switching transistor Q1 serves as the drain of the NMOS transistor.

[0046] The first end of the resistor RA1 is connected to the input voltage VIN and the same-name end of the primary winding LP respectively, the opposite-name end of the primary winding LP is connected to the drain of the first switch tube Q1, the drain of the primary winding LP is connected to the first end of the resistor RA2, the second end of the resistor RA2 is grounded GND, the opposite-name end of the secondary winding LS1 is connected to the anode of the diode DA1, the same-name end of the secondary winding LS1 and the second end of the capacitor CA1 are both grounded GND, the cathode of the diode DA1 is connected to the first end of the capacitor CA1, and the output voltage VOUT is output. The auxiliary winding The opposite-name ends of LS2 are respectively connected to the anode of diode DA2 and the first end of resistor RA3, the cathode of diode DA2 is respectively connected to the first end of capacitor CA2 and the second end of resistor RA1, the same-name end of auxiliary winding LS2 and the second end of capacitor CA2 are both grounded GND, the second end of resistor RA3 is connected to the first end of resistor RA4, the second end of resistor RA4 is grounded GND, the second end of resistor RA2, the gate of first switch tube Q1, the first end of resistor RA2 and the first end of resistor RA4 are all connected to driver chip 1000.

[0047] Figure 2 The circuit shown operates as follows: After input voltage VIN is applied, resistor RA1 and startup capacitor CA2 begin supplying power to the power pin of driver chip 1000. Driver chip 1000 generates a pulse-width modulated signal PWM1 to drive first switch Q1. When first switch Q1 is on, input voltage VIN charges primary winding LP. When first switch Q1 is off, energy is transferred to secondary winding LS1 and auxiliary winding LS2. The current flowing through secondary winding LS1 is rectified by diode DA1 and charges output capacitor CA1, providing power to the load. Simultaneously, the current flowing through auxiliary winding LS2 is rectified by diode DA2 and provides power to driver chip 1000. Simultaneously, driver chip 1000 monitors the current flowing through primary winding LP via overcurrent sensing resistor RA2 and indirectly controls output voltage VOUT via feedback signals generated by resistors RA3 and RA4.

[0048] During each cycle of the pulse-width modulated signal PWM1, when the pulse-width modulated signal PWM1 transitions to a high level, the input voltage VIN charges the primary winding LP, causing the current flowing through the primary winding LP to increase at a predetermined slope. At this time, due to the presence of diode DA1, the current flowing through the secondary winding LS1 is zero. The voltages at the opposite terminals of the secondary winding LS1 and the auxiliary winding LS2 are negative, and the feedback signal is also negative. When the pulse-width modulated signal PWM1 transitions to a low level, the switching power supply 10000 enters the demagnetization phase. The voltages across the windings reverse, and the current flowing through the primary winding LP drops to zero. The energy stored in the transformer is released through the secondary winding LS1 and the auxiliary winding LS2. The current flowing through the secondary winding LS1 reaches a peak value and then slowly decreases to zero, ending the demagnetization phase. The demagnetization signal period is the duration from the moment the switching power supply 10000 enters the demagnetization phase (when the pulse-width modulation signal PWM1 transitions to a low level) to the moment the current flowing through the secondary winding LS1 decreases to zero. During the demagnetization signal period, the voltage between resistors RA3 and RA4 is the demagnetization signal. This indicates that the driver chip 1000 can both determine the demagnetization signal period and obtain the demagnetization signal.

[0049] Please refer back to Figure 1 Driver chip 1000 includes a sampling circuit 100. Sampling circuit 100 receives a first voltage VCOMP as input, samples a demagnetization signal based on the first voltage VCOMP, and adjusts first voltage VCOMP based on the sampling result. Subsequently, other circuit structures in driver chip 1000 adjust the frequency and duty cycle of pulse-width modulation signal PWM1 based on the first voltage VCOMP to adjust the output voltage VOUT.

[0050] Please refer to Figure 3 , Figure 3 Schematic diagram of the composition block diagram of the sampling circuit 100 provided in the embodiment of the present application. Among them, the sampling circuit is applied to the driver chip in the switching power supply, and the switching power supply also includes a first switch tube. The driver chip is used to output a pulse width modulation signal to drive the first switch tube to turn on or off. The specific implementation of the switching power supply can refer to the embodiment of the present application. Figure 1 and Figure 2 The description of , will not be repeated here. Figure 3 As shown, the sampling circuit 100 includes at least two sampling signal generating branches, a signal selecting branch 10 and a switching branch 20 .

[0051] The at least two sampling signal generating branches include a first sampling signal generating branch A1, a second sampling signal generating branch A2, ..., and an Nth sampling signal generating branch AN, where N is an integer greater than or equal to 2. Each sampling signal generating branch is used to sample the demagnetization signal period, i.e., the first sampling signal generating branch A1 is used to sample the demagnetization signal period, the second sampling signal generating branch A2 is used to sample the demagnetization signal period, ..., and the Nth sampling signal generating branch AN is used to sample the demagnetization signal period. Different sampling signal generating branches generate sampling signals based on different positions in the demagnetization signal period, i.e., the first sampling signal generating branch A1 generates a first sampling signal SAM1 based on a first position in the demagnetization signal period, the second sampling signal generating branch A2 generates a second sampling signal SAM2 based on a second position in the demagnetization signal period, ..., and the Nth sampling signal generating branch AN generates an Nth sampling signal SAMN based on an Nth position in the demagnetization signal period; any two of the first position, the second position, ..., and the Nth position are different.

[0052] The signal selection branch 10 is connected to at least two sampling signal generation branches and the first voltage VCOMP output by the sampling circuit 100. The signal selection branch 10 is configured to output a sampling signal generated by one of the at least two sampling signal generation branches based on the first voltage VCOMP. That is, the signal selection branch 10 outputs one of the first sampling signal SAM1, the second sampling signal SAM2, ..., and the Nth sampling signal SAMN based on the first voltage VCOMP.

[0053] The switch branch 20 is connected to the signal selection branch 10. The switch branch 20 inputs the demagnetization signal SDE. The switch branch 20 is configured to conduct and output the demagnetization signal SDE upon receiving the sampling signal. The driver chip 1000 is configured to adjust the frequency and duty cycle of the pulse width modulation signal PWM1 based on the demagnetization signal output by the switch branch 20 to adjust the output voltage VOUT.

[0054] In summary, since the signal selection branch 10 inputs the first voltage VCOMP, which is derived from the demagnetization signal SDE, and the demagnetization signal SDE is related to the current flowing through the auxiliary winding LS2 (i.e., the current flowing through the secondary winding LS1, and thus the load size), the signal selection branch 10 can determine the load size based on the first voltage VCOMP. For example, if the signal selection branch 10 determines that the first voltage VCOMP is less than the first preset voltage, the load is small. Furthermore, based on the load size, the signal selection branch 10 can determine which sampling signal to output: the first sampling signal SAM1, the second sampling signal SAM2, ..., or the Nth sampling signal SAMN, and output it. For example, if the signal selection branch 10 determines that the sampling signal to output is the first sampling signal SAM1 based on the load size, the first sampling signal SAM1 is output. Subsequently, the switch branch 20 switches the demagnetization signal SDE based on the received sampling signal. In this case, the sampling position for sampling the demagnetization signal SDE is determined by the sampling signal received by the switch branch 20. Thus, the process of adjusting the sampling position by adjusting the sampling signal according to the load size is realized. Compared with the method of sampling only at a fixed position of the demagnetization signal cycle in the related art, the embodiment of the present application provides a method of sampling by adjusting the sampling position according to the load size. This method can not only increase the probability of avoiding the ringing portion of the demagnetization signal, but also reduce the probability of not collecting the demagnetization signal due to the short demagnetization signal cycle, which is conducive to improving the sampling accuracy. The ringing portion refers to the portion of the demagnetization signal with large voltage fluctuations at the front end due to the leakage inductance of the transformer. If the ringing portion of the demagnetization signal is sampled, it will cause a large error in the subsequent control of the output voltage VOUT.

[0055] In some embodiments, as Figure 4 As shown, the sampling circuit 100 further includes a first filtering branch 30 , a signal following branch 40 , a signal amplifying branch 50 and a second filtering branch 60 .

[0056] The first filter branch 30 is connected to the switch branch 20 and is configured to filter the demagnetization signal SDE output by the switch branch 20. The signal follower branch 40 is connected to the first filter branch 30 and is configured to output a sampling voltage equal to the voltage of the filtered demagnetization signal SDE. The signal amplification branch 50 is connected to the signal follower branch 40 and inputs a reference voltage VREF3. The signal amplification branch 50 is configured to amplify the difference between the reference voltage VREF3 and the sampling voltage and output an amplified signal VCOMP. The second filter branch 60 is connected to the signal amplification branch 50 and is configured to filter the amplified signal VCOMP. The driver chip 1000 is further configured to adjust the frequency and duty cycle of the pulse width modulation signal PWM1 based on the filtered amplified signal VCOMP.

[0057] In some embodiments, as Figure 5 As shown, at least two sampling signal generating branches include a first sampling signal generating branch A1, a second sampling signal generating branch A2 and a third sampling signal generating branch A3, wherein the first sampling signal generating branch A1 is used to generate a first sampling signal SAM1 at a moment after a first preset time length from the start moment of the demagnetization signal period (denoted as T_SDE), the second sampling signal generating branch A2 is used to generate a second sampling signal SAM2 at a middle moment of the demagnetization signal period (i.e., the moment where 1 / 2T_SDE is located), and the third sampling signal generating branch A3 is used to generate a third sampling signal SAM3 at a moment of 2 / 3 of the demagnetization signal period (i.e., the moment where 2 / 3T_SDE is located).

[0058] The signal selection branch 10 is further configured to output a first sampling signal SAM1 when the first voltage VCOMP is less than a first preset voltage VREF1, a second sampling signal SAM2 when the first voltage VCOMP is greater than or equal to the first preset voltage VREF1 and less than or equal to a second preset voltage VREF2, and a third sampling signal SAM3 when the first voltage VCOMP is greater than the second preset voltage VREF2. The first preset voltage VREF1 and the second preset voltage VREF2 can be set according to actual application scenarios and are not specifically limited in this embodiment of the present application. Furthermore, the first preset voltage VREF1 is less than the second preset voltage VREF2. In this embodiment of the present application, a light load corresponds to a first voltage VCOMP less than the first preset voltage VREF1; a medium load corresponds to a first voltage VCOMP greater than or equal to the first preset voltage VREF1 and less than or equal to the second preset voltage VREF2; and a heavy load corresponds to a first voltage VCOMP greater than the second preset voltage VREF2. This allows the sampling signal to be adjusted based on the load size, thereby adjusting the sampling position, which improves sampling accuracy.

[0059] Please refer to Figure 6 , Figure 6 For Figure 5 A circuit structure corresponding to the block diagram shown in FIG. Figure 6 As shown, the signal selection branch 10 includes a first comparator U1 , a second comparator U2 , a first NOT gate NOT1 , a second NOT gate NOT2 , a third NOT gate NOT3 , a fourth NOT gate NOT4 and a selector UB1 .

[0060] The first comparator U1 has a non-inverting input terminal inputting a first voltage VCOMP, an inverting input terminal inputting a first preset voltage VREF1, an output terminal of the first comparator U1 connected to an input terminal of a first NOT gate NOT1, an output terminal of the first NOT gate NOT1 connected to an input terminal of a second NOT gate NOT2, and an output terminal of the second NOT gate NOT2 outputting a first selection signal to the selector UB1; the second comparator U2 has a non-inverting input terminal inputting a first voltage VCOMP, an inverting input terminal of the second comparator U2 inputting a second preset voltage VREF2, an output terminal of the second comparator U2 connected to an input terminal of a third NOT gate NOT3, and an output terminal of the third NOT gate NOT3. The first sampling signal SAM1 is input to the first input of the selector UB1, the second sampling signal SAM2 is input to the second input of the selector UB1, and the third sampling signal SAM3 is input to the third input of the selector UB1. When the first selection signal is low and the second selection signal is low, the first sampling signal SAM1 is output; when the first selection signal is high and the second selection signal is low, the second sampling signal SAM2 is output; and when the first selection signal is high and the second selection signal is high, the third sampling signal SAM3 is output.

[0061] In some embodiments, the switch branch 20 includes a second switch Q2 , a first terminal of which is connected to the signal selection branch 10 , a second terminal of which is input with the demagnetization signal SDE, and a third terminal of which is used to output the demagnetization signal SDE.

[0062] In this embodiment, the second switch transistor Q2 is an NMOS transistor, for example, wherein the gate of the NMOS transistor is the first end of the second switch transistor Q2, the source of the NMOS transistor is the second end of the second switch transistor Q2, and the drain of the NMOS transistor is the third end of the second switch transistor Q2.

[0063] In addition, the second switch tube Q2 can be any controllable switch, such as an insulated gate bipolar transistor (IGBT) device, an integrated gate-commutated thyristor (IGCT) device, a gate-turn-off thyristor (GTO) device, a silicon-controlled rectifier (SCR) device, a junction-gate field-effect transistor (JFET) device, a MOS-controlled thyristor (MCT) device, etc.

[0064] In some embodiments, the first filtering branch 30 includes a first resistor R1 and a first capacitor C1. The first resistor R1 and the first capacitor C1 are connected in series between the switch branch 20 and ground GND. The connection point between the first resistor R1 and the first capacitor C1 is connected to the signal follower branch 40. The first resistor R1 and the first capacitor C1 are used to implement RC filtering.

[0065] In some embodiments, the signal follower branch 40 includes an operational amplifier UA3. The non-inverting input terminal of the operational amplifier UA3 is connected to the first filter branch 30, and the inverting input terminal of the operational amplifier UA3 is connected to the output terminal and is connected to the signal amplification branch 50. The signal follower branch 40 can be used to copy the signal input to the non-inverting input terminal of the operational amplifier UA3 and pass it to the output, while trying not to change the amplitude of the signal, that is, the voltage output by the operational amplifier UA3 is equal to the voltage corresponding to the filtered demagnetization signal SDE. The signal follower branch 40 can effectively isolate the front-stage and rear-stage circuits to prevent load changes from adversely affecting the signal source. Depending on the type of active device used, the signal follower branch 40 can be divided into several different forms, including voltage followers, current followers, source followers, etc.

[0066] In some embodiments, the signal amplification branch 50 includes a second resistor R2, a third resistor R3, and a third comparator UA4. The second resistor R2 and the third resistor R3 are connected in series between the signal follower branch 40 and the output of the third comparator UA4. The output of the third comparator UA4 is also connected to the second filter branch 60. The connection point between the second resistor R2 and the third resistor R3 is connected to the inverting input of the third comparator UA4. The non-inverting input of the third comparator UA4 receives a reference voltage VREF3. In this embodiment, the magnitude of the first voltage VCOMP is: VCOMP = ((R2 + R3) * VREF - R3 * VSDE) / R2, where VSDE is the voltage output by the op amp UA3.

[0067] In some embodiments, the second filtering branch 60 includes a fourth resistor R4 and a second capacitor C2. The fourth resistor R4 and the second capacitor C2 are connected in series between the signal amplifying branch 50 and the ground GND. The fourth resistor R4 and the second capacitor C2 form an RC filter.

[0068] The following will be combined Figure 7 right Figure 6 The principle of the circuit shown is explained. Figure 7 In the figure, the horizontal axis represents time; the vertical axes represent the first voltage VCOMP, the demagnetization signal SDE, and the sampling signal SAMK from top to bottom, respectively. The sampling signal SAMK is one of the first sampling signal SAM1, the second sampling signal SAM2, and the third sampling signal SAM3, that is, K is one of 1, 2, and 3.

[0069] Specifically, at time t1, the first voltage VCOMP is greater than the second preset voltage VREF2, corresponding to a heavy load. The selector UB1 outputs the third sampling signal SAM3, i.e., the demagnetization signal SDE is sampled at time t3. The duration between time t1 and time t3 is 2 / 3 of the demagnetization signal period (i.e., 2 / 3T_SDE). Before time t4, the first voltage VCOMP remains greater than the second preset voltage VREF2, so the selector UB1 outputs the third sampling signal SAM3 in each period, and the demagnetization signal SDE is sampled at 2 / 3 of the demagnetization signal period. Figure 7 It can be seen that each sampling moment skips the ringing part of the demagnetization signal SDE (such as the part corresponding to the duration between time t1 and time t2), and can complete the sampling within the range of the demagnetization signal SDE, with high sampling accuracy.

[0070] Until time t4, the first voltage VCOMP decreases to be equal to and begins to be less than the second preset voltage VREF2. At the same time, the first voltage VCOMP is still greater than the first preset voltage VREF1. At this time, the corresponding load is medium load, and the selector UB1 outputs the second sampling signal SAM2, that is, the demagnetization signal SDE is sampled at time t7. The duration between time t5 and time t7 is 1 / 2 of the demagnetization signal cycle (i.e., 1 / 2T_SDE). Before time t8, the first voltage VCOMP remains less than the second preset voltage VREF2 and greater than the first preset voltage VREF1, so the selector UB1 outputs the second sampling signal SAM2 in each cycle, and keeps sampling the demagnetization signal SDE at the moment of 1 / 2 of the demagnetization signal cycle. Figure 7 It can be seen that each sampling moment skips the ringing part of the demagnetization signal SDE (such as the part corresponding to the duration between time t5 and time t6), and can complete the sampling within the range of the demagnetization signal SDE, with high sampling accuracy.

[0071] Until time t8, the first voltage VCOMP decreases to be equal to and then begins to be less than the first preset voltage VREF1. At this time, the corresponding load is light, and the selector UB1 outputs the first sampling signal SAM1, that is, the demagnetization signal SDE is sampled at time t11. The time between time t9 and time t11 is the first preset time. Before time t12, the first voltage VCOMP remains less than the first preset voltage VREF1, so the selector UB1 outputs the first sampling signal SAM1 in each cycle, and keeps sampling the demagnetization signal SDE at the moment when the first preset time has passed from the start of the demagnetization signal cycle. Figure 7It can be seen that the ringing part of the demagnetization signal SDE (such as the part corresponding to the duration between time t9 and time t10) is skipped at each sampling moment, and although the duration of the demagnetization signal SDE is short each time, the sampling can still be completed within the range of the demagnetization signal SDE, that is, the probability of empty sampling is low, thereby having higher sampling accuracy.

[0072] The above description is merely an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

[0073] The above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them. Based on the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, and the steps may be implemented in any order. A person skilled in the art should understand that the technical solutions described in the above embodiments may be modified, or some of the technical features may be replaced by equivalents. However, such modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A sampling circuit, characterized in that: A driver chip used to output a pulse width modulation signal to drive the first switch tube to turn on or off, the sampling circuit includes: At least two sampling signal generating branches, each sampling signal generating branch is used to sample a degaussing signal period, and different sampling signal generating branches generate sampling signals based on different positions of the degaussing signal period; a signal selection branch connected to the at least two sampling signal generation branches and the first voltage output by the sampling circuit, and configured to output a sampling signal generated by one of the at least two sampling signal generation branches based on the first voltage; The switch branch is connected to the signal selection branch and inputs a demagnetization signal, and is used to be turned on and output the demagnetization signal when receiving the sampling signal.

2. The sampling circuit according to claim 1, wherein: The sampling circuit further includes: a first filtering branch, connected to the switch branch, and configured to filter the demagnetization signal output by the switch branch; a signal following branch, connected to the first filtering branch, and configured to output a sampling voltage that is the same as the voltage of the filtered demagnetization signal; a signal amplifying branch connected to the signal following branch and inputting a reference voltage, for amplifying the difference between the reference voltage and the sampling voltage and then outputting an amplified signal; The second filtering branch is connected to the signal amplifying branch, and is used to filter the amplified signal and output the first voltage.

3. The sampling circuit according to claim 1 or 2, characterized in that: The at least two sampling signal generating branches include a first sampling signal generating branch, a second sampling signal generating branch, and a third sampling signal generating branch, wherein the first sampling signal generating branch is configured to generate a first sampling signal at a moment after a first preset time period has elapsed from the start of the demagnetization signal period, the second sampling signal generating branch is configured to generate a second sampling signal at a middle moment of the demagnetization signal period, and the third sampling signal generating branch is configured to generate a third sampling signal at a moment 2 / 3 of the demagnetization signal period; The signal selection branch is further used to output the first sampling signal when the first voltage is less than a first preset voltage, and to output the second sampling signal when the first voltage is greater than or equal to the first preset voltage and less than or equal to a second preset voltage, and to output the third sampling signal when the first voltage is greater than the second preset voltage, wherein the first preset voltage is less than the second preset voltage.

4. The sampling circuit according to claim 3, wherein: The signal selection branch includes a first comparator, a second comparator, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate and a selector; The first voltage is input to the non-inverting input of the first comparator, the first preset voltage is input to the inverting input of the first comparator, the output of the first comparator is connected to the input of the first NOT gate, the output of the first NOT gate is connected to the input of the second NOT gate, and the output of the second NOT gate outputs a first selection signal to the selector; The first voltage is input to the non-inverting input of the second comparator, the second preset voltage is input to the inverting input of the second comparator, the output of the second comparator is connected to the input of the third NOT gate, the output of the third NOT gate is connected to the input of the fourth NOT gate, and the output of the fourth NOT gate outputs a second selection signal to the selector; The first input terminal of the selector inputs the first sampling signal, the second input terminal of the selector inputs the second sampling signal, and the third input terminal of the selector inputs the third sampling signal. The first sampling signal is output when the first selection signal is low and the second selection signal is low, the second sampling signal is output when the first selection signal is high and the second selection signal is low, and the third sampling signal is output when the first selection signal is high and the second selection signal is high.

5. The sampling circuit according to claim 1 or 2, characterized in that: The switch branch includes a second switch tube; The first end of the second switch tube is connected to the signal selection branch, the second end of the second switch tube inputs the demagnetization signal, and the third end of the second switch tube is used to output the demagnetization signal.

6. The sampling circuit according to claim 2, wherein: The first filter branch includes a first resistor and a first capacitor, and the second filter branch includes a fourth resistor and a second capacitor; The first resistor and the first capacitor are connected in series between the switch branch and the ground, and a connection point between the first resistor and the first capacitor is connected to the signal follower branch; The fourth resistor and the second capacitor are connected in series between the signal amplifying branch and the ground.

7. The sampling circuit according to claim 2, wherein: The signal follower branch includes an operational amplifier; The non-inverting input terminal of the operational amplifier is connected to the first filtering branch, and the inverting input terminal of the operational amplifier is connected to the output terminal and the signal amplifying branch.

8. The sampling circuit according to claim 2, wherein: The signal amplifying branch includes a second resistor, a third resistor and a third comparator; The second resistor and the third resistor are connected in series between the signal follower branch and the output end of the third comparator. The output end of the third comparator is also connected to the second filter branch. The connection point between the second resistor and the third resistor is connected to the inverting input end of the third comparator. The reference voltage is input to the non-inverting input end of the third comparator.

9. A driver chip, characterized in that: The method comprises the sampling circuit according to any one of claims 1 to 8.

10. A switching power supply, characterized in that: It comprises a first switching tube and the driving chip as claimed in claim 9, wherein the driving chip is used to output a pulse width modulation signal to drive the first switching tube to be turned on or off.

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