Vertical power component and apparatus

Abstract

The description relates to a vertical power component formed in and on a semiconductor substrate doped with a first conductivity type, and an upper side of the semiconductor substrate is coated with a semiconductor layer doped with the first conductivity type. The component comprises: an active region (100A); and first and second sets of first concentric field limiting rings surrounding the active region. Each first ring includes a first semiconductor region doped with a second conductivity type opposite to the first conductivity type, the first semiconductor region extending vertically from an upper side of the semiconductor layer into a thickness of the semiconductor layer; and a second field limiting ring laterally interposed between the first and second sets of first field limiting rings (GR). The second ring includes a second doped semiconductor region of the second conductivity type extending vertically from above the semiconductor layer into the thickness of the semiconductor layer. A width of the second semiconductor region is at least three times greater than a width of the widest first semiconductor region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority of French patent application No. FR 2309013, filed on August 28, 2023, entitled “Composant vertical depuissance”, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] The present description relates generally to electronic devices and more particularly to vertical power components. Background Art

[0004] Vertical power components have been proposed. Among these components, JBS (junction-barrier Schottky) diodes have been particularly proposed. JBS diodes have similar advantages to conventional Schottky diodes, including low on-state voltage drop, low threshold voltage, and low switching losses. In addition, JBS diodes have improved resistance and lower leakage current under current overload conditions compared to conventional Schottky diodes.

[0005] However, existing vertical power components suffer from various drawbacks. More specifically, arcing can occur within these components when they are subjected to high reverse voltages. This arcing causes irreversible degradation of the vertical power component at the point where the arc forms, leading to failure that renders the component at least partially inoperable. Summary of the Invention

[0006] It is desirable to overcome all or some of the disadvantages of existing vertical power components. In particular, it is desirable to prevent arcing in existing vertical power components.

[0007] To this end, one embodiment provides a vertical power component formed in and on a semiconductor substrate doped with a first conductivity type, and coated with a semiconductor layer doped with the first conductivity type on the upper side of the semiconductor substrate, the component comprising:

[0008] active area; and

[0009] a first and a second set of first concentric field limiting rings surrounding the active region, each first ring comprising a first semiconductor region doped with a second conductivity type opposite to the first conductivity type, extending vertically from an upper side of the semiconductor layer into the thickness of the semiconductor layer;

[0010] a second field limiting ring, laterally interposed between the first and second groups of first field limiting rings, the second ring comprising a second doped semiconductor region of a second conductivity type, extending vertically from an upper surface of the semiconductor layer into the thickness of the semiconductor layer; and

[0011] a first insulating region (109) located on top of the entire upper surface of the second doped semiconductor region (305P) and in mechanical contact therewith,

[0012] The width of the second semiconductor region is at least three times greater than the width of the widest first semiconductor region.

[0013] According to one embodiment, the second ring reduces the electric field present near the interface between the first insulating region arranged on and in contact with the upper side of the semiconductor layer and the second insulating region located in the peripheral area of the vertical power component by at least half, for example by at least two thirds.

[0014] According to one embodiment, the second ring enables reducing the electric field present near the interface between the first insulating region arranged on and in contact with the upper side of the semiconductor layer and the mold resin of the encapsulation of the vertical power component by at least half, for example by at least two thirds.

[0015] According to one embodiment, the first group and the second group comprise exactly the same number of first rings.

[0016] According to one embodiment, the first and second field limiting rings are floating guard rings.

[0017] According to one embodiment, the component further comprises at least a third group of first rings, and at least one third field limiting ring interposed between the second group of first rings and the at least one third group of first rings.

[0018] According to one embodiment, the semiconductor layer has a doping level strictly lower than a doping level of the semiconductor substrate.

[0019] According to one embodiment, the component comprises:

[0020] a first conductive electrode formed in the active area and including a conductive region on the semiconductor layer; and

[0021] The second conductive electrode is arranged on a side of the semiconductor substrate opposite to the semiconductor layer.

[0022] According to one embodiment, the semiconductor substrate is made of silicon or silicon carbide.

[0023] According to one embodiment, the first conductivity type is N and the second conductivity type is P.

[0024] According to one embodiment, the component is a JBS diode.

[0025] According to one aspect of the present disclosure, a vertical power component is provided, comprising: a semiconductor substrate doped with a first conductivity type; a semiconductor layer doped with the first conductivity type on the semiconductor substrate; an active area; a first set and a second set of first field limiting rings surrounding the active area, each first field limiting ring comprising a first semiconductor region doped with a second conductivity type opposite to the first conductivity type and extending into the thickness of the semiconductor layer; second field limiting rings laterally inserted between the first set and the second set of first field limiting rings, the second field limiting rings comprising a second semiconductor region doped with the second conductivity type and extending into the thickness of the semiconductor layer; and a first insulating region across the entire surface of the second semiconductor region and in mechanical contact therewith, wherein a width of the second semiconductor region is at least three times greater than a width of the widest first semiconductor region.

[0026] According to one embodiment, the vertical power component further comprises: a second insulating region located in a peripheral region of the vertical power component, wherein the second field limiting ring is configured to reduce an electric field existing near an interface between the first insulating region and the second insulating region by at least half.

[0027] According to one embodiment, the second field limiting ring enables the electric field present near the interface between the first insulating region and the molding resin of the package of the vertical power component to be reduced by at least half.

[0028] According to one embodiment, the first group and the second group include the same number of first field limiting rings.

[0029] According to one embodiment, the first field limiting ring and the second field limiting ring are floating guard rings.

[0030] According to one embodiment, the vertical power component further comprises: at least one third group of first field limiting rings; and at least one third field limiting ring interposed between the second group of first field limiting rings and the at least one third group of first field limiting rings.

[0031] According to one embodiment, the doping level of the semiconductor layer is lower than the doping level of the semiconductor substrate.

[0032] According to one embodiment, the vertical power component further includes: a first conductive electrode formed in the active area and including a conductive region on the semiconductor layer; and a second conductive electrode arranged on a side of the semiconductor substrate opposite to the semiconductor layer.

[0033] According to one embodiment, the semiconductor substrate is made of silicon or silicon carbide.

[0034] According to one embodiment, the first conductivity type is N and the second conductivity type is P.

[0035] According to one embodiment, the vertical power component is a Junction-Barrier Schottky (JBS) diode.

[0036] According to another aspect of the present disclosure, a device is provided, including: a semiconductor substrate having a first conductivity type; a semiconductor layer on the semiconductor substrate, the semiconductor layer having the first conductivity type; and a power component on the semiconductor layer, the power component including an active area and a peripheral area surrounding the active area, the peripheral area including: a first plurality of first semiconductor regions extending into the semiconductor layer, the first semiconductor regions having a second conductivity type; a second semiconductor region extending into the semiconductor layer, the width of the second semiconductor region being greater than each of the widths of the first semiconductor regions; and a second plurality of first semiconductor regions extending into the semiconductor layer, the first plurality of first semiconductor regions being separated from the second plurality of first semiconductor regions by the second semiconductor regions.

[0037] According to an embodiment, the width of the second semiconductor region is at least three times greater than each of the widths of the first semiconductor region.

[0038] According to one embodiment, the device further includes a first insulating region on the semiconductor layer, the first plurality of first semiconductor regions, the second semiconductor region, and the second plurality of first semiconductor regions.

[0039] According to one embodiment, the first insulating region physically contacts the entire surface of the second semiconductor region.

[0040] According to one embodiment, the active region includes a conductive region on the semiconductor layer, and the first insulating region is on the conductive region.

[0041] According to one embodiment, the device further comprises: a second insulating region on the first insulating region and the conductive region.

[0042] According to one embodiment, the semiconductor layer is an epitaxial layer.

[0043] According to another aspect of the present disclosure, a device is provided, comprising: a semiconductor substrate having a first conductivity type; a semiconductor layer on the semiconductor substrate, the semiconductor layer having the first conductivity type; an active region in and on the semiconductor layer; and a peripheral region surrounding the active region, the peripheral region comprising: a first plurality of first semiconductor regions in the semiconductor layer; a second plurality of first semiconductor regions in the semiconductor layer, the first semiconductor regions having a second conductivity type; a second semiconductor region in the semiconductor layer and located between the first plurality of first semiconductor regions and the second plurality of first semiconductor regions, the width of the second semiconductor region being greater than each of the widths of the first semiconductor regions; and a first insulating region on the semiconductor layer, the first plurality of first semiconductor regions, the second plurality of first semiconductor regions, and the second semiconductor region.

[0044] According to one embodiment, each of the first semiconductor region and the second semiconductor region has a thickness smaller than that of the semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0046] Figure 1A and Figure 1B Along the Figure 1A A schematic and partial view of an example of a vertical power component is shown from the top and in section through the plane BB shown in FIG;

[0047] Figure 2 yes Figure 1A and Figure 1B Schematic and partial top view of the peripheral area of the vertical power component shown in;

[0048] Figure 3 is a detailed schematic and partial view of a peripheral area of a vertical power component according to one embodiment; and

[0049] Figure 4 It is an icon Figure 3 Graph showing changes in the electric field and electrostatic potential in the peripheral region of the vertical power component shown in FIG. DETAILED DESCRIPTION

[0050] Similar features are denoted by similar reference numerals in the various figures. In particular, common structural and / or functional features between various embodiments may have the same reference numerals and may have identical structures, sizes, and material properties.

[0051] For clarity, operations and elements useful for understanding the embodiments described herein have been detailed and described. In particular, various applications implementing vertical power components are not described in detail, and the described embodiments are compatible with all or most applications that may utilize one or more vertical power components.

[0052] Unless otherwise specified, when two elements are referred to as being connected together, this means a direct connection without any intermediate elements other than conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0053] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers (such as terms "front", "back", "top", "bottom", "left", "right", etc.), or referring to relative position qualifiers (such as terms "above", "below", "higher", "lower", etc.), or referring to orientation qualifiers (such as "horizontal", "vertical", etc.), the reference is to the orientation shown in the figure.

[0054] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "around" all mean within 10%, and in some cases within 5%.

[0055] In the following description, unless otherwise specified, the qualifiers "insulating" and "conductive" mean electrical insulation and electrical conductivity, respectively.

[0056] Figure 1A is a schematic partial top view illustrating an example of a vertical power component 100 . Figure 1B is the vertical power component 100 along Figure 1A Cross-sectional view of plane BB.

[0057] In the example shown, the vertical power component 100 is a JBS (junction-barrier Schottky) diode including an active area 100A, which corresponds, for example, to an area through which a power signal may flow during component operation. In this example, the active area 100A of the vertical power component 100 is surrounded (flanked) by a peripheral area 100P through which a power signal is not intended to flow during component operation. The active area 100A is, for example, substantially located at the center of the vertical power component 100. The peripheral area 100P of the vertical power component 100 surrounds the active area 100A and, for example, has an annular shape in a top view. The peripheral area 100P is laterally inserted between the active area 100A and the edge of the vertical power component 100. Figure 1AAn example is shown in which the vertical power component 100 has a generally rectangular shape in top view. However, such an example is not limiting, as the vertical power component 100 may have any general shape in variations, such as a square shape, an oval shape, a circular shape, etc.

[0058] In the example shown, the vertical power component 100 is formed in and on a semiconductor substrate 101. The substrate 101 is, for example, a wafer or a piece of a wafer made of a semiconductor material, such as silicon (Si) or silicon carbide (SiC). The semiconductor substrate 101 is doped with a first conductivity type, for example, N-type, and has a conductivity of, for example, between 1*10 17 and 5*10 20 at. / cm 3 The doping level between (N in the case where the first conductivity type is N type) + As an example, the semiconductor substrate 101 has a thickness greater than or equal to approximately 50 μm, the thickness of the semiconductor substrate 101 being selected, for example, to ensure the mechanical strength of the structure of the vertical power component 100 .

[0059] exist Figure 1B , a semiconductor layer 103 is coated on the upper surface of the semiconductor substrate 101 in the direction shown in FIG. The semiconductor layer 103 is made of, for example, the same material as the substrate 101 (for example, silicon or silicon carbide). As an example, the semiconductor layer 103 is an epitaxial layer, that is, formed by epitaxial growth on the upper surface of the semiconductor substrate 101. The semiconductor layer 103 is doped with, for example, a first conductivity type (in this example, N-type). The semiconductor layer 103 has, for example, a doping level strictly lower than the doping level of the semiconductor substrate 101, for example, between 1*10 13 and 5*10 17 at. / cm 3 The semiconductor layer 103 has a doping level and a thickness selected, for example, according to a voltage withstand to be achieved by the vertical power component 100 .

[0060] In the example shown, the vertical power component 100 further includes semiconductor regions 105A, 105I, and 105P, which are formed from the side of the semiconductor layer 103 opposite to the semiconductor substrate 101 (at Figure 1B10 . The semiconductor regions 105A, 105I and 105P extend vertically over the thickness of the semiconductor layer 103 (in the orientation shown in FIG). The semiconductor regions 105A, 105I and 105P have a thickness that is strictly less than the thickness of the semiconductor layer 103. In the example shown, the semiconductor region 105A forms part of the active region 100A, and the semiconductor regions 105I and 105P form part of the peripheral region 100P of the vertical power component 100, with the region 105I being laterally inserted between the regions 105A and 105P. The semiconductor regions 105A, 105I and 105P are doped with a second conductivity type (in this example, P-type) that is opposite to the first conductivity type. As an example, the semiconductor regions 105A, 105I and 105P have a thickness between 1*10 17 and 5*10 20 at. / cm 3 The maximum doping level between (in the case where the second conductivity type is P type is P + Doping). The semiconductor regions 105A, 105I, and 105P are formed on the side of the semiconductor layer 103 opposite to the semiconductor substrate 101 by, for example, an ion implantation step and then an annealing step. Figure 1A In the embodiment, the semiconductor regions 105A and 105P are not shown in detail, but some semiconductor regions 105P (in this case, three semiconductor regions 105P) are shown to avoid overloading the drawing. Moreover, the number of semiconductor regions 105A and 105P may be the same as that of the semiconductor regions 105A and 105P. Figure 1A and 1B As an example, the number of semiconductor regions 105P is between five and three hundred, for example between ten and fifty, for example equal to approximately fifteen.

[0061] In the illustrated example, semiconductor regions 105P and 105I have concentric annular shapes in top view, with each semiconductor region 105P, 105I surrounding all of semiconductor region 105A. As an example, each semiconductor region 105P, 105I has a rectangular outline with rounded corners. In top view, semiconductor regions 105A, for example, form strips that are parallel to one another and extend laterally in a direction perpendicular to plane BB. In alternative embodiments, semiconductor regions 105A may form a grid in top view, comprising first strips that are parallel to one another and perpendicular to plane BB, and second strips that are parallel to one another and perpendicular to the first strips, a hexagonal shape, an elliptical or circular shape, discontinuous strips, or the like.

[0062] In the illustrated example, vertical power component 100 further includes a conductive region 107, which is disposed on and in contact with a portion of the upper surface of semiconductor layer 103. This portion of semiconductor layer 103 forms part of active region 100A of component 100, and conductive region 107 contacts the upper surfaces of semiconductor regions 105A and 105I. Conductive region 107, for example, defines active region 100A of component 100. Conductive region 107 is, for example, made of a metal stack, such as aluminum (Al). In this case, region 107 forms a Schottky contact (metal-semiconductor contact) with semiconductor layer 103.

[0063] In the illustrated example, insulating region 109 is disposed over and in contact with a portion of the upper surface of semiconductor layer 103, which is part of peripheral region 100P of vertical power component 100. Insulating region 109 contacts the upper surface of semiconductor region 105P and a portion of semiconductor region 105I. Insulating region 109, for example, has an annular shape, enclosing active region 100A of component 100, in a top view. In the illustrated example, conductive region 107 extends laterally over and in contact with a portion of the upper surface of insulating region 109. Insulating region 109, for example, serves as a passivation layer for vertical power component 100. By way of example, insulating region 109 is made of an oxide (e.g., silicon dioxide).

[0064] In the illustrated example, vertical power component 100 further includes another insulating region 113 located in peripheral region 100P of component 100, which is arranged on and in contact with a portion of the upper surface of conductive region 107 and in contact with the upper surface of insulating region 109. Insulating region 113 has, for example, a ring shape in a top view that surrounds active region 100A of component 100. Insulating region 113 forms, for example, a passivation layer of vertical power component 100. By way of example, insulating region 113 is made of an organic material, for example, a polymer such as polybutylene oxide (PBO) or polyimide.

[0065] As a variant, the insulating region 113 may be omitted, in the case of a molded package assembly, the insulating region 109 being in contact with the molding resin.

[0066] The vertical power component 100 further includes a conductive layer disposed on a surface of the semiconductor substrate 101 opposite to the semiconductor layer 103 (at Figure 1B In the orientation shown in FIG, , the conductive layer is coated on one side of the lower side of the semiconductor substrate 101. This conductive layer is, for example, part of another conductive electrode (e.g., a cathode) of the vertical power component 100. The conductive layer coating the lower side of the substrate 101 is, for example, made of the same material as the conductive region 107 (e.g., a metal (e.g., nickel) or a metal alloy).

[0067] Also, although not shown, the vertical power component 100 may be surrounded by a package (eg, a package made of a polymer resin molded around the structure of the vertical power component 100 ).

[0068] Figure 2 yes Figure 1A and Figure 1B Schematic and partially detailed view of a peripheral area 100P of a vertical power component 100 is shown in FIG. Figure 2 More precisely with Figure 1B 1 corresponds to a detailed cross-sectional view of the region 150 defined by the dotted box in FIG.

[0069] exist Figure 2 In the example shown in , the semiconductor regions 105P have exactly the same size within the manufacturing dispersion and are substantially regularly spaced. However, this example is not restrictive, and as a variant, the semiconductor regions 105P can have different sizes and / or spacings. In this case, the semiconductor regions 105P have, for example, exactly the same width and a variable pitch, or a variable width and a constant pitch. The semiconductor regions 105P of the peripheral region 100P of the vertical power component 100 make it possible to extend the depletion region of the main junction formed at the interface between the semiconductor layer 103 and the conductive region 105I over a distance suitable for ensuring the voltage tolerance of the component 100.

[0070] In the illustrated example, the semiconductor regions 105P are each part of a field limiting ring (GR) (e.g., a floating guard ring (FGR)), each GR ring including a single semiconductor region 105P. As an example, the field limiting rings GR have a pitch and a width sized to achieve a substantially constant electric field near the interface between the insulating regions 109 and 113 when the vertical power component 100 is subjected to a nominal voltage applied between its conductive electrodes. As an example, the absolute value of the nominal voltage is greater than or equal to 350 V, for example, between 600 V and 15 kV.

[0071] In the example shown, the field limiting rings GR of the vertical power component 100 are divided into three sets (or groups) S1, S2, and S3 of rings GR, each set (or group) including a substantially equal number of rings GR and, therefore, a substantially equal number of semiconductor regions 105P. In the example shown, group S1 includes rings GR whose semiconductor regions 105P are closest to the active region 100A of the vertical power component 100, group S3 includes rings GR whose semiconductor regions 105P are farthest from the active region 100A, and group S2 includes rings GR whose semiconductor regions 105P are laterally inserted between the semiconductor regions of group S1 and the semiconductor regions of group S3. Figure 2 , with the top of the semiconductor substrate 101 and Figure 1AAn axis parallel to the plane BB shown in FIG. 1 and oriented from the active region 100A toward the peripheral region 100P of the vertical power component 100 enables identification of the distance (D) separating each GR or each semiconductor region 105P from the active region 100A.

[0072] A disadvantage of the vertical power component 100 is due to the fact that delamination or detachment can occur, in particular, between the package and the vertical power component 100, or between the insulating region 113 and the insulating region 109. In the case of a vertical power component 100 without the insulating region 113, delamination can occur between the insulating region 109 and the molded resin of the package. This delamination leads to the formation of a gaseous layer (e.g., an air layer) in which arcs can form, for example, when the vertical power component is subjected to a high reverse voltage. The arcs cause irreversible damage in the vertical power component 100, leading to failure, which renders the vertical power component 100 at least partially inoperable.

[0073] Figure 3 is a schematic and partially detailed view of a peripheral area of a vertical power component 300 according to one embodiment. In the example shown, the vertical power component 300 is a JBS diode. Figure 3 The vertical power component 300 shown in FIG. 1 includes Figure 1A 、 Figure 1B and Figure 2 Such common elements will not be discussed in detail below. Figure 3 The vertical power component 300 shown in FIG. Figure 1A 、 Figure 1B and Figure 2 The vertical power component 100 shown in FIG. 1 differs in that the component 300 includes a peripheral region 300P similar to the peripheral region 100P of the component 100, but in addition to the groups S1, S2 and S3 of field limiting rings GR including the semiconductor region 105P, further field limiting rings (LGRs), e.g., floating guard rings, each including a semiconductor region 305P.

[0074] The semiconductor regions 105P and 305P are, for example, concentric, and each semiconductor region 305P is laterally interposed between two groups of semiconductor regions 105P. In other words, each field limiting ring LGR is laterally interposed between two groups (S1 and S2, or S2 and S3) of field limiting rings GR. In the example shown, the field limiting rings LGR form two gaps or spaces G1 and G2, separating group S1 from group S2 and group S2 from group S3, respectively.

[0075] exist Figure 3 In the example shown in FIG, each semiconductor region 305P is formed from a surface of the semiconductor layer 103 opposite to the semiconductor substrate 101 (at Figure 310 , the upper surface of the layer 103 extends vertically into the thickness of the semiconductor layer 103. The semiconductor region 305P has a thickness that is strictly less than the thickness of the semiconductor layer 103, for example, a thickness that is substantially equal to the thickness of the semiconductor region 105P. In the example shown, the semiconductor region 305P forms part of the peripheral region 300P of the vertical power component 300. The semiconductor region 305P is doped with a second conductivity type (in this example, P type). As an example, the 305P semiconductor region has a thickness between 1*10 17 and 5*10 20 at. / cm3 doping level (P + The semiconductor region 305P is formed on the side of the semiconductor layer 103 opposite to the semiconductor substrate 101 by, for example, an ion implantation step and a subsequent annealing step. As an example, the semiconductor regions 105P and 305P are formed simultaneously.

[0076] According to one embodiment, each semiconductor region 305P has a width that is strictly greater than the width of each semiconductor region 105P. In other words, the field limiting ring LGR has a width that is strictly greater than the width of the field limiting ring GR. As an example, the width of each 305P semiconductor region is at least three times greater than the width of the widest 105P semiconductor region. Figure 3 In the example shown in , the semiconductor regions 305P have exactly the same size within the manufacturing dispersion.

[0077] According to one embodiment, the insulating region 109 is located on top of and in mechanical contact with the entire upper surface of each semiconductor region 305P. In particular, the vertical power component 300 does not have any electrically conductive elements in contact with the upper surface of the semiconductor region 305P. In the example shown, the insulating region 109 is also located on top of and in mechanical contact with the entire upper surface of each semiconductor region 105P. In particular, the vertical power component 300 does not have any electrically conductive elements in contact with the upper surface of the semiconductor region 105P.

[0078] As an example, the number of field-limiting rings LGR or the number of groups of field-limiting rings GR is selected based on the target voltage tolerance of vertical power component 300. Furthermore, the number of field-limiting rings GR in each group S1, S2, and S3 is selected, for example, based on the minimum voltage at which arcing occurs in the event of delamination or detachment in vertical power component 300. For example, the minimum voltage is given by Paschen's law as applied to vertical power component 300. The geometry, number, and distribution of the field-limiting rings GR are defined so that the electric field near the interface between insulating regions 109 and 113 is substantially constant across groups S1, S2, and S3.

[0079] One advantage of vertical power component 300 is that the presence of ring LGR including semiconductor region 305P reduces the intensity of the electric field present near the interface between insulating regions 109 and 113. This advantageously prevents or limits the risk of arcing in the event of delamination or detachment in vertical power component 300.

[0080] Figure 4 is a graph 400, which illustrates the Figure 3 The changes in the electric field E and electrostatic potential (V) in the peripheral area 300P of the vertical power component 300 shown in FIG. 3 are shown in FIG. 4 , where the electric field E is expressed in volts per centimeter (V.cm). -1 ), and the electrostatic potential (V) is expressed in volts (V). For comparison, the graph 400 also illustrates the changes in the electric field E and the electrostatic potential V in the peripheral region 100P of the vertical power component 100 by dashed curves 405 and 407, respectively. The graph 400 more accurately represents the changes in the electric field E in the insulating region 109 of the vertical power component 100 or 300 (for example, near the interface with the insulating region 113), and the changes in the electrostatic potential V in the semiconductor material near the interface with the insulating region 109. This change is expressed as a function of the distance D.

[0081] In the example shown, the curve 401 indicates that directly below each group S1 , S2 , S3 of the rings GR, the electric field E is substantially constant and equal to approximately 2*10 5 V.cm -1 , and in each gap G1, G2 located directly below the LGR ring, the electric field E is sharply reduced, for example, by a factor of 2 or 3. In other words, the field limiting ring LGR reduces the electric field E by half, for example, by at least two-thirds, compared to the constant field region. For comparison, the curve 405 indicates that in the case of the vertical power component 100, the electric field E along the distance axis D is substantially constant and equal to approximately 2*10 5 V.cm -1 .

[0082] exist Figure 4In the example shown in FIG, curve 403 indicates that the electrostatic potential V increases by a value V1 between the ends of group S1 of loops GR, by a value V2 between the ends of group S2 of loops GR, and by a value V3 between the ends of group S3 of loops GR. For example, each of values V1, V2, and V3 is strictly below a minimum voltage, above which arcing may occur in vertical power component 300 in the event of delamination or detachment. By way of example, each of values V1, V2, and V3 is below 280 V, for example, around 250 V, and the sum of values V1, V2, and V3 is, for example, approximately 750 V. Furthermore, in the example shown, the electrostatic potential V is substantially constant across gaps G1 and G2, with curve 403 including a plateau corresponding to the position of loop LGR. In comparison, curve 407 lacks such a plateau.

[0083] like Figure 4 As shown in the graph 400 in FIG, an advantage of the vertical power component 300 lies in the fact that the presence of the field limiting rings LGR, which are laterally inserted between the groups S1, S2 and S3 of field limiting rings GR, creates a weak electric field region, which prevents the formation of arcs that would adversely affect the operation of the component 300 in the event of delamination or detachment.

[0084] Various embodiments and variations have been described. It will be understood by those skilled in the art that certain features of these embodiments may be combined, and that other variations will readily occur to those skilled in the art. In particular, the embodiments are not limited to the case where the vertical power component 300 is a JBS diode, but are more generally applicable to any type of vertical power component including a field limiting ring, such as a bipolar diode, a MOS (metal oxide semiconductor) transistor, a thyristor, etc., for example, to any type of vertical power component that may be subjected to a voltage greater than 350V between its conductive electrodes. Based on the above indications, it is within the scope of those skilled in the art to apply the embodiments to such components.

[0085] Finally, based on the functional description provided above, actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art. In particular, those skilled in the art will be able to adjust the number of field-limiting ring GR groups, the number of field-limiting rings GR in each group of field-limiting rings GR, and the lateral size of each field-limiting ring LGR based on the application. Furthermore, the embodiments are not limited to the materials and dimensions described in the examples.

[0086] A vertical power component (300) can be formed in and on a semiconductor substrate (101) that is doped with a first conductivity type and coated on its upper side with a semiconductor layer (103) doped with the first conductivity type. The component (300) can be summarized as comprising: an active area (100A); and first and second groups (S1, S2) of first concentric field limiting rings (GR) surrounding the active area (100A), each first ring (GR) comprising a first semiconductor region (105P) doped with a second conductivity type opposite to the first conductivity type, extending vertically from the upper side of the semiconductor layer (103) into the thickness of the semiconductor layer (103); and - a second field limiting ring (LGR) that is laterally inserted between the first group and the second group (S1, S2) between the first field limiting ring (GR), the second ring (LGR) includes a second doped semiconductor region (305P) of the second conductivity type, which extends vertically from the upper side of the semiconductor layer (103) into the thickness of the semiconductor layer (103); and a first insulating region (109) which is located on top of the entire upper side of the second doped semiconductor region (305P) and is in mechanical contact with it, wherein the width of the second semiconductor region (305P) is at least three times the width of the widest first semiconductor region (105P).

[0087] The second ring (LGR) reduces the electric field (E) present near the interface between the first insulating region (109) arranged on the upper surface of the semiconductor layer (103) and in contact therewith and the second insulating region (113) located in the peripheral region (100P) of the vertical power component (300) by at least half, preferably by at least two thirds.

[0088] The second ring (LGR) enables the electric field (E) present near the interface between the first insulating region (109) arranged on the upper side of the semiconductor layer (103) and in contact therewith and the molded resin of the package of the vertical power component (300) to be reduced by at least half, preferably by at least two thirds.

[0089] The first and second groups (S1, S2) include exactly the same number of first rings (GR).

[0090] The first and second field limiting rings (GR, LGR) are floating guard rings.

[0091] The component (300) further comprises at least a third group (S3) of first rings (GR), and at least one third field limiting ring (LGR) interposed between the second group (S2) of first rings and the at least one third group (S3) of first rings.

[0092] The semiconductor layer (103) has a doping level that is strictly lower than the doping level of the semiconductor substrate (101).

[0093] The component (300) may include: a first conductive electrode formed in the active area (100A) and including a conductive region (107) located on the semiconductor layer (103); and a second conductive electrode arranged on a side of the semiconductor substrate (101) opposite to the semiconductor layer.

[0094] The semiconductor substrate (101) is made of silicon or silicon carbide.

[0095] The first conductivity type is N, and the second conductivity type is P.

[0096] The component is a JBS diode.

[0097] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. Generally speaking, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to which such claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A vertical power component, characterized in that include: a semiconductor substrate doped with a first conductivity type; a semiconductor layer doped with a first conductivity type, on a semiconductor substrate; active area; a first and a second set of first field limiting rings surrounding the active region, each first field limiting ring comprising a first semiconductor region doped with a second conductivity type opposite to the first conductivity type and extending into the thickness of the semiconductor layer; a second field limiting ring, laterally interposed between the first and second groups of first field limiting rings, the second field limiting ring comprising a second semiconductor region doped with a second conductivity type and extending into the thickness of the semiconductor layer; as well as a first insulating region extending over the entire surface of the second semiconductor region and in mechanical contact therewith, The width of the second semiconductor region is at least three times greater than the width of the widest first semiconductor region.

2. The vertical power component according to claim 1, characterized in that Also includes: a second insulating region located in a peripheral region of the vertical power component, The second field limiting ring is configured to reduce an electric field existing near an interface between the first insulating region and the second insulating region by at least half.

3. The vertical power component according to claim 1, characterized in that The second field limiting ring enables the electric field present near the interface between the first insulating region and the molding resin of the package of the vertical power component to be reduced by at least half.

4. The vertical power component according to claim 1, characterized in that The first group and the second group include the same number of first field limiting rings.

5. The vertical power component according to claim 1, characterized in that The first field limiting ring and the second field limiting ring are floating guard rings.

6. The vertical power component according to claim 1, wherein Also includes: at least one third set of first field limiting rings; as well as At least one third field limiting ring is inserted between the second group of first field limiting rings and the at least one third group of first field limiting rings.

7. The vertical power component according to claim 1, characterized in that The doping level of the semiconductor layer is lower than the doping level of the semiconductor substrate.

8. The vertical power component according to claim 1, wherein Also includes: a first conductive electrode formed in the active area and comprising a conductive region on the semiconductor layer; as well as The second conductive electrode is arranged on a side of the semiconductor substrate opposite to the semiconductor layer.

9. The vertical power component according to claim 1, characterized in that The semiconductor substrate is made of silicon or silicon carbide.

10. The vertical power component according to claim 1, characterized in that Wherein the first conductivity type is N and the second conductivity type is P.

11. The vertical power component according to claim 1, characterized in that The vertical power component is a junction-barrier Schottky JBS diode.

12. A device, characterized in that include: a semiconductor substrate having a first conductivity type; a semiconductor layer on the semiconductor substrate, the semiconductor layer having a first conductivity type; as well as A power component on a semiconductor layer, the power component comprising an active area and a peripheral area surrounding the active area, the peripheral area comprising: a first plurality of first semiconductor regions extending into the semiconductor layer, the first semiconductor regions having a second conductivity type; a second semiconductor region extending into the semiconductor layer, the second semiconductor region having a width greater than each of the widths of the first semiconductor region; and A second plurality of first semiconductor regions extends into the semiconductor layer, the first plurality of first semiconductor regions being separated from the second plurality of first semiconductor regions by second semiconductor regions.

13. The device according to claim 12, characterized in that Wherein a width of the second semiconductor region is at least three times greater than each of the widths of the first semiconductor region.

14. The device according to claim 12, characterized in that Also includes: A first insulating region is on the semiconductor layer, the first plurality of first semiconductor regions, the second semiconductor region, and the second plurality of first semiconductor regions.

15. The device according to claim 14, characterized in that The first insulating region physically contacts the entire surface of the second semiconductor region.

16. The device according to claim 14, characterized in that The active region includes a conductive region on the semiconductor layer, and the first insulating region is on the conductive region.

17. The device according to claim 16, characterized in that Also includes: A second insulating region is located on the first insulating region and the conductive region.

18. The device according to claim 12, characterized in that The semiconductor layer is an epitaxial layer.

19. A device, characterized in that include: a semiconductor substrate having a first conductivity type; a semiconductor layer on the semiconductor substrate, the semiconductor layer having a first conductivity type; active regions in and on the semiconductor layer; as well as A peripheral region surrounding the active area, the peripheral region comprising: a first plurality of first semiconductor regions in the semiconductor layer; a second plurality of first semiconductor regions in the semiconductor layer, the first semiconductor regions having a second conductivity type; a second semiconductor region in the semiconductor layer and between the first plurality of first semiconductor regions and the second plurality of first semiconductor regions, the second semiconductor region having a width greater than each of the widths of the first semiconductor regions; and The first insulating region is on the semiconductor layer, the first plurality of first semiconductor regions, the second plurality of first semiconductor regions, and the second semiconductor region.

20. The device according to claim 19, characterized in that Each of the first semiconductor region and the second semiconductor region has a thickness smaller than that of the semiconductor layer.

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