Lithium battery parallel protection plate

Abstract

The utility model belongs to the technical field of lithium batteries, and particularly relates to a lithium battery parallel protection plate. Comprising a pulse modulation circuit, a gate drive circuit, a linear voltage stabilizing circuit and a first optocoupler circuit, the linear voltage stabilizing circuit is connected with the pulse modulation circuit and the gate driving circuit, the gate driving circuit is connected with the pulse modulation circuit, the first optocoupler circuit is connected with the pulse modulation circuit, a working power supply interface is arranged in the linear voltage stabilizing circuit, and a main circuit output interface is arranged in the gate driving circuit. According to the scheme, the problem that the adaptation range of the chip adaptation circuit is small when the current of the chip adjustment circuit is added into the current modulation circuit connected in series on the parallel branch of the lithium batteries under the problem that the lithium batteries are grouped in parallel to form circulating current can be solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of lithium batteries, and specifically relates to a parallel protection board for lithium batteries. Background Art

[0002] With the advancement of science and technology, lithium batteries have become mainstream. As an energy storage device, a lithium battery pack typically consists of single cells or modules, electronic components, a battery box, and interfaces with external systems. In practical applications, the entire lithium battery pack is usually composed of several lithium battery modules. A lithium battery module is the smallest grouping of single cells electrically connected physically and circuitry to form a battery pack or system, and can be replaced as a single unit. However, as the demand for charging power continues to increase, the capacity of single cells has limitations. Therefore, more single lithium battery modules are often needed to meet the growing charging demand.

[0003] At present, the common method for paralleling lithium batteries is to use the equipotential parallel method. The equipotential parallel method requires the same voltage for paralleling, which has great defects in actual use. Its defects include: (1) The voltage inconsistency caused by the storage of lithium battery packs. After a period of storage, the voltage of lithium batteries will drop. The voltage drop is affected by many factors such as the storage environment, the degree of wear and tear, and the structure of the battery itself. Even the same type of lithium battery in the same storage environment will have voltage inconsistencies after being stored for the same period of time. (2) When lithium batteries are stored, lithium batteries with different voltages are mixed together, resulting in inconsistent voltages between lithium batteries during operation. If lithium batteries or lithium battery packs with inconsistent voltages are directly paralleled into a battery pack, the voltage difference after paralleling will form a circulation, thereby burning the battery and even causing a fire accident, endangering property and personal safety.

[0004] In order to solve the circulating current problem caused by inconsistent voltage when lithium batteries are connected in parallel, the existing technology usually adopts the method of connecting a current modulation circuit in series with the parallel branches of the lithium batteries. Although this method adjusts the current in the parallel branches and achieves the purpose of solving the circulating current problem, this method is not applicable. After replacing the parallel lithium batteries, the series current modulation circuit needs to be readjusted according to the conditions of the replaced lithium batteries.

[0005] In order to expand the application scope of current modulation circuits, existing technologies have also proposed adding a chip to the series current modulation circuit to adjust the current. This method requires the use of an adapter circuit to connect the chip to the current modulation circuit, but there are too few adapter circuits in the existing technology. Therefore, there is an urgent need for a lithium battery parallel protection board that can solve the problem of circulating current in lithium batteries and add a chip to the current modulation circuit in series on the parallel branches of lithium batteries to adjust the circuit current. Utility Model Content

[0006] The purpose of this solution is to provide a lithium battery parallel protection board to solve the problem of circulating current formed by lithium batteries in parallel. When the chip adjustment circuit current is added to the current modulation circuit in series on the lithium battery parallel branch, the chip adaptation circuit has a small adaptation range.

[0007] In order to achieve the above-mentioned purpose, the technical solution of the present utility model is implemented in the following manner:

[0008] A lithium battery parallel protection board includes: a pulse modulation circuit, a gate drive circuit, a linear voltage stabilization circuit and a first optocoupler circuit; the linear voltage stabilization circuit is connected to the pulse modulation circuit and the gate drive circuit, the gate drive circuit is connected to the pulse modulation circuit, the first optocoupler circuit is connected to the pulse modulation circuit, the linear voltage stabilization circuit is provided with a working power supply interface, and the gate drive circuit is provided with a total circuit output interface.

[0009] Compared with the existing technology, the present invention has the following principles and advantages:

[0010] The utility model divides the circuit into four different functional modules, implements these four functional modules separately, and finally combines and connects them together. This method can reduce the coupling between circuits. When encountering different adaptation requirements, the adaptation range of the utility model can be increased by adding an optocoupler circuit; at the same time, the pulse modulation circuit, gate drive circuit and linear voltage stabilization circuit provided by the utility model provide a more stable and safer modulation current for the chip-regulated current modulation circuit through a combination of multiple MOS tubes, multiple grounding settings, and a variety of high-efficiency circuit connection combinations.

[0011] Furthermore, the linear voltage regulator circuit is provided with a linear voltage regulator U3, the Vin pin of the linear voltage regulator U3 is set to U3-2, the U3-2 is a working power supply interface, the Out pin of the linear voltage regulator U3 is set to U3-3, the GND pin of the linear voltage regulator U3 is set to U3-1, the linear voltage regulator circuit is provided with a first grounding point, and the U3-1 pin of the linear voltage regulator U3 is connected to the first grounding point; the linear voltage regulator circuit is further provided with a capacitor C3, one end of the capacitor C3 is connected to the U3-3 pin of the linear voltage regulator U3, and the other end of the capacitor C3 is connected to the U3-1 pin of the linear voltage regulator U3; the linear voltage regulator U3 is further provided with resistors R5, R6, R7, R8, R9, and R10, the linear voltage regulator U3 is provided with MOS tubes Q1 and Q2, and the linear voltage regulator U3 is provided with diodes D3 and D2; One end of the resistor R5 is connected to the U3-3 pin of the linear regulator U3. The other end of the resistor R5 is connected to the gate of the MOS transistor Q1 and one end of the resistor R6. The source of the MOS transistor Q1 is connected to the U3-3 pin of the linear regulator U3. The drain of the MOS transistor Q1 is set as the first point. The other end of the resistor R6 is connected to the anode of the diode D2. The diodes D2 and D3 are connected in parallel, and the cathode of the parallel connection is set as the second point. The anode of the diode D3 is connected to one end of the resistor R7. The other end of the resistor R7 is connected to the gate of the MOS transistor Q2 and one end of the resistor R8. The other end of the resistor R8 is connected to the first point. The source of the MOS transistor Q2 is connected to the first point. The drain of the MOS transistor Q2 is connected to one end of the resistor R10. The other end of the resistor R10 is set as the fourth point. One end of the resistor R9 is connected to the fourth point. The other end of the resistor R9 is connected to the first ground point.

[0012] Furthermore, the gate drive circuit is provided with a gate drive chip U2, the GND pin in the gate drive chip U2 is set to the U2-3 pin, and the U2-3 pin of the gate drive chip U2 is connected to the first grounding point; the gate drive circuit is provided with resistors R12 and R13, the gate drive circuit is provided with diodes D4 and D6, the INA pin and INB pin in the gate drive chip U2 are set to U2-2 and U2-4 respectively, the U2-2 pin of the gate drive chip U2 is connected to the U2-4 pin of the gate drive chip U2, the cathode of the diode D6 is connected to the U2-4 pin of the gate drive chip U2, and the anode of the diode D6 is connected to the diode The cathode of D4, the anode of the diode D4 is set as the fifth point. The gate drive circuit is provided with a MOS transistor Q3, the gate of the MOS transistor Q3 is connected to the fifth point, the source of the MOS transistor Q3 is connected to the cathode of the diode D4, the drain of the MOS transistor Q3 is connected to one end of the resistor R12, and the other end of the resistor R12 is connected to the fifth point. The gate drive circuit is further provided with a capacitor C5, one end of the capacitor C5 is connected to the drain of the MOS transistor Q3, and the other end of the capacitor C5 is connected to the U2-4 pin of the gate drive chip U2. One end of the resistor R13 is connected to the drain of the MOS transistor Q3, and the other end of the resistor R13 is connected to the U2-4 pin of the gate drive chip U2.

[0013] The VDD pin in U2 is set to U2-6, and a resistor R16 is provided in the gate drive circuit. One end of the resistor R16 is connected to the U2-6 pin of the gate drive chip U2, and the other end of the resistor R16 is set to the sixth point; the OUTA and OUTB pins in the gate drive chip U2 are set to U2-7 and U2-5 respectively, and the gate drive circuit is further provided with resistors R20, R21, R22, R23 and R33, R34. The gate drive circuit is provided with diodes D8 and D7, and the gate drive circuit is provided with MOS tubes Q7 and Q8; the resistor R20 is connected in series with the diode D8 and in parallel with the resistor R21 to form a local circuit one, the positive electrode of the local circuit one is connected to the U2-5 pin of the gate drive chip U2, and the negative electrode is connected to one end of the resistor R33, and the negative electrode of the local circuit one is also connected to the gate of the MOS tube Q7; the resistor R22 is connected in series with the diode D7 and in parallel Resistor R23 forms a local circuit 2, the positive electrode of the local circuit 2 is connected to the U2-7 pin of the gate drive chip U2, and the negative electrode is connected to one end of the resistor R34. The negative electrode of the local circuit 2 is also connected to the gate of the MOS transistor Q8; the other end of the resistor R33 is set to the seventh point, the other end of the resistor R34 is connected to the seventh point, and the source of the MOS transistor Q7 and the source of the MOS transistor Q8 are connected to the seventh point; the gate drive circuit is provided with an inductor L1, one end of the inductor L1 is set to L1-2, and the other end is set to L1-1, and the drain of the MOS transistor Q7 and the drain of the MOS transistor Q8 are connected to the L1-2 end of the inductor L1; the gate drive circuit is also provided with a resistor R30 and a capacitor C9, one end of the resistor R30 is connected to the L1-2 end of the inductor L1, and the other end of the resistor R30 is connected to one end of the capacitor C9. The gate drive circuit is provided with an interface MIDMOS, and the other end of the capacitor C9 is connected to the MID MOS, the MID MOS is the total circuit output interface, the L1-1 end of the inductor L1 is connected to the MID MOS; the gate drive circuit is also provided with electrolytic capacitors CAP2, CAP3, CAP4 and CAP5, the electrolytic capacitor CAP2 and the electrolytic capacitor CAP5 are connected in series and the positive poles are connected, the electrolytic capacitor CAP3 and the electrolytic capacitor CAP4 are connected in series and the positive poles are connected, the negative pole of the electrolytic capacitor CAP2 is set to the eighth point, the negative pole of the electrolytic capacitor CAP3 is connected to the eighth point, the negative pole of the electrolytic capacitor CAP4 and the negative pole of the electrolytic capacitor CAP5 are connected to the MID MOS.

[0014] Furthermore, the pulse modulation circuit is provided with a PWM pulse width modulation control chip U1, a second grounding point is provided in the pulse modulation circuit, resistors R32, R31, and R2 are provided in the pulse modulation circuit, capacitors C11 and C13 are provided in the pulse modulation circuit, the 1IN+ pin of the PWM pulse width modulation control chip U1 is set to U1-1, the 2IN+ pin of the PWM pulse width modulation control chip U1 is set to U1-16, the C11 and the resistor R32 are connected in parallel, and the positive pole of the parallel circuit is connected to the U1-1 pin of the PWM pulse width modulation control chip U1, and the negative pole of the parallel circuit is connected to the seventh point; the capacitor C13 and the resistor R31 are connected in parallel, and the positive pole of the parallel circuit is connected to the U1-16 pin of the PWM pulse width modulation control chip U1, and the negative pole of the parallel circuit is connected to the eighth point; one end of the resistor R2 is connected to the seventh point, and the other end is connected to the eighth point; the second grounding point is connected to the eighth point.

[0015] The pulse modulation circuit is provided with capacitors C9, C12, C10, and C8, and the pulse modulation circuit is provided with resistors RF51K, R29, R28, R27, R24, R19, and R18. The 1IN- pin in the PWM pulse width modulation control chip U1 is set to U1-2, the FEEDBACK pin in the PWM pulse width modulation control chip U1 is set to U1-3, the 2IN- pin in the PWM pulse width modulation control chip U1 is set to U1-15, the DTC pin in the PWM pulse width modulation control chip U1 is set to U1-4, and the REF pin in the PWM pulse width modulation control chip U1 is set to U1-14. One end of the capacitor C9 is connected to the PWM pulse width modulation The U1-3 pin of the PWM pulse width modulation control chip U1 is connected to the U1-15 pin of the PWM pulse width modulation control chip U1. One end of the resistor RF51K is connected to the U1-3 pin of the PWM pulse width modulation control chip U1. The other end of the resistor RF51K is connected to the U1-15 pin of the PWM pulse width modulation control chip U1. One end of the capacitor C12 is connected to the U1-15 pin of the PWM pulse width modulation control chip U1. The other end of the capacitor C12 is connected to one end of the capacitor C10. The other end of the capacitor C10 is connected to the U1-2 pin of the PWM pulse width modulation control chip U1. One end of the resistor R29 is connected to the U1-2 pin of the PWM pulse width modulation control chip U1. The other end of R29 is connected to the second grounding point, one end of the resistor R24 is connected to the U1-14 pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R24 is connected to the U1-2 pin of the PWM pulse width modulation control chip U1. The resistor R19 is connected in parallel with the resistor R24, one end of the resistor R19 is connected to the U1-14 pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R19 is connected to the U1-15 pin of the PWM pulse width modulation control chip U1. The resistor R18 is connected in parallel with the resistor R19, one end of the resistor R18 is connected to the U1-14 pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R18 is connected to the U1-2 pin of the PWM pulse width modulation control chip U1. -4 pin, the capacitor C8 and the resistor R18 are connected in parallel, one end of the capacitor C8 is connected to the U1-14 pin of the PWM pulse width modulation control chip U1, and the other end of the capacitor C8 is connected to the U1-4 pin of the PWM pulse width modulation control chip U1, one end of the resistor R28 is connected to the U1-15 pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R28 is connected to the second grounding point. A MOS transistor Q6 is provided in the pulse modulation circuit, one end of the resistor R27 is connected to the U1-4 pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R27 is connected to the drain of the MOS transistor Q6, the source of the MOS transistor Q6 is connected to the second grounding point, and the gate of the MOS transistor Q6 is connected to the fourth point.

[0016] The pulse modulation circuit is provided with resistors R25, R26 and R17, and a MOS transistor Q5 is provided in the pulse modulation circuit. One end of the resistor R17 is set to the third point, the other end of the resistor R17 is connected to the gate of the MOS transistor Q5, the source of the MOS transistor Q5 is connected to the second grounding point, the drain of the MOS transistor Q5 is connected to one end of the resistor R26, the other end of the resistor R26 is connected to the U1-2 pin of the PWM pulse width modulation control chip U1, one end of the resistor R25 is connected to the gate of the MOS transistor Q5, and the other end of the resistor R25 is connected to the source of the MOS transistor Q5.

[0017] The pulse modulation circuit is provided with a fuse F, one end of which is set as F-1 and the other end is set as F-2. The F-1 end of the fuse F is connected to the second grounding point, and the F-1 end of the fuse F is the negative electrode interface of the working power supply.

[0018] The pulse modulation circuit is provided with a diode D5, and the pulse modulation circuit is provided with capacitors C6 and C7. The diode D5, capacitor C6 and capacitor C7 are connected in parallel, and the negative electrode of the parallel circuit is connected to the sixth point and the positive electrode is connected to the first ground point; the capacitor C1 pin and the capacitor C2 pin in the PWM pulse width modulation control chip U1 are connected, and the capacitor C1 pin is connected to the sixth point.

[0019] The U1-9 and U1-10 pins of the PWM pulse width modulation control chip U1 are connected, and the U1-9 pin of the PWM pulse width modulation control chip U1 is connected to the fifth point.

[0020] A resistor R1 is provided in the pulse modulation circuit, and a capacitor C1 is provided in the pulse modulation circuit. One end of the resistor R1 is connected to the RT pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R1 is set to the ninth point. One end of the capacitor C1 is connected to the CT pin of the PWM pulse width modulation control chip U1, and the other end is connected to the ninth point. The OUTPUT CTRL pin of the PWM pulse width modulation control chip U1 is connected to the ninth point, and the GND pin of the PWM pulse width modulation control chip U1 is connected to the ninth point. An electrolytic capacitor CAP1 is provided in the pulse modulation circuit, and the positive pole of the electrolytic capacitor CAP1 is connected to the U1-12 pin of the PWM pulse width modulation control chip U1, and the negative pole of the electrolytic capacitor CAP1 is connected to the ninth point.

[0021] Furthermore, resistors R3 and R4 are provided in the first optocoupler circuit, a capacitor resistor C2 is provided in the first optocoupler circuit, an optocoupler U4 is provided in the first optocoupler circuit, an MCU-5 interface is provided in the first optocoupler circuit, the input positive pin of the optocoupler U4 is connected to one end of the resistor R3, the input negative pin of the optocoupler U4 is connected to the other end of the resistor R3, the collector pin of the optocoupler U4 is connected to the second point, the emitter pin of the optocoupler U4 is set to the third grounding point, the resistor C2 is connected in parallel with the resistor R3, one end of the resistor C2 is connected to the input positive pin of the optocoupler U4, the other end of the resistor C2 is connected to the input negative pin of the optocoupler U4, one end of the resistor R4 is connected to the input positive pin of the optocoupler U4, and the other end of the resistor R4 is connected to MCU-5.

[0022] Since the current in a parallel circuit flows from the higher voltage end to the lower voltage end, when batteries are connected in parallel and a loop current forms, the current will flow from the higher voltage battery to the lower voltage battery, causing the current in the parallel branch where the lower voltage battery is located to increase. Therefore, the formation of a loop current can be prevented by adjusting and limiting the current in the parallel branch.

[0023] The lithium battery parallel protection board described in this utility model is activated when a circulating current forms. The MCU-5 interface of the first optocoupler circuit is connected to a high level, the positive and negative input pins of the optocoupler U4 are conductive, and MOS transistor Q1 is turned on. A 12V operating power supply is connected to the U1-12 (VCC), U1-8 (C1), and U1-11 (C2) pins of the PWM pulse width modulation control chip via the U3-3 pin of the linear regulator U3. This power supply is also connected to the U2-6 pin of the gate driver chip U2 through resistor R16, providing operating power to the PWM pulse width modulation control chip U1 and the gate driver chip U2, ensuring normal operation of the PWM pulse width modulation control chip U1 and the gate driver chip U2. The U1-1 (1IN+) and U1-16 (2IN+) pins of the PWM pulse width modulation control chip U1 are connected to the current sampling resistor R2 for current sampling. The PWM pulse width modulation (PWM) control chip U1's U1-1 pin (E1) and U1-10 (E2) pin are fed through diodes D4 and D6 to gate driver chip U2's U2-2 (INB) and U2-4 (INA) pins. Gate driver chip U2's U2-7 (OUTA) pin drives MOSFET Q8 through resistor R22 and diode D7. Gate driver chip U2's U2-5 (OUTB) pin drives MOSFET Q7 through resistor R20 and diode D8. Combined with energy storage inductor L1 and electrolytic capacitors CAP2, CAP3, CAP4, and CAP5, the current is ultimately limited and output to the MID MOS interface.

[0024] The utility model solves the problem of circulating current formed when multiple lithium batteries are connected in parallel during charging by limiting the output fixed current. This method can not only connect lithium batteries with different voltages, but also connect lithium batteries with different resistances and capacities, so that there is a wider range of choices when connecting batteries.

[0025] Furthermore, the lithium battery parallel protection board also includes a second optocoupler circuit, the second optocoupler circuit is provided with an optocoupler U5, resistors R11, R, R14 and R15, the second optocoupler circuit is provided with a capacitor C4, the second optocoupler circuit is provided with a MOS tube Q4, the second optocoupler circuit is provided with a diode D1, the second optocoupler circuit is provided with a fourth grounding point, the fourth grounding point is connected to the ninth point, the emitter pin of the optocoupler U5 is connected to the fourth grounding point, the collector pin of the optocoupler U5 is connected to the cathode of the diode D1, the cathode of the diode D1 is connected to one end of the resistor R15, and the The other end of the resistor R15 is connected to the gate of the MOS tube Q4, the drain of the MOS tube Q4 is connected to the third point, the source of the MOS tube Q4 is connected to U1-12, one end of the resistor R14 is connected to the gate of the MOS tube Q4, and the other end of the resistor R14 is connected to the source of the MOS tube Q4. The resistor R11 is connected in parallel with the resistor C4. One end of the circuit after the resistor R11 and the resistor C4 are connected in parallel is connected to the input positive pin of the optocoupler U5, and the other end is connected to the input negative pin of the optocoupler U5. One end of the resistor R is connected to the input positive pin of the optocoupler U5, and the other end of the resistor R is provided with an interface MCU-6 interface.

[0026] This approach can also be distinguished from the first optocoupler circuit, which outputs other limited fixed currents. This approach enables the present invention to cope with more different circulating current conditions, making the present invention more adaptable.

[0027] Furthermore, a lithium battery parallel protection board also includes a battery charging circuit, wherein the battery charging circuit is provided with a MID MOS interface, and the MID MOS interface in the battery charging circuit is connected to the MID MOS interface in the gate drive circuit.

[0028] Furthermore, the battery charging circuit is provided with a circuit negative output interface and a circuit positive output interface, the battery charging circuit is provided with a power supply positive pole point and a power supply negative pole point, the battery charging circuit includes a discharge control circuit, a current modulation circuit and an overvoltage protection circuit, the positive output interface is connected to the power supply positive pole point, the power supply negative pole point is connected to the discharge control circuit, the discharge control circuit is connected to the current modulation circuit, the current modulation circuit is connected to the overvoltage protection circuit, and the overvoltage protection circuit is connected to the negative output interface.

[0029] A lithium battery parallel protection board and a battery of the present invention are connected in series using a battery charging circuit, and the battery charging circuit directly controls and starts a lithium battery parallel protection board to output a limited fixed current. This method enables the present invention to more stably limit the current on the parallel branch, and can also not limit the current of the parallel branch when no circulation is formed, thereby saving energy and avoiding energy loss.

[0030] Further, the discharge control circuit is provided with resistors R40, R41 and R90, the resistors R40, R41 and R90 are connected in parallel, one end of the resistors R40, R41 and R90 connected in parallel is connected to the negative pole of the power supply, and the other end of the resistors R40, R41 and R90 connected in parallel is set to the first point; the discharge control circuit is provided with resistors R42, R43, R45, R46, R83 and R48, the discharge control circuit is provided with a transistor Q4, the discharge control circuit is provided with a diode D4, one end of the resistor R42 is connected to the first point, the other end of the resistor R42 is connected to the base of the transistor Q4, the emitter of the transistor Q4 is connected to one end of the resistor R45, and the transistor The collector of Q4 is connected to the cathode of diode D4, the anode of diode D4 is connected to the base of transistor Q4, the other end of the resistor R45 is connected to the first point, one end of the resistor R43 is connected to the base of transistor Q4, and the other end of the resistor R43 is provided with a DSG interface. The discharge control circuit is also provided with a voltage regulator diode D5, the cathode of diode D5 is connected to the cathode of diode D4, and the anode of diode D5 is connected to the first point, one end of the resistor R46 is connected to the cathode of diode D4, and the other end of the resistor R46 is connected to the first point, one end of the resistor R83 is connected to the cathode of diode D4, and the other end of the resistor R83 is set to the second point, one end of the resistor R48 is connected to the cathode of diode D4, and the other end of the resistor R48 is set to the third point.

[0031] The current modulation circuit is provided with MOS discharge tubes M1 and M3, the current modulation circuit is provided with charging MOS tubes M2 and M4, the current modulation circuit is further provided with a voltage regulator diode combination Z17, Z18, Z29 and Z30, the voltage regulator diode combination includes two voltage regulator diodes connected to the positive pole, the current modulation circuit is further provided with capacitors C35, C37, C69 and C70, the current modulation circuit is further provided with a resistor R51, one end of the resistor R51 is set to the fourth point, the other end of the resistor R51 is provided with a DISD interface, the gate of the MOS discharge tube M1 is connected to the third point, the The drain of the MOS discharge tube M1 is connected to the fourth point, the source of the MOS discharge tube M1 is connected to the first point, the gate of the MOS discharge tube M3 is connected to the second point, the drain of the MOS discharge tube M3 is connected to the fourth point, the source of the MOS discharge tube M1 is connected to the first point, the voltage regulator diode combination Z17 and the voltage regulator diode combination Z29 are connected in parallel, one end of the circuit after the voltage regulator diode combination Z17 and the voltage regulator diode combination Z29 are connected in parallel is connected to the first point, and the other end is connected to the fourth point, the resistor C35 and the resistor C37 are connected in series, and one end of the circuit after the resistor C35 and the resistor C37 are connected in series is connected to the first point, The other end is connected to the fourth point; the charging MOS tube M2 and the charging MOS tube M4 are respectively provided with 8 pins, the drain of the charging MOS tube M2 is provided with a fifth, sixth, seventh and eighth pins, the fifth, sixth, seventh and eighth pins are connected in parallel to the fourth point, the gate is provided with a fourth pin, the fourth pin is set as the fifth point, the source is provided with a first, second and third pins, the first, second and third pins are connected in parallel to the negative output interface of the circuit; the drain of the charging MOS tube M4 is provided with a fifth, sixth, seventh and eighth pins, the fifth, sixth, seventh and eighth pins are connected in parallel to The fourth point is connected, a fourth pin is provided on the gate, and the fourth pin is set to the sixth point. The first, second, and third pins are provided on the source, and the first, second, and third pins are connected in parallel to the negative output interface of the circuit; the voltage regulator diode combination Z18 and the voltage regulator diode combination Z30 are connected in parallel, and one end of the circuit after the voltage regulator diode combination Z18 and the voltage regulator diode combination Z30 are connected in parallel is connected to the fourth point, and the other end is connected to the negative output interface of the circuit. The resistor C69 and the resistor C70 are connected in series, and one end of the circuit after the resistor C69 and the resistor C70 are connected in series is connected to the negative output interface of the circuit, and the other end is connected to the fourth point.

[0032] The overvoltage protection circuit includes resistors R55, R84, R57, R60, and R58. Diodes D10 and D11 are also provided in the overvoltage protection circuit. A voltage stabilizing diode D6 is also provided in the overvoltage protection circuit. One end of resistor R55 is connected to the fifth point, and the other end is connected to the cathode of diode D10. One end of resistor R84 is connected to the sixth point, and the other end is connected to the cathode of diode D10. One end of resistor R58 is connected to the cathode of diode D10, and the other end is connected to the circuit's negative output interface. The cathode of diode D6 is connected to the cathode of diode D10, and the anode of diode D6 is connected to the circuit's negative output interface. The anode of diode D10 is connected to one end of resistor R57, and the other end of resistor R57 is provided with a CHG interface. One end of resistor R60 is connected to the circuit's negative output interface, and the other end of resistor R60 is provided with a CHGD interface.

[0033] The discharge control circuit, current modulation circuit and overvoltage protection circuit in the battery charging circuit can perform stable and safe charging when no circulating current is formed, and can more stably and safely add limited current when circulating current is formed, making the parallel lithium battery pack more stable and safer to charge. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a lithium battery parallel protection board structure circuit.

[0035] Figure 2 The invention relates to a lithium battery parallel protection board battery charging circuit. DETAILED DESCRIPTION

[0036] The utility model combines the same lithium batteries that have been placed for a period of time, and these lithium batteries have different voltages, different internal resistances, and different capacities into a lithium battery pack, and connects the positive electrode of the combined lithium battery pack to the positive power point of the battery charging circuit, and the negative electrode to the negative power point of the battery charging circuit.

[0037] Connect the MID MOS interface in the gate driver to the MID MOS interface in the battery charging circuit, and connect a 12V power supply to the working power interface of the linear voltage regulator circuit.

[0038] The embodiment is basically as shown in the attached Figure 1 、 Figure 2 As shown:

[0039] A lithium battery parallel protection board includes: a pulse modulation circuit, a gate drive circuit, a linear voltage stabilization circuit and a first optocoupler circuit; the linear voltage stabilization circuit is connected to the pulse modulation circuit and the gate drive circuit, the gate drive circuit is connected to the pulse modulation circuit, the first optocoupler circuit is connected to the pulse modulation circuit, the linear voltage stabilization circuit is provided with a working power supply interface, and the gate drive circuit is provided with a total circuit output interface.

[0040] The pulse modulation circuit is provided with a PWM pulse width modulation control chip U1, the gate drive circuit is provided with a gate drive chip U2, the linear voltage regulator circuit is provided with a linear voltage regulator U3, and the first optocoupler circuit is provided with an optocoupler U4; the U3-3 pin of the linear voltage regulator U3 is connected to the U1-12 pin of the PWM pulse width modulation control chip U1 and the U2-6 pin of the gate drive chip U2, the U2-2 pin and U2-4 pin of the gate drive chip U2 are connected to the U1-9 or U1-10 pin of the PWM pulse width modulation control chip U1, the collector pin of the optocoupler U4 is connected to the second point of the linear voltage regulator circuit, the U3-2 pin of the linear voltage regulator U3 is set as the working power supply interface, and the MID MOS interface of the gate drive circuit is set as the total circuit output interface.

[0041] The Vin pin in the linear regulator U3 is set to U3-2, and U3-2 is the working power supply interface. The Out pin in the linear regulator U3 is set to U3-3, and the GND pin in the linear regulator U3 is set to U3-1. A first grounding point is provided in the linear voltage regulator circuit, and the U3-1 pin of the linear voltage regulator U3 is connected to the first grounding point; a capacitor C3 is also provided in the linear voltage regulator circuit, one end of the capacitor C3 is connected to the U3-3 pin of the linear regulator U3, and the other end of the capacitor C3 is connected to the U3-1 pin of the linear voltage regulator U3.

[0042] The linear regulator U3 is further provided with resistors R5, R6, R7, R8, R9, and R10. The linear regulator U3 is provided with MOS tubes Q1 and Q2, and the linear regulator U3 is provided with diodes D3 and D2. One end of the resistor R5 is connected to the U3-3 pin of the linear regulator U3, and the other end of the resistor R5 is connected to the gate of the MOS tube Q1 and one end of the resistor R6. The source of the MOS tube Q1 is connected to the U3-3 pin of the linear regulator U3, and the drain of the MOS tube Q1 is set to the first point. The other end of the resistor R6 is connected to the gate of the MOS tube Q1 and the U3-3 pin of the linear regulator U3. The anode of the diode D2 is connected to the anode of the diode D2, and the diodes D2 and D3 are connected in parallel, and the cathode of the parallel connection is set as the second point; the anode of the diode D3 is connected to one end of the resistor R7, the other end of the resistor R7 is connected to the gate of the MOS transistor Q2 and one end of the resistor R8, the other end of the resistor R8 is connected to the first point, and the source of the MOS transistor Q2 is connected to the first point; the drain of the MOS transistor Q2 is connected to one end of the resistor R10, and the other end of the resistor R10 is set as the fourth point, one end of the resistor R9 is connected to the fourth point, and the other end of the resistor R9 is connected to the first ground point.

[0043] The GND pin in the gate drive chip U2 is set to the U2-3 pin, and the U2-3 pin of the gate drive chip U2 is connected to the first grounding point; the gate drive circuit is provided with resistors R12 and R13, and the gate drive circuit is provided with diodes D4 and D6. The INA pin and INB pin in the gate drive chip U2 are set to U2-2 and U2-4 respectively, and the U2-2 pin of the gate drive chip U2 is connected to the U2-4 pin of the gate drive chip U2. The cathode of the diode D6 is connected to the U2-4 pin of the gate drive chip U2, and the anode of the diode D6 is connected to the cathode of the diode D4. The anode of the diode D4 is connected to the cathode of the diode D4. The electrode is set to the fifth point. A MOS transistor Q3 is provided in the gate drive circuit. The gate of the MOS transistor Q3 is connected to the fifth point. The source of the MOS transistor Q3 is connected to the cathode of the diode D4. The drain of the MOS transistor Q3 is connected to one end of the resistor R12, and the other end of the resistor R12 is connected to the fifth point. The gate drive circuit is further provided with a capacitor C5. One end of the capacitor C5 is connected to the drain of the MOS transistor Q3, and the other end of the capacitor C5 is connected to the U2-4 pin of the gate drive chip U2. One end of the resistor R13 is connected to the drain of the MOS transistor Q3, and the other end of the resistor R13 is connected to the U2-4 pin of the gate drive chip U2.

[0044] The VDD pin in U2 is set to U2-6, and a resistor R16 is provided in the gate drive circuit. One end of the resistor R16 is connected to the U2-6 pin of the gate drive chip U2, and the other end of the resistor R16 is set to the sixth point; the OUTA and OUTB pins in the gate drive chip U2 are set to U2-7 and U2-5 respectively, and the gate drive circuit is further provided with resistors R20, R21, R22, R23 and R33, R34. The gate drive circuit is provided with diodes D8 and D7, and the gate drive circuit is provided with MOS tubes Q7 and Q8; the resistor R20 and the diode D8 are connected in series and in parallel with the resistor R21 to form a local circuit one, the positive electrode of the local circuit one is connected to the U2-5 pin of the gate drive chip U2, and the negative electrode is connected to one end of the resistor R33. The negative electrode of the local circuit one is also connected to the gate of the MOS tube Q7; the resistor R22 is connected to the second resistor R21 in parallel. The transistor D7 is connected in series with a resistor R23 in parallel to form a local circuit 2. The positive electrode of the local circuit 2 is connected to the U2-7 pin of the gate drive chip U2, and the negative electrode is connected to one end of the resistor R34. The negative electrode of the local circuit 2 is also connected to the gate of the MOS transistor Q8. The other end of the resistor R33 is set to the seventh point, and the other end of the resistor R34 is connected to the seventh point. The source of the MOS transistor Q7 and the source of the MOS transistor Q8 are connected to the seventh point. The gate drive circuit is provided with an inductor L1, one end of the inductor L1 is set to L1-2, and the other end is set to L1-1. The drain of the MOS transistor Q7 and the drain of the MOS transistor Q8 are connected to the L1-2 end of the inductor L1. The gate drive circuit is also provided with a resistor R30 and a capacitor C9. One end of the resistor R30 is connected to the L1-2 end of the inductor L1, and the other end of the resistor R30 is connected to one end of the capacitor C9. The gate drive circuit is provided with an interface MID MOS, the other end of the capacitor C9 is connected to MIDMOS, the MID MOS is the total circuit output interface, and the L1-1 end of the inductor L1 is connected to MID MOS; the gate drive circuit is also provided with electrolytic capacitors CAP2, CAP3, CAP4 and CAP5, the electrolytic capacitor CAP2 and the electrolytic capacitor CAP5 are connected in series and the positive poles are connected, the electrolytic capacitor CAP3 and the electrolytic capacitor CAP4 are connected in series and the positive poles are connected, the negative pole of the electrolytic capacitor CAP2 is set to the eighth point, the negative pole of the electrolytic capacitor CAP3 is connected to the eighth point, the negative pole of the electrolytic capacitor CAP4 and the negative pole of the electrolytic capacitor CAP5 are connected to MID MOS.

[0045] A second grounding point is provided in the pulse modulation circuit, and resistors R32, R31, and R2 are provided in the pulse modulation circuit. Capacitors C11 and C13 are provided in the pulse modulation circuit. The 1IN+ pin of the PWM pulse width modulation control chip U1 is set to U1-1, and the 2IN+ pin of the PWM pulse width modulation control chip U1 is set to U1-16. The C11 and the resistor R32 are connected in parallel, and the positive pole of the circuit after parallel connection is connected to the U1-1 pin of the PWM pulse width modulation control chip U1, and the negative pole of the circuit after parallel connection is connected to the seventh point; the capacitor C13 and the resistor R31 are connected in parallel, and the positive pole of the circuit after parallel connection is connected to the U1-16 pin of the PWM pulse width modulation control chip U1, and the negative pole of the circuit after parallel connection is connected to the eighth point; one end of the resistor R2 is connected to the seventh point, and the other end is connected to the eighth point; the second grounding point is connected to the eighth point.

[0046] The pulse modulation circuit is provided with capacitors C9, C12, C10, and C8, and the pulse modulation circuit is provided with resistors RF51K, R29, R28, R27, R24, R19, and R18. The 1IN- pin in the PWM pulse width modulation control chip U1 is set to U1-2, the FEEDBACK pin in the PWM pulse width modulation control chip U1 is set to U1-3, the 2IN- pin in the PWM pulse width modulation control chip U1 is set to U1-15, the DTC pin in the PWM pulse width modulation control chip U1 is set to U1-4, and the REF pin in the PWM pulse width modulation control chip U1 is set to U1-14. One end of the capacitor C9 is connected to the PWM pulse width modulation The U1-3 pin of the PWM pulse width modulation control chip U1 is connected to the U1-15 pin of the PWM pulse width modulation control chip U1. One end of the resistor RF51K is connected to the U1-3 pin of the PWM pulse width modulation control chip U1. The other end of the resistor RF51K is connected to the U1-15 pin of the PWM pulse width modulation control chip U1. One end of the capacitor C12 is connected to the U1-15 pin of the PWM pulse width modulation control chip U1. The other end of the capacitor C12 is connected to one end of the capacitor C10. The other end of the capacitor C10 is connected to the U1-2 pin of the PWM pulse width modulation control chip U1. One end of the resistor R29 is connected to the U1-2 pin of the PWM pulse width modulation control chip U1. The other end of R29 is connected to the second grounding point, one end of the resistor R24 is connected to the U1-14 pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R24 is connected to the U1-2 pin of the PWM pulse width modulation control chip U1. The resistor R19 is connected in parallel with the resistor R24, one end of the resistor R19 is connected to the U1-14 pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R19 is connected to the U1-15 pin of the PWM pulse width modulation control chip U1. The resistor R18 is connected in parallel with the resistor R19, one end of the resistor R18 is connected to the U1-14 pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R18 is connected to the U1-2 pin of the PWM pulse width modulation control chip U1. -4 pin, the capacitor C8 and the resistor R18 are connected in parallel, one end of the capacitor C8 is connected to the U1-14 pin of the PWM pulse width modulation control chip U1, and the other end of the capacitor C8 is connected to the U1-4 pin of the PWM pulse width modulation control chip U1, one end of the resistor R28 is connected to the U1-15 pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R28 is connected to the second grounding point. A MOS transistor Q6 is provided in the pulse modulation circuit, one end of the resistor R27 is connected to the U1-4 pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R27 is connected to the drain of the MOS transistor Q6, the source of the MOS transistor Q6 is connected to the second grounding point, and the gate of the MOS transistor Q6 is connected to the fourth point.

[0047] The pulse modulation circuit is provided with resistors R25, R26 and R17, and a MOS transistor Q5 is provided in the pulse modulation circuit. One end of the resistor R17 is set to the third point, the other end of the resistor R17 is connected to the gate of the MOS transistor Q5, the source of the MOS transistor Q5 is connected to the second grounding point, the drain of the MOS transistor Q5 is connected to one end of the resistor R26, the other end of the resistor R26 is connected to the U1-2 pin of the PWM pulse width modulation control chip U1, one end of the resistor R25 is connected to the gate of the MOS transistor Q5, and the other end of the resistor R25 is connected to the source of the MOS transistor Q5.

[0048] The pulse modulation circuit is provided with a fuse F, one end of which is set as F-1 and the other end is set as F-2. The F-1 end of the fuse F is connected to the second grounding point, and the F-1 end of the fuse F is the negative electrode interface of the working power supply.

[0049] The pulse modulation circuit is provided with a diode D5, and the pulse modulation circuit is provided with capacitors C6 and C7. The diode D5, capacitor C6 and capacitor C7 are connected in parallel, and the negative electrode of the parallel circuit is connected to the sixth point and the positive electrode is connected to the first ground point; the capacitor C1 pin and the capacitor C2 pin in the PWM pulse width modulation control chip U1 are connected, and the capacitor C1 pin is connected to the sixth point.

[0050] The U1-9 and U1-10 pins of the PWM pulse width modulation control chip U1 are connected, and the U1-9 pin of the PWM pulse width modulation control chip U1 is connected to the fifth point.

[0051] A resistor R1 is provided in the pulse modulation circuit, and a capacitor C1 is provided in the pulse modulation circuit. One end of the resistor R1 is connected to the RT pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R1 is set to the ninth point. One end of the capacitor C1 is connected to the CT pin of the PWM pulse width modulation control chip U1, and the other end is connected to the ninth point. The OUTPUT CTRL pin of the PWM pulse width modulation control chip U1 is connected to the ninth point, and the GND pin of the PWM pulse width modulation control chip U1 is connected to the ninth point. An electrolytic capacitor CAP1 is provided in the pulse modulation circuit, and the positive pole of the electrolytic capacitor CAP1 is connected to the U1-12 pin of the PWM pulse width modulation control chip U1, and the negative pole of the electrolytic capacitor CAP1 is connected to the ninth point.

[0052] The first optocoupler circuit is provided with resistors R3 and R4, the first optocoupler circuit is provided with a capacitor resistor C2, the first optocoupler circuit is provided with an optocoupler U4, the first optocoupler circuit is provided with an MCU-5 interface, the input positive pin of the optocoupler U4 is connected to one end of the resistor R3, the input negative pin of the optocoupler U4 is connected to the other end of the resistor R3, the collector pin of the optocoupler U4 is connected to the second point, the emitter pin of the optocoupler U4 is set to the third grounding point, the resistor C2 is connected in parallel with the resistor R3, one end of the resistor C2 is connected to the input positive pin of the optocoupler U4, the other end of the resistor C2 is connected to the input negative pin of the optocoupler U4, one end of the resistor R4 is connected to the input positive pin of the optocoupler U4, and the other end of the resistor R4 is connected to MCU-5.

[0053] The lithium battery parallel protection board further includes a battery charging circuit, wherein the battery charging circuit is provided with a MIDMOS interface, and the MID MOS interface in the battery charging circuit is connected to the MID MOS interface in the gate drive circuit.

[0054] The battery charging circuit is provided with a circuit negative output interface and a circuit positive output interface, and is provided with a power supply positive pole point and a power supply negative pole point. The battery charging circuit includes a discharge control circuit, a current modulation circuit and an overvoltage protection circuit. The positive output interface is connected to the power supply positive pole point, the power supply negative pole point is connected to the discharge control circuit, the discharge control circuit is connected to the current modulation circuit, the current modulation circuit is connected to the overvoltage protection circuit, and the overvoltage protection circuit is connected to the negative output interface.

[0055] The discharge control circuit is provided with resistors R40, R41 and R90, the resistors R40, R41 and R90 are connected in parallel, one end of the resistors R40, R41 and R90 connected in parallel is connected to the negative pole of the power supply, and the other end of the resistors R40, R41 and R90 connected in parallel is set as the first point; the discharge control circuit is provided with resistors R42, R43, R45, R46, R83 and R48, the discharge control circuit is provided with a transistor Q4, the discharge control circuit is provided with a diode D4, one end of the resistor R42 is connected to the first point, the other end of the resistor R42 is connected to the base of the transistor Q4, the emitter of the transistor Q4 is connected to one end of the resistor R45, and the transistor Q4 The collector is connected to the cathode of the diode D4, the anode of the diode D4 is connected to the base of the transistor Q4, the other end of the resistor R45 is connected to the first point, one end of the resistor R43 is connected to the base of the transistor Q4, and the other end of the resistor R43 is provided with a DSG interface. The discharge control circuit is also provided with a voltage regulator diode D5, the cathode of the diode D5 is connected to the cathode of the diode D4, and the anode of the diode D5 is connected to the first point, one end of the resistor R46 is connected to the cathode of the diode D4, and the other end of the resistor R46 is connected to the first point, one end of the resistor R83 is connected to the cathode of the diode D4, and the other end of the resistor R83 is set to the second point, one end of the resistor R48 is connected to the cathode of the diode D4, and the other end of the resistor R48 is set to the third point.

[0056] The current modulation circuit is provided with MOS discharge tubes M1 and M3, the current modulation circuit is provided with charging MOS tubes M2 and M4, the current modulation circuit is further provided with a voltage regulator diode combination Z17, Z18, Z29 and Z30, the voltage regulator diode combination includes two voltage regulator diodes connected to the positive pole, the current modulation circuit is further provided with capacitors C35, C37, C69 and C70, the current modulation circuit is further provided with a resistor R51, one end of the resistor R51 is set to the fourth point, the other end of the resistor R51 is provided with a DISD interface, the gate of the MOS discharge tube M1 is connected to the third point, the The drain of the MOS discharge tube M1 is connected to the fourth point, the source of the MOS discharge tube M1 is connected to the first point, the gate of the MOS discharge tube M3 is connected to the second point, the drain of the MOS discharge tube M3 is connected to the fourth point, the source of the MOS discharge tube M1 is connected to the first point, the voltage regulator diode combination Z17 and the voltage regulator diode combination Z29 are connected in parallel, one end of the circuit after the voltage regulator diode combination Z17 and the voltage regulator diode combination Z29 are connected in parallel is connected to the first point, and the other end is connected to the fourth point, the resistor C35 and the resistor C37 are connected in series, and one end of the circuit after the resistor C35 and the resistor C37 are connected in series is connected to the first point, The other end is connected to the fourth point; the charging MOS tube M2 and the charging MOS tube M4 are respectively provided with 8 pins, the drain of the charging MOS tube M2 is provided with a fifth, sixth, seventh and eighth pins, the fifth, sixth, seventh and eighth pins are connected in parallel to the fourth point, the gate is provided with a fourth pin, the fourth pin is set as the fifth point, the source is provided with a first, second and third pins, the first, second and third pins are connected in parallel to the negative output interface of the circuit; the drain of the charging MOS tube M4 is provided with a fifth, sixth, seventh and eighth pins, the fifth, sixth, seventh and eighth pins are connected in parallel to The fourth point is connected, a fourth pin is provided on the gate, and the fourth pin is set to the sixth point. The first, second, and third pins are provided on the source, and the first, second, and third pins are connected in parallel to the negative output interface of the circuit; the voltage regulator diode combination Z18 and the voltage regulator diode combination Z30 are connected in parallel, and one end of the circuit after the voltage regulator diode combination Z18 and the voltage regulator diode combination Z30 are connected in parallel is connected to the fourth point, and the other end is connected to the negative output interface of the circuit. The resistor C69 and the resistor C70 are connected in series, and one end of the circuit after the resistor C69 and the resistor C70 are connected in series is connected to the negative output interface of the circuit, and the other end is connected to the fourth point.

[0057] The overvoltage protection circuit is provided with resistors R55, R84, R57, R60 and R58, and is provided with diodes D10 and D11. The overvoltage protection circuit is provided with a voltage stabilizing diode D6. One end of the resistor R55 is connected to the fifth point, and the other end of the resistor R55 is connected to the cathode of the diode D10. One end of the resistor R84 is connected to the sixth point, and the other end of the resistor R84 is connected to the cathode of the diode D10. One end of the resistor R58 is connected to the cathode of the diode D10, and the other end of the resistor R58 is connected to the cathode output interface of the circuit. The cathode of the diode D6 is connected to the cathode of the diode D10, and the positive electrode of the diode D6 is connected to the negative output interface of the circuit. The positive electrode of the diode D10 is connected to one end of the resistor R57, and the other end of the resistor R57 is provided with a CHG interface. One end of the resistor R60 is connected to the negative output interface of the circuit, and the other end of the resistor R60 is provided with a CHGD interface.

[0058] Example 1

[0059] In this example, four types of lithium batteries were selected: a 5V, 2000mA lithium battery, a 5V, 4000mA lithium battery, a 10V, 2000mA lithium battery, and a 10V, 4000mA lithium battery. These four types of lithium batteries were combined into a lithium battery pack to charge a 15,000mA toy car. In this example, the operator was asked to charge the charging device vehicle.

[0060] The operator connects the assembled lithium battery pack and the depleted charging device to the battery charging circuit.

[0061] When the maximum charging current is 50A, Figure 1 The MCU-5 pin is at a low level. At this time, the positive input pin and the negative input pin of the optocoupler U4 are not conducting, the MOS tube Q1 is cut off, the U1-12 (VCC) pin of the PWM pulse width modulation control chip U1 has no working power supply, the entire current limiting circuit is not started, and the battery is charged normally. The process is as follows (such as Figure 2 ), the charging current flows from C+ through the battery B+ to B-, through the resistors R40, R41, R90 sampling resistors, MOS discharge tubes M1, M3, charging MOS tubes M2, M4, and flows through C- for normal charging.

[0062] When the charging current is greater than the maximum charging current of 50A, the operator connects a lithium battery parallel protection board to the power supply and battery charging circuit. Figure 1When MCU-5 is high, the positive and negative input pins of U4 are conducting, and MOS transistor Q1 (P transistor) is also conducting. The U3-3 (OUT) pin (12V) of linear regulator U3 is connected to the U1-12 (VCC), U1-8 (C1), and U1-11 (C2) pins of PWM pulse width modulation control chip U1. This is also connected to the U2-6 (VDD) pin of gate driver chip U2 through resistor R16, providing operating power for PWM pulse width modulation control chip U1 and gate driver chip U2, ensuring normal operation of PWM pulse width modulation control chip U1 and gate driver chip U2. The U1-1 (1IN+) and U1-16 (2IN+) pins of PWM pulse width modulation control chip U1 are connected to current sampling resistor R2 for current sampling. The PWM pulse width modulation (PWM) control chip U1's U1-9 (E1) and U1-10 (E2) pins are fed through diodes D4 and D6 to the gate driver chip U2's U2-2 (INB) and U2-4 (INA) pins. Gate driver chip U2's U2-7 (OUTA) pin drives MOSFET Q8 via resistor R22 and diode D7. Gate driver chip U2's U2-5 (OUTB) pin drives MOSFET Q7 via resistor R20 and diode D8. Together with energy storage inductor L1 and electrolytic capacitors CAP2, CAP3, CAP4, and CAP5, this circuit forms a 10A current limiter. The 10A current limiter is initially activated for 10 minutes. If the current continues to exceed 50A, the current limiter is activated again for 10 minutes. This cycle is repeated three times until the cell voltage reaches 3.65V, triggering overcharge protection. If this occurs three times, the device must be shut down and restarted regardless of the current level. If the charging current is lower than 50A and MCU-5 is at a low level, the U4-3 and U4-4 pins of the optocoupler U4 are not conducting, the MOS tube Q1 is cut off, the PWM pulse width modulation control chip U1 and the gate drive chip U2 are powered off, and the system returns to normal charging.

[0063] The depletion of the lithium battery power is considered to be the end of charging of the charging device. After charging is completed, the operator operates the charging device to deplete the power of the charging device. The operator records the operating time of the charging device during this period, which is 11 hours. The operator then uses four lithium batteries to charge the charging device respectively and records the corresponding operating time of the four lithium batteries. The corresponding charging time and operating time of the four lithium batteries are: 5V, 2000mA lithium battery works for 2 hours, 5V, 4000mA lithium battery works for 4 hours, 10V, 2000mA lithium battery works for 2 hours, and 10V, 4000mA lithium battery works for 4 hours. It can be seen that the utility model realizes the arbitrary combination of battery packs with different voltages, capacities, and internal resistances, and also achieves the effect of rapid capacity expansion.

[0064] Example 2

[0065] The only difference from Example 1 is that:

[0066] The lithium battery parallel protection board also includes a second optocoupler circuit, wherein the second optocoupler circuit is provided with an optocoupler U5, resistors R11, R, R14 and R15, the second optocoupler circuit is provided with a capacitor C4, the second optocoupler circuit is provided with a MOS tube Q4, the second optocoupler circuit is provided with a diode D1, the second optocoupler circuit is provided with a fourth grounding point, the fourth grounding point is connected to the ninth point, the emitter pin of the optocoupler U5 is connected to the fourth grounding point, the collector pin of the optocoupler U5 is connected to the cathode of the diode D1, the cathode of the diode D1 is connected to one end of the resistor R15, and the fourth grounding point is connected to the ninth point. The other end of the resistor R15 is connected to the gate of the MOS tube Q4, the drain of the MOS tube Q4 is connected to the third point, and the source of the MOS tube Q4 is connected to U1-12. One end of the resistor R14 is connected to the gate of the MOS tube Q4, and the other end of the resistor R14 is connected to the source of the MOS tube Q4. The resistor R11 is connected in parallel with the resistor C4. One end of the circuit after the resistor R11 and the resistor C4 are connected in parallel is connected to the input positive pin of the optocoupler U5, and the other end is connected to the input negative pin of the optocoupler U5. One end of the resistor R is connected to the input positive pin of the optocoupler U5, and the other end of the resistor R is provided with an interface MCU-6 interface.

[0067] like Figure 1 As shown, Figure 1 When MCU-6 is at a high level, the optocoupler U5 is turned on, and at the same time, the MOS tube Q4 (P tube) and the MOS tube Q5 are turned on. The resistors R26 and R29 are connected in parallel and divided with the resistor R24 as the reverse end of the error amplifier to input the 1IN- pin (i.e., U1-2 pin) of the PWM pulse width modulation control chip U1, changing the sampling current amplification factor and realizing 20A current limited charging.

[0068] The above is only an embodiment of the present invention, and the commonly known specific structures and characteristics of the scheme are not described in detail here. It should be pointed out that for those skilled in the art, several modifications and improvements can be made without departing from the structure of the present invention, and these should also be regarded as the scope of protection of the present invention. These will not affect the effect of the implementation of the present invention and the practicality of the patent. The scope of protection claimed by this application shall be based on the content of its claims, and the specific implementation methods and other records in the specification can be used to interpret the content of the claims.

Claims

1. A lithium battery parallel protection board, characterized in that: include: A pulse modulation circuit, a gate drive circuit, a linear voltage stabilization circuit, and a first optocoupler circuit; the linear voltage stabilization circuit is connected to the pulse modulation circuit and the gate drive circuit, the gate drive circuit is connected to the pulse modulation circuit, the first optocoupler circuit is connected to the pulse modulation circuit, the linear voltage stabilization circuit is provided with a working power supply interface, and the gate drive circuit is provided with a total circuit output interface; The pulse modulation circuit is provided with a PWM pulse width modulation control chip U1, the gate drive circuit is provided with a gate drive chip U2, the linear voltage regulator circuit is provided with a linear voltage regulator U3, and the first optocoupler circuit is provided with an optocoupler U4; the U3-3 pin of the linear voltage regulator U3 is connected to the U1-12 pin of the PWM pulse width modulation control chip U1 and the U2-6 pin of the gate drive chip U2, the U2-2 pin and U2-4 pin of the gate drive chip U2 are connected to the U1-9 or U1-10 pin of the PWM pulse width modulation control chip U1, the collector pin of the optocoupler U4 is connected to the second point of the linear voltage regulator circuit, the U3-2 pin of the linear voltage regulator U3 is set as the working power supply interface, and the MID MOS interface of the gate drive circuit is set as the total circuit output interface.

2. The lithium battery parallel protection board according to claim 1, characterized in that: The linear voltage regulator circuit is provided with a linear voltage regulator U3, the Vin pin of the linear voltage regulator U3 is set to U3-2, the U3-2 is a working power supply interface, the Out pin of the linear voltage regulator U3 is set to U3-3, the GND pin of the linear voltage regulator U3 is set to U3-1, the linear voltage regulator circuit is provided with a first grounding point, and the U3-1 pin of the linear voltage regulator U3 is connected to the first grounding point; the linear voltage regulator circuit is further provided with a capacitor C3, one end of the capacitor C3 is connected to the U3-3 pin of the linear voltage regulator U3, and the other end of the capacitor C3 is connected to the U3-1 pin of the linear voltage regulator U3; The linear regulator U3 is further provided with resistors R5, R6, R7, R8, R9, and R10. The linear regulator U3 is provided with MOS transistors Q1 and Q2. The linear regulator U3 is provided with diodes D3 and D2. One end of the resistor R5 is connected to the U3-3 pin of the linear regulator U3, and the other end of the resistor R5 is connected to the gate of the MOS transistor Q1 and one end of the resistor R6. The source of the MOS transistor Q1 is connected to the U3-3 pin of the linear regulator U3. The drain of the MOS transistor Q1 is set to the first point. The other end of the resistor R6 is connected to the gate of the MOS transistor Q1 and the U3-3 pin of the linear regulator U3. The anode of diode D2 is connected, and the diodes D2 and D3 are connected in parallel, and the cathode of the parallel connection is set as the second point. The anode of diode D3 is connected to one end of resistor R7, the other end of resistor R7 is connected to the gate of MOS transistor Q2 and one end of resistor R8, the other end of resistor R8 is connected to the first point, and the source of MOS transistor Q2 is connected to the first point. The drain of MOS transistor Q2 is connected to one end of resistor R10, and the other end of resistor R10 is set as the fourth point. One end of resistor R9 is connected to the fourth point, and the other end of resistor R9 is connected to the first ground point.

3. The lithium battery parallel protection board according to claim 2, characterized in that: The gate drive circuit is provided with a gate drive chip U2, the GND pin in the gate drive chip U2 is set to the U2-3 pin, and the U2-3 pin of the gate drive chip U2 is connected to the first grounding point; the gate drive circuit is provided with resistors R12 and R13, and the gate drive circuit is provided with diodes D4 and D6. The INA pin and INB pin in the gate drive chip U2 are set to U2-2 and U2-4 respectively, the U2-2 pin of the gate drive chip U2 is connected to the U2-4 pin of the gate drive chip U2, the cathode of the diode D6 is connected to the U2-4 pin of the gate drive chip U2, and the anode of the diode D6 is connected to the diode D4 The cathode of the diode D4 is set as the fifth point. The gate drive circuit is provided with a MOS transistor Q3. The gate of the MOS transistor Q3 is connected to the fifth point. The source of the MOS transistor Q3 is connected to the cathode of the diode D4. The drain of the MOS transistor Q3 is connected to one end of the resistor R12. The other end of the resistor R12 is connected to the fifth point. The gate drive circuit is further provided with a capacitor C5. One end of the capacitor C5 is connected to the drain of the MOS transistor Q3. The other end of the capacitor C5 is connected to the U2-4 pin of the gate drive chip U2. One end of the resistor R13 is connected to the drain of the MOS transistor Q3. The other end of the resistor R13 is connected to the U2-4 pin of the gate drive chip U2. The VDD pin in U2 is set to U2-6, and a resistor R16 is provided in the gate drive circuit. One end of the resistor R16 is connected to the U2-6 pin of the gate drive chip U2, and the other end of the resistor R16 is set to the sixth point; the OUTA and OUTB pins in the gate drive chip U2 are set to U2-7 and U2-5 respectively, and the gate drive circuit is further provided with resistors R20, R21, R22, R23 and R33, R34. The gate drive circuit is provided with diodes D8 and D7, and the gate drive circuit is provided with MOS tubes Q7 and Q8; the resistor R20 and the diode D8 are connected in series and in parallel with the resistor R21 to form a local circuit one, the positive electrode of the local circuit one is connected to the U2-5 pin of the gate drive chip U2, and the negative electrode is connected to one end of the resistor R33. The negative electrode of the local circuit one is also connected to the gate of the MOS tube Q7; the resistor R22 is connected to the second resistor R21 in parallel. The transistor D7 is connected in series with a resistor R23 in parallel to form a local circuit 2. The positive electrode of the local circuit 2 is connected to the U2-7 pin of the gate drive chip U2, and the negative electrode is connected to one end of the resistor R34. The negative electrode of the local circuit 2 is also connected to the gate of the MOS transistor Q8. The other end of the resistor R33 is set to the seventh point, and the other end of the resistor R34 is connected to the seventh point. The source of the MOS transistor Q7 and the source of the MOS transistor Q8 are connected to the seventh point. The gate drive circuit is provided with an inductor L1, one end of the inductor L1 is set to L1-2, and the other end is set to L1-1. The drain of the MOS transistor Q7 and the drain of the MOS transistor Q8 are connected to the L1-2 end of the inductor L1. The gate drive circuit is also provided with a resistor R30 and a capacitor C9. One end of the resistor R30 is connected to the L1-2 end of the inductor L1, and the other end of the resistor R30 is connected to one end of the capacitor C9. The gate drive circuit is provided with an interface MID MOS, the other end of the capacitor C9 is connected to the MID MOS, the MID MOS is the total circuit output interface, and the L1-1 end of the inductor L1 is connected to the MIDMOS; the gate drive circuit is also provided with electrolytic capacitors CAP2, CAP3, CAP4 and CAP5, the electrolytic capacitor CAP2 and the electrolytic capacitor CAP5 are connected in series and the positive poles are connected, the electrolytic capacitor CAP3 and the electrolytic capacitor CAP4 are connected in series and the positive poles are connected, the negative pole of the electrolytic capacitor CAP2 is set to the eighth point, the negative pole of the electrolytic capacitor CAP3 is connected to the eighth point, the negative pole of the electrolytic capacitor CAP4 and the negative pole of the electrolytic capacitor CAP5 are connected to the MID MOS.

4. The lithium battery parallel protection board according to claim 3, characterized in that: The pulse modulation circuit is provided with a PWM pulse width modulation control chip U1, a second grounding point is provided in the pulse modulation circuit, resistors R32, R31, and R2 are provided in the pulse modulation circuit, capacitors C11 and C13 are provided in the pulse modulation circuit, the 1IN+ pin of the PWM pulse width modulation control chip U1 is set to U1-1, the 2IN+ pin of the PWM pulse width modulation control chip U1 is set to U1-16, the C11 and the resistor R32 are connected in parallel, and the positive electrode of the parallel circuit is connected to the U1-1 pin of the PWM pulse width modulation control chip U1, and the negative electrode of the parallel circuit is connected to the seventh point; the capacitor C13 is connected in parallel with the resistor R31, and the positive electrode of the parallel circuit is connected to the U1-16 pin of the PWM pulse width modulation control chip U1, and the negative electrode of the parallel circuit is connected to the eighth point; one end of the resistor R2 is connected to the seventh point, and the other end is connected to the eighth point; the second grounding point is connected to the eighth point; The pulse modulation circuit is provided with capacitors C9, C12, C10, and C8, and the pulse modulation circuit is provided with resistors RF51K, R29, R28, R27, R24, R19, and R18. The 1IN- pin in the PWM pulse width modulation control chip U1 is set to U1-2, the FEEDBACK pin in the PWM pulse width modulation control chip U1 is set to U1-3, the 2IN- pin in the PWM pulse width modulation control chip U1 is set to U1-15, the DTC pin in the PWM pulse width modulation control chip U1 is set to U1-4, and the REF pin in the PWM pulse width modulation control chip U1 is set to U1-14. One end of the capacitor C9 is connected to the PWM pulse width modulation The U1-3 pin of the PWM pulse width modulation control chip U1 is connected to the U1-15 pin of the PWM pulse width modulation control chip U1. One end of the resistor RF51K is connected to the U1-3 pin of the PWM pulse width modulation control chip U1. The other end of the resistor RF51K is connected to the U1-15 pin of the PWM pulse width modulation control chip U1. One end of the capacitor C12 is connected to the U1-15 pin of the PWM pulse width modulation control chip U1. The other end of the capacitor C12 is connected to one end of the capacitor C10. The other end of the capacitor C10 is connected to the U1-2 pin of the PWM pulse width modulation control chip U1. One end of the resistor R29 is connected to the U1-2 pin of the PWM pulse width modulation control chip U1. The other end of R29 is connected to the second grounding point, one end of the resistor R24 is connected to the U1-14 pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R24 is connected to the U1-2 pin of the PWM pulse width modulation control chip U1. The resistor R19 is connected in parallel with the resistor R24, one end of the resistor R19 is connected to the U1-14 pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R19 is connected to the U1-15 pin of the PWM pulse width modulation control chip U1. The resistor R18 is connected in parallel with the resistor R19, one end of the resistor R18 is connected to the U1-14 pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R18 is connected to the U1-2 pin of the PWM pulse width modulation control chip U1. -4 pin, the capacitor C8 and the resistor R18 are connected in parallel, one end of the capacitor C8 is connected to the U1-14 pin of the PWM pulse width modulation control chip U1, and the other end of the capacitor C8 is connected to the U1-4 pin of the PWM pulse width modulation control chip U1, one end of the resistor R28 is connected to the U1-15 pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R28 is connected to the second grounding point, a MOS transistor Q6 is provided in the pulse modulation circuit, one end of the resistor R27 is connected to the U1-4 pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R27 is connected to the drain of the MOS transistor Q6, the source of the MOS transistor Q6 is connected to the second grounding point, and the gate of the MOS transistor Q6 is connected to the fourth point; The pulse modulation circuit is provided with resistors R25, R26 and R17, and a MOS transistor Q5 is provided in the pulse modulation circuit. One end of the resistor R17 is set to the third point, the other end of the resistor R17 is connected to the gate of the MOS transistor Q5, the source of the MOS transistor Q5 is connected to the second grounding point, the drain of the MOS transistor Q5 is connected to one end of the resistor R26, the other end of the resistor R26 is connected to the U1-2 pin of the PWM pulse width modulation control chip U1, one end of the resistor R25 is connected to the gate of the MOS transistor Q5, and the other end of the resistor R25 is connected to the source of the MOS transistor Q5; The pulse modulation circuit is provided with a fuse F, one end of which is set as F-1 and the other end is set as F-2. The F-1 end of the fuse F is connected to the second grounding point, and the F-1 end of the fuse F is the negative electrode interface of the working power supply; The pulse modulation circuit is provided with a diode D5, and the pulse modulation circuit is provided with capacitors C6 and C7. The diode D5, capacitor C6 and capacitor C7 are connected in parallel, and the negative electrode of the parallel circuit is connected to the sixth point and the positive electrode is connected to the first ground point; the capacitor C1 pin and the capacitor C2 pin in the PWM pulse width modulation control chip U1 are connected, and the capacitor C1 pin is connected to the sixth point; The U1-9 and U1-10 pins of the PWM pulse width modulation control chip U1 are connected, and the U1-9 pin of the PWM pulse width modulation control chip U1 is connected to the fifth point; A resistor R1 is provided in the pulse modulation circuit, and a capacitor C1 is provided in the pulse modulation circuit. One end of the resistor R1 is connected to the RT pin of the PWM pulse width modulation control chip U1, and the other end of the resistor R1 is set to the ninth point. One end of the capacitor C1 is connected to the CT pin of the PWM pulse width modulation control chip U1, and the other end is connected to the ninth point. The OUTPUT CTRL pin of the PWM pulse width modulation control chip U1 is connected to the ninth point, and the GND pin of the PWM pulse width modulation control chip U1 is connected to the ninth point. An electrolytic capacitor CAP1 is provided in the pulse modulation circuit, and the positive pole of the electrolytic capacitor CAP1 is connected to the U1-12 pin of the PWM pulse width modulation control chip U1, and the negative pole of the electrolytic capacitor CAP1 is connected to the ninth point.

5. The lithium battery parallel protection board according to claim 4, characterized in that: The first optocoupler circuit is provided with resistors R3 and R4, the first optocoupler circuit is provided with a capacitor resistor C2, the first optocoupler circuit is provided with an optocoupler U4, the first optocoupler circuit is provided with an MCU-5 interface, the input positive pin of the optocoupler U4 is connected to one end of the resistor R3, the input negative pin of the optocoupler U4 is connected to the other end of the resistor R3, the collector pin of the optocoupler U4 is connected to the second point, the emitter pin of the optocoupler U4 is set to the third grounding point, the resistor C2 is connected in parallel with the resistor R3, one end of the resistor C2 is connected to the input positive pin of the optocoupler U4, the other end of the resistor C2 is connected to the input negative pin of the optocoupler U4, one end of the resistor R4 is connected to the input positive pin of the optocoupler U4, and the other end of the resistor R4 is connected to MCU-5.

6. The lithium battery parallel protection board according to claim 5, characterized in that: The lithium battery parallel protection board also includes a second optocoupler circuit, wherein the second optocoupler circuit is provided with an optocoupler U5, resistors R11, R, R14 and R15, the second optocoupler circuit is provided with a capacitor C4, the second optocoupler circuit is provided with a MOS tube Q4, the second optocoupler circuit is provided with a diode D1, the second optocoupler circuit is provided with a fourth grounding point, the fourth grounding point is connected to the ninth point, the emitter pin of the optocoupler U5 is connected to the fourth grounding point, the collector pin of the optocoupler U5 is connected to the cathode of the diode D1, the cathode of the diode D1 is connected to one end of the resistor R15, and the fourth grounding point is connected to the ninth point. The other end of the resistor R15 is connected to the gate of the MOS tube Q4, the drain of the MOS tube Q4 is connected to the third point, and the source of the MOS tube Q4 is connected to U1-12. One end of the resistor R14 is connected to the gate of the MOS tube Q4, and the other end of the resistor R14 is connected to the source of the MOS tube Q4. The resistor R11 is connected in parallel with the resistor C4. One end of the circuit after the resistor R11 and the resistor C4 are connected in parallel is connected to the input positive pin of the optocoupler U5, and the other end is connected to the input negative pin of the optocoupler U5. One end of the resistor R is connected to the input positive pin of the optocoupler U5, and the other end of the resistor R is provided with an interface MCU-6 interface.

7. The lithium battery parallel protection board according to claim 6, characterized in that: A lithium battery parallel protection board also includes a battery charging circuit, wherein the battery charging circuit is provided with a MID MOS interface, and the MID MOS interface in the battery charging circuit is connected to the MID MOS interface in the gate drive circuit.

8. The lithium battery parallel protection board according to claim 7, characterized in that: The battery charging circuit is provided with a circuit negative output interface and a circuit positive output interface, and is provided with a power supply positive pole point and a power supply negative pole point. The battery charging circuit includes a discharge control circuit, a current modulation circuit and an overvoltage protection circuit. The positive output interface is connected to the power supply positive pole point, the power supply negative pole point is connected to the discharge control circuit, the discharge control circuit is connected to the current modulation circuit, the current modulation circuit is connected to the overvoltage protection circuit, and the overvoltage protection circuit is connected to the negative output interface.

9. The lithium battery parallel protection board according to claim 8, characterized in that: The discharge control circuit is provided with resistors R40, R41 and R90, the resistors R40, R41 and R90 are connected in parallel, one end of the resistors R40, R41 and R90 connected in parallel is connected to the negative pole of the power supply, and the other end of the resistors R40, R41 and R90 connected in parallel is set as the first point; the discharge control circuit is provided with resistors R42, R43, R45, R46, R83 and R48, the discharge control circuit is provided with a transistor Q4, the discharge control circuit is provided with a diode D4, one end of the resistor R42 is connected to the first point, the other end of the resistor R42 is connected to the base of the transistor Q4, the emitter of the transistor Q4 is connected to one end of the resistor R45, and the transistor Q4 The collector is connected to the cathode of the diode D4, the anode of the diode D4 is connected to the base of the transistor Q4, the other end of the resistor R45 is connected to the first point, one end of the resistor R43 is connected to the base of the transistor Q4, and the other end of the resistor R43 is provided with a DSG interface. The discharge control circuit is further provided with a voltage regulator diode D5, the cathode of the diode D5 is connected to the cathode of the diode D4, and the anode of the diode D5 is connected to the first point, one end of the resistor R46 is connected to the cathode of the diode D4, and the other end of the resistor R46 is connected to the first point, one end of the resistor R83 is connected to the cathode of the diode D4, and the other end of the resistor R83 is set to the second point, one end of the resistor R48 is connected to the cathode of the diode D4, and the other end of the resistor R48 is set to the third point; The current modulation circuit is provided with MOS discharge tubes M1 and M3, the current modulation circuit is provided with charging MOS tubes M2 and M4, the current modulation circuit is further provided with a voltage regulator diode combination Z17, Z18, Z29 and Z30, the voltage regulator diode combination includes two voltage regulator diodes connected to the positive pole, the current modulation circuit is further provided with capacitors C35, C37, C69 and C70, the current modulation circuit is further provided with a resistor R51, one end of the resistor R51 is set to the fourth point, the other end of the resistor R51 is provided with a DISD interface, the gate of the MOS discharge tube M1 is connected to the third point, the The drain of the MOS discharge tube M1 is connected to the fourth point, the source of the MOS discharge tube M1 is connected to the first point, the gate of the MOS discharge tube M3 is connected to the second point, the drain of the MOS discharge tube M3 is connected to the fourth point, the source of the MOS discharge tube M1 is connected to the first point, the voltage regulator diode combination Z17 and the voltage regulator diode combination Z29 are connected in parallel, one end of the circuit after the voltage regulator diode combination Z17 and the voltage regulator diode combination Z29 are connected in parallel is connected to the first point, and the other end is connected to the fourth point, the resistor C35 and the resistor C37 are connected in series, and one end of the circuit after the resistor C35 and the resistor C37 are connected in series is connected to the first point, The other end is connected to the fourth point; the charging MOS tube M2 and the charging MOS tube M4 are respectively provided with 8 pins, the drain of the charging MOS tube M2 is provided with a fifth, sixth, seventh and eighth pins, the fifth, sixth, seventh and eighth pins are connected in parallel to the fourth point, the gate is provided with a fourth pin, the fourth pin is set as the fifth point, the source is provided with a first, second and third pins, the first, second and third pins are connected in parallel to the negative output interface of the circuit; the drain of the charging MOS tube M4 is provided with a fifth, sixth, seventh and eighth pins, the fifth, sixth, seventh and eighth pins are connected in parallel to Connected to the fourth point, the gate is provided with a fourth pin, the fourth pin is set as the sixth point, the source is provided with first, second, and third pins, the first, second, and third pins are connected in parallel to the circuit negative output interface; the voltage regulator diode combination Z18 and the voltage regulator diode combination Z30 are connected in parallel, one end of the circuit of the voltage regulator diode combination Z18 and the voltage regulator diode combination Z30 is connected in parallel to the fourth point, and the other end is connected to the circuit negative output interface, the resistor C69 and the resistor C70 are connected in series, one end of the circuit of the resistor C69 and the resistor C70 is connected in series to the circuit negative output interface, and the other end is connected to the fourth point; The overvoltage protection circuit is provided with resistors R55, R84, R57, R60 and R58, and is provided with diodes D10 and D11. The overvoltage protection circuit is provided with a voltage stabilizing diode D6. One end of the resistor R55 is connected to the fifth point, and the other end of the resistor R55 is connected to the cathode of the diode D10. One end of the resistor R84 is connected to the sixth point, and the other end of the resistor R84 is connected to the cathode of the diode D10. One end of the resistor R58 is connected to the cathode of the diode D10, and the other end of the resistor R58 is connected to the cathode output interface of the circuit. The cathode of the diode D6 is connected to the cathode of the diode D10, and the positive electrode of the diode D6 is connected to the negative output interface of the circuit. The positive electrode of the diode D10 is connected to one end of the resistor R57, and the other end of the resistor R57 is provided with a CHG interface. One end of the resistor R60 is connected to the negative output interface of the circuit, and the other end of the resistor R60 is provided with a CHGD interface.

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