Integrated body assembly

Abstract

The utility model provides an integrated body assembly, comprising a substrate comprising a channel region; a gate structure disposed on the substrate and over the channel region; the first doping region of the first doping type is located on the first side of the gate structure; the second doping region of the first doping type is located on the second side of the gate structure; a shallow trench isolation structure disposed on an opposite side of the gate structure from the first doped region, the shallow trench isolation structure having a bottom surface at a first depth below the top surface of the substrate; and a shallow trench isolation structure extending from the second doped region to the gate structure, the shallow trench isolation structure having a bottom surface at a second depth below the top surface of the substrate, where the second depth is less than the first depth.

Description

Technical Field

[0001] The utility model relates to an integrated component. Background Art

[0002] Many modern electronic components include metal oxide semiconductor field effect transistors (MOSFETs). Different types of MOSFETs can be designed to accommodate different power levels, such as low voltage MOSFETs (LVMOS) and high voltage MOSFETs (HVMOS). HVMOS devices are designed to withstand higher gate-to-drain voltages than LVMOS devices. LVMOS devices are smaller and more efficient than HVMOS devices. Utility Model Content

[0003] The utility model provides an integrated circuit component, which includes a substrate including a channel region; a gate structure, which is configured on the substrate and located above the channel region; a first doping region of a first doping type, which is located on a first side of the gate structure; a second doping region of the first doping type, which is located on a second side of the gate structure; a shallow trench isolation structure, which is configured on an opposite side of the gate structure as the first doping region, and the shallow trench isolation structure has a bottom surface at a first depth below the top surface of the substrate; and a shallow trench isolation structure, which extends from the second doping region to the gate structure, and the shallow trench isolation structure has a bottom surface at a second depth below the top surface of the substrate, wherein the second depth is less than the first depth.

[0004] The present invention provides an integrated circuit component, which includes a substrate; a conductive gate configured on the substrate; a gate dielectric layer separating the conductive gate from the substrate, and the gate dielectric layer has a first thickness; a first source / drain region located on a first side of the conductive gate; a second source / drain region located on a second side of the conductive gate; a shallow trench isolation structure adjacent to the first source / drain region, and the shallow trench isolation structure has a second thickness greater than the first thickness; and a shallow trench isolation structure located between the second source / drain region and the conductive gate, and the shallow trench isolation structure has a third thickness between the first thickness and the second thickness.

[0005] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A cross-sectional view of an integrated circuit chip having a shallow trench isolation (SSTI) structure below a gate structure in some embodiments is shown.

[0007] Figures 2A to 2FA cross-sectional view of an integrated circuit chip according to some other embodiments is shown, wherein the integrated circuit chip has an SSTI structure below the gate structure.

[0008] Figures 3A to 3B A cross-sectional view of an integrated circuit chip according to some embodiments is shown, which has an SSTI structure separating a gate structure from a substrate.

[0009] Figures 4A to 4D Some parameter diagrams of an integrated circuit chip are depicted, wherein the integrated circuit chip in some embodiments has an SSTI structure under the gate structure.

[0010] Figures 5 to 28 A cross-sectional view of a method for forming an integrated chip having an SSTI structure below a gate structure in some embodiments is shown.

[0011] Figure 29 A flow chart of a method for forming an integrated chip having an SSTI structure below a gate structure in some embodiments is shown.

[0012] Description of Reference Numerals

[0013] 100, 200a, 200a-200f, 200b, 200d, 200e, 300a, 300b, 500, 500-800, 600, 700, 800, 900, 900-1200, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 1900-2000, 2000, 2100, 2200, 2300, 2400, 2500, 2600, 2700, 2800: Cross-sectional view

[0014] 102: substrate

[0015] 104: Gate structure

[0016] 104e: First gate edge

[0017] 106: Conductive gate

[0018] 108: Gate dielectric layer

[0019] 110: Spacer

[0020] 112: Second source / drain region

[0021] 114: First high voltage well

[0022] 116: First source / drain region

[0023] 118: First Main Area

[0024] 119: Field board

[0025] 120: STI structure

[0026] 120L, 122L: bottom surface

[0027] 122: SSTI structure

[0028] 124: Second main area

[0029] 126: The first shallow well

[0030] 127: Second high voltage well

[0031] 128: Contact conductor

[0032] 130: Dielectric layer

[0033] 132: First wiring level

[0034] 134: Resistor protective oxide layer

[0035] 136: Connecting source wire

[0036] 138, 230: Area

[0037] 140: Channel area

[0038] 200c: Top view

[0039] 200f, 400a, 400b, 400c, 400d: Chart

[0040] 202: Second Ring Area

[0041] 204: Second shallow ring

[0042] 206: The First Deep Well

[0043] 208: The Second Deepest Well

[0044] 210: First annular area

[0045] 212: First shallow ring

[0046] 217: First high-voltage MOS device

[0047] 218: Second high-voltage MOS device

[0048] 220: Hafnium oxide layer

[0049] 224: First voltage line

[0050] 226: Second voltage line

[0051] 228: Third voltage line

[0052] 232: Difference

[0053] 234: First doping profile

[0054] 236: Second doping profile

[0055] 302: First source / drain well

[0056] 304: Second source / drain well

[0057] 402: First Line

[0058] 404: Second Line

[0059] 406: Third Line

[0060] 408: Fourth Line

[0061] 410: Fifth Line

[0062] 412: Sixth Line

[0063] 414: Seventh Line

[0064] 416: Eighth Line

[0065] 418: Ninth Line

[0066] 502: Pad oxide layer

[0067] 504: First nitride layer

[0068] 506: TEOS layer

[0069] 508: First anti-reflection layer

[0070] 510: First oxynitride layer

[0071] 602: First etching process

[0072] 604: First mask layer

[0073] 606: First Opening

[0074] 702: First conformal oxide layer

[0075] 902: Second nitride layer

[0076] 904: Second tetraethoxysilane layer

[0077] 906: Second anti-reflection layer

[0078] 908: Second Nitride Oxide Layer

[0079] 1002: Second etching process

[0080] 1004: Second mask layer

[0081] 1006: Second opening

[0082] 1102: Second conformal oxide layer

[0083] 1302: First implantation process

[0084] 1304: Third mask layer

[0085] 1306: Sacrificial oxide layer

[0086] 1402: Second implantation process

[0087] 1404: Fourth mask layer

[0088] 1502: The third implantation process

[0089] 1504: Fifth mask layer

[0090] 1602: The fourth implantation process

[0091] 1604: Sixth mask layer

[0092] 1702: Fifth Implantation Process

[0093] 1704: Seventh mask layer

[0094] 1802: Sixth Implantation Process

[0095] 1804: Eighth mask layer

[0096] 1902: Gate Materials

[0097] 1904: Gate dielectric materials

[0098] 2002: The third etching process

[0099] 2004: Ninth Mask Layer

[0100] 2102: Conformal spacer layer

[0101] 2202: Fourth etching process

[0102] 2302: Seventh Implantation Process

[0103] 2304: Tenth mask layer

[0104] 2402: Eighth Implantation Process

[0105] 2404: Eleventh mask layer

[0106] 2502: Conformal resistor protection oxide 2602: Fifth etching process

[0107] 2604: twelfth mask layer

[0108] 2900: Flowchart

[0109] 2902, 2904, 2906, 2908, 2910: Action

[0110] a1: first angle

[0111] a2: second angle

[0112] d1: first depth

[0113] d2: second depth

[0114] t1: first thickness

[0115] t2: second thickness

[0116] t3: third thickness DETAILED DESCRIPTION

[0117] The following utility model provides many different embodiments or examples for realizing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the utility model. Of course, these are merely examples and are not intended to be limiting. As shown in the figure for example, forming a first feature or upper and second features in the description below may include an embodiment in which the first and second features are directly formed in contact, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be directly in contact. In addition, in various examples, the utility model may be repeated reference numbers and / or letters. This repetition is for the purpose of simplicity and clarity and does not itself specify the relationship between the various embodiments and / or architectures discussed.

[0118] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another component or feature(s), as shown in the figures. Spatially relative terms are intended to encompass different orientations of a component in use or operation in orientations other than those depicted in the figures. The device may be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0119] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are used in a variety of applications in integrated circuits, including memory, logic, and power control devices. Different uses for transistors require different amounts of power. Different types of MOSFETs are used to signal different power levels. For example, high-voltage (HVMOS) transistors are used in power applications and other higher voltage processes. Due to their smaller size and higher power efficiency, low-voltage (LVMOS) transistors are used in applications that can use lower power levels. Both LVMOS and HVMOS devices can be fabricated on the same chip, and the process flow can be integrated to address the thermal and process limitations of the different MOSFET types.

[0120] To further reduce the size and profile of HVMOS components, thereby increasing the number of components that can be accommodated on a chip, the thickness of the HVMOS component's gate dielectric layer can be reduced. While reducing the component's profile, the reduced thickness also increases the component's gate leakage and channel leakage. In some cases, the gate leakage of an HVMOS component with a reduced gate dielectric thickness can increase by approximately 200 times after reaching the breakdown voltage. Furthermore, the open-circuit current of an HVMOS component with a reduced gate dielectric thickness can increase by approximately 1000 times after reaching the breakdown voltage. This increase in leakage current and open-circuit current is primarily due to electron capture near the first gate edge of the gate, which is caused by a combination of a high impact ionization rate and a voltage differential between the gate and the underlying substrate. This change in leakage current can lead to inconsistent and erroneous readings in the circuits where the HVMOS component is located, and can result in inefficient power usage. Therefore, it is desirable to have a component that can maintain a thinner gate dielectric layer while reducing the impact of reaching the breakdown voltage. Furthermore, after doping of the LVMOS component is completed, additional thermal processes may adversely affect the LVMOS components in the same chip. Therefore, it is desirable to have a component that can reduce the impact of reaching the breakdown voltage without adding a thermal process after the doping process.

[0121] The present invention provides an integrated circuit component including an SSTI structure positioned below a gate dielectric layer. The SSTI structure is disposed below a first gate edge of the gate structure and is located between the first gate edge and the source / drain regions of the component. The addition of the SSTI structure displaces the substrate below the first gate edge to increase the distance between the conductive gate and the substrate below the first gate edge. The SSTI structure effectively extends the gate dielectric layer into the substrate, providing the advantages of a thicker gate dielectric layer at the first gate edge.

[0122] Furthermore, with the addition of the SSTI structure, a new point of highest impact ionization occurs in the region at the edge of the SSTI structure. The larger distance between this region and the source / drain regions, combined with interference from the SSTI structure and the gate extending beyond the SSTI structure, reduces the voltage differential between the conductive gate and the substrate. This lower voltage differential between the conductive gate and the substrate results in fewer electron and hole traps forming in this region when the breakdown voltage is applied, significantly reducing current leakage after the breakdown voltage is reached.

[0123] Figure 1 A cross-sectional view 100 of an integrated circuit chip is shown having an SSTI structure below a gate structure in some embodiments.

[0124] The gate structure 104 includes a gate dielectric layer 108 and a conductive gate 106 disposed above the substrate 102. The gate structure 104 is surrounded by spacers 110 and is separated from the gate structure 104 by a resistive protection oxide (RPO) layer 134 on one side. The gate structure 104 has a first gate edge 104e overlying the SSTI structure 122. The portion of the conductive gate 106 overlying the SSTI structure 122 acts as a field plate, resulting in a smaller electric field at the edge of the SSTI structure 122 than if the first gate edge 104e were located on or before the SSTI structure 122. The STI structure 120 is located on an opposite side of the gate structure 104, opposite the SSTI structure 122. The first source / drain region 116 is adjacent to the STI structure 120, and the second source / drain region 112 is separated from the gate structure 104 by the SSTI structure 122. The first source / drain region 116 and the second source / drain region 112 are doped regions of a first doping type (eg, positive doping).

[0125] The first high voltage well 114 surrounds the second source / drain region 112 and the SSTI structure 122. A first shallow well 126 surrounds portions of the STI structure 120 and extends between the first source / drain region 116 and the first high voltage well 114. The first shallow well 126 separates the first source / drain region 116 from the first high voltage well 114 to form a channel region 140 below the gate structure 104. The first high voltage well 114 has a first doping type, and the first shallow well 126 has a second doping type that is different from the first doping type (e.g., negative doping). The first body region 118 and the second body region 124 are located above the first shallow well 126 and have the second doping type. The second high voltage well 127 extends directly below the first high voltage well 114 and has the second doping type.

[0126] A dielectric layer 130 covers the gate structure 104 and the substrate 102. A contact conductor 128 connects the first source / drain region 116, the second source / drain region 112, the first body region 118, and the second body region 124 to a first wiring level 132. In some embodiments, the first wiring level 132 includes a butted-source wire 136 coupled to the first body region 118, the second body region 124, and the first source / drain region 116. In some embodiments, the first wiring level 132 includes a plurality of field plates 119 overlying the gate structure 104. In other embodiments, the field plates 119 are electrically coupled to the conductive gate 106 and terminate on the SSTI structure 122. The field plates 119 cooperate with the portion of the conductive gate 106 overlying the SSTI structure 122 to further increase the breakdown voltage and change the shape of the electromagnetic field.

[0127] The gate dielectric layer 108 has a first thickness t1. The SSTI structure 122 has a second thickness t2 that is greater than the first thickness t1. The greater thickness of the SSTI structure 122 can result in a greater distance between the channel region 140 and the first gate edge 104e, thereby improving insulation between the first gate edge 104e and the first high voltage well 114 and moving the region 138 with the highest impact ionization away from the first gate edge 104e (e.g., by eliminating regions with higher impact ionization at the first gate edge). A second thickness t2 that is too low (e.g., equal to or less than the first thickness t1) will maintain a region with higher impact ionization directly below the gate edge, resulting in higher gate leakage during operation, similar to embodiments without the SSTI structure 122. The STI structure 120 has a third thickness t3 that is greater than the second thickness t2. The STI structure 120 has a greater thickness than the SSTI structure 122 to more effectively block charge transfer between different doping regions. If the second thickness t2 is too high (e.g., equal to or greater than the third thickness t3), the SSTI structure 122 will block the first high voltage well 114 and alter the ability of the conductive gate 106 to function as a field plate, thereby reducing device performance. Specifically, the SSTI structure 122 has a second thickness t2 that is greater than the first thickness t1 of the gate dielectric layer 108 and less than the third thickness t3 of the STI structure 120.

[0128] SSTI structure 122 extends beneath gate structure 104 to cover the portion of substrate 102 beneath first gate edge 104e. The location of SSTI structure 122 reduces the number of electron and hole traps that form beneath first gate edge 104e. Electron and hole traps form due to a combination of higher impact ionization beneath first gate edge 104e, the voltage differential between conductive gate 106 and the high impact ionization region, and the high drain voltage caused by breakdown of gate dielectric layer 108. By replacing the portion of substrate 102 closest to first gate edge 104e with SSTI structure 122, electron and hole traps are substantially prevented from forming at that location within substrate 102. With the addition of SSTI structure 122, region 138 at the edge of SSTI structure 122 becomes the portion of substrate 102 with the highest impact ionization. In devices with reduced gate dielectric layer 108 thickness and without SSTI structure 122, impact ionization in region 138 is lower than at first gate edge 104e. The highest voltage differential between the conductive gate 106 and the substrate 102 in the assembly is located below the first gate edge 104e. Region 138 is spaced apart from the first gate edge 104e of the gate structure 104, resulting in a lower voltage differential at region 138 between the conductive gate 106 and the substrate 102. The spacing of the first gate edge 104e from the substrate, the reduction in voltage differential, and the rate of impact ionization at region 138 reduce the number of traps generated by the applied breakdown voltage.

[0129] Figures 2A to 2F Cross-sectional views 200 a - 200 f of integrated circuit chips are shown in some other embodiments, each having an SSTI structure below a gate structure.

[0130] like Figure 2A As shown in cross-sectional view 200a, in some embodiments, two or more HVMOS components share a single source / drain region on a chip. For example, a first HVMOS component 217 and a second HVMOS component 218 can be disposed around the second source / drain region 112. A first shallow ring 212 of the second doping type surrounds the first HVMOS component 217 and the second HVMOS component 218. A second shallow ring 204 of the first doping type extends between the first shallow ring 212 and the first HVMOS component 217 and the second HVMOS component 218. A first annular region 210 covers the first shallow ring 212, and a second annular region 202 covers the second shallow ring 204. A contact conductor 128 couples the first annular region 210 and the second annular region 202 to the first wiring level 132.

[0131] In some embodiments, a first deep well 206 of a first doping type is disposed below the second shallow ring 204. A second deep well 208 is disposed below the first deep well 206 and extends directly below the first HVMOS device 217 and the second HVMOS device 218. The first deep well 206 and the second deep well 208 surround the first HVMOS device 217 and the second HVMOS device 218 and electrically isolate the first HVMOS device 217 and the second HVMOS device 218 from other components in the substrate 102.

[0132] like Figure 2B As shown in the cross-sectional view 200b of FIG, the first source / drain region 116, the second source / drain region 112, the first high voltage well 114, the second high voltage well 127, the first shallow well 126, the first body region 118, and the second body region 124 can have different doping types than previously described. For example, the first shallow well 126, the first body region 118, the second body region 124, and the second high voltage well 127 can have a first doping type, while the first source / drain region 116, the second source / drain region 112, and the first high voltage well 114 can have a second doping type. In other embodiments, the second shallow ring can be omitted (see FIG. Figure 2A 204 in) and the second annular region (see Figure 2A 202 in the figure). In addition, the second high voltage well 127 can extend to the second deep well 208. In addition, the first deep well 206 can extend from the first shallow well 126 to the second deep well 208.

[0133] The SSTI structure 122 has a bottom surface 122L located at a first depth d1 below the top surface of the substrate 102. The STI structure 120 has a bottom surface 120L located at a second depth d2 below the top surface of the substrate 102. The second depth d2 is greater than the first depth d1. If the first depth d1 is equal to or greater than the second depth d2, the SSTI structure 122 will hinder charge transfer between the channel region 140 and the second source / drain region 112 and alter the ability of the conductive gate 106 to function as a field plate, thereby reducing device performance. In some embodiments, the top surface of the SSTI structure 122 and the top surface of the STI structure 120 are approximately at the top surface of the substrate 102. The SSTI structure 122 further has a first angle a1 between the sidewalls of the substrate 102 and the bottom surface 122L. The STI structure 120 has a second angle a2 between the sidewalls of the substrate 102 and the bottom surface 120L. The first angle a1 is less than the second angle a2. A first doping profile 234 measured under the SSTI structure 122 is different from a second doping profile 236 measured under the gate dielectric layer 108 within the first high voltage well 114. In some embodiments, the first wiring level 132 has a field plate 119 extending over the gate structure 104. The field plate 119 extends over and terminates the SSTI structure 122, and in some embodiments, the field plate 119 is electrically coupled to the conductive gate 106. The field plate is configured to distribute an electric field to the substrate 102 and increase the breakdown voltage.

[0134] like Figure 2C As shown in top view 200c of FIG, second annular region 202 surrounds first HVMOS device 217 and second HVMOS device 218. Furthermore, second body region 124 surrounds first HVMOS device 217 and second HVMOS device 218. First annular region 210 surrounds second annular region 202 and second body region 124. First HVMOS device 217 and second HVMOS device 218 are located within a central region defined by second body region 124. First body region 118 and first source / drain region 116 are located on opposite sides of the central region and are separated from second source / drain region 112 by SSTI structure 122 and conductive gate 106.

[0135] like Figure 2D As shown in the cross-sectional view 200d of FIG. 1 , the first angle a1 is between about 45 degrees and 65 degrees, between about 40 degrees and 60 degrees, between about 50 degrees and 70 degrees, or other suitable angle ranges. Within the angle range, a decrease in the first angle a1 results in a higher breakdown voltage of the HVMOS component than a component with a larger angle. In other words, the first angle a1 is negatively correlated with a higher breakdown voltage. The range of the first angle a1 is lower than that of the conventional STI structure (see FIG. Figure 1The angle of 120 can also reduce voltage differentials near the edge of the SSTI structure 122, thereby increasing the reliability of the HVMOS device. In some embodiments, the gate dielectric layer 108 is an oxide extending above the SSTI structure 122 and the first high voltage well 114. In some embodiments, the gate dielectric layer 108 is separated from the conductive gate 106 by a hafnium oxide layer 220. In some embodiments, the gate dielectric layer 108 has multiple upper surfaces.

[0136] like Figure 2E As shown in the cross-sectional view 200e of , the region 138 is depicted in more detail. In some embodiments, due to the addition of the SSTI structure 122, the voltage difference between the conductive gate 106 and the substrate 102 is mainly gate-to-substrate coupling rather than gate-to-drain coupling. The first voltage line 224, the second voltage line 226, and the third voltage line 228 depict the voltage contour of the component in the region 138. The difference between the first voltage line 224 and the second voltage line 226 is approximately 1 volt, and the difference between the second voltage line 226 and the third voltage line 228 is approximately 1 volt. Region 230 depicts the location of the highest impact ionization in the channel of the HVMOS component. In some embodiments, the impact ionization is approximately between 10 24 (1 / ((cm 3 )(s)) and 10 26 (1 / ((cm 3 )(s))) between, 10 25 (1 / ((cm 3 )(s)) and 10 27 (1 / ((cm 3 )(s)) between 10 22 (1 / ((cm 3 )(s)) and 10 25 (1 / ((cm 3 )(s))), or other similar ranges.

[0137] like Figure 2FAs shown in the graph 200f of FIG. 2 , the electron potential from the conductive gate 106 to the substrate varies. The electron potential is close to 0 in the conductive gate 106, drops sharply at the hafnium oxide layer 220, remains low throughout the gate dielectric layer 108, and rises at the top surface of the first high voltage well 114. In some embodiments, the difference 232 between the electron potential of the conductive gate 106 and the electron potential of the first high voltage well 114 is approximately between 1.5 volts and 2 volts, between 1.7 volts and 2.5 volts, between 1 volt and 1.7 volts, or in other similar ranges. The region (see FIG. 2 ) is substantially zero. Figure 2E 138) will be lower than that without SSTI structure (see Figure 2E The electron potential difference in the region of highest impact ionization in the HVMOS device (122 in FIG. 1 ) is shown. When providing a breakdown voltage, the lower difference 232 can result in a Figure 1 102) lesser amount of damage.

[0138] Figures 3A to 3B A cross-sectional view of an integrated circuit chip according to some embodiments is shown, which has an SSTI structure separating a gate structure from a substrate.

[0139] like Figure 3A As shown in cross-sectional view 300a of FIG. 1 , the SSTI structure 122 may cover the bottom surface of the gate dielectric layer 108. The SSTI structure 122 separates the gate structure 104 from the substrate 102, thereby mitigating leakage current from gate and dielectric breakdown. In some embodiments, the first source / drain region 116 and the second source / drain region 112 symmetrically surround the gate structure 104. The first source / drain region 116 and the second source / drain region 112 have a first source / drain well 302 and a second source / drain well 304, respectively. The first source / drain well 302 and the second source / drain well 304 have the second doping type. The first source / drain well 302 and the second source / drain well 304 are separated by a channel region 140, wherein the channel region 140 has the first doping type. The first body region 118 and the first shallow well 126 are adjacent to the first source / drain well 302 and the second source / drain well 304 , and the first body region 118 and the first shallow well 126 have the first doping type.

[0140] like Figure 3BAs shown in cross-sectional view 300b of FIG, the first source / drain region 116, the second source / drain region 112, the first source / drain well 302, the second source / drain well 304, the channel region 140, the first body region 118, and the first shallow well 126 may have different doping types than previously described. For example, the first source / drain region 116, the second source / drain region 112, the first source / drain well 302, and the second source / drain well 304 may have a first doping type, and the channel region 140, the first body region 118, and the first shallow well 126 may have a second doping type. In some embodiments, a second high voltage well is included below the channel region 140 and extends from a first side of the first shallow well 126 to a second side of the first shallow well 126.

[0141] like Figure 4A As shown in the graph 400a in , it illustrates the relationship between the drain current and the drain voltage of the HVMOS component in the off state. The first line 402 illustrates the relationship between the drain current and the drain voltage before the breakdown voltage is provided to the component. The second line 404, the third line 406, the fourth line 408 and the fifth line 410 respectively illustrate the relationship between the drain current and the drain voltage after the breakdown voltage is provided to the component once, twice, three times and four times. As shown in the figure, the drain current does not increase significantly after the breakdown voltage is provided. In some embodiments, after the provided drain voltage range reaches the breakdown voltage 4 times or more, the drain current can increase by about 2.7 times the original drain current. At higher drain voltages, the drain current decreases compared to the first line 402 where no breakdown voltage is provided. This is for HVMOS components that do not have SSTI structures (see Figure 1 122), the drain current may be increased by more than 1000 times compared to the drain current before the breakdown voltage is provided.

[0142] like Figure 4B , which depicts the relationship between gate voltage and drain current. A sixth line 412 depicts the relationship between gate voltage and drain current before applying the breakdown voltage, and a seventh line 414 depicts the relationship between gate voltage and drain current after applying the breakdown voltage. As shown in the figure, after applying the breakdown voltage, it can be seen that the drain current increases slightly at higher gate voltages.

[0143] like Figure 4C4, which depicts the relationship between the gate voltage and the gate current. The eighth line 416 depicts the relationship between the gate voltage and the gate current before the breakdown voltage is provided, and the ninth line 418 depicts the relationship between the gate voltage and the gate current after the breakdown voltage is provided. As shown in the figure, for a range of gate voltages, the gate current is greater after the breakdown voltage is provided. In some embodiments, the maximum gate current after the breakdown voltage is provided is approximately 4 to 5 times greater than the maximum gate current before the breakdown voltage is provided. The increase in the maximum gate current to between 4 and 5 times the original maximum gate current is for HVMOS components that do not have an SSTI structure (see Figure 1 122), while the maximum gate current of the HVMOS component without the SSTI structure may be increased to more than 200 times the original maximum gate current.

[0144] like Figure 4D As shown in Figure 400d, the SSTI structure (see Figure 2B 122) below the first doping profile 234 (eg Figure 2B shown) and gate structures (see Figure 2B 104) below the second doping profile 236 (eg Figure 2B shown) through the SSTI structure (see Figure 2B 122) is plotted as a graph. As shown, the second doping profile 236 is non-constant and has a maximum dopant concentration near the upper surface of the substrate 102 that is greater than the maximum dopant concentration of the first doping profile 234. In some embodiments, the maximum dopant concentration of the second doping profile 236 is approximately twice the maximum dopant concentration of the first doping profile 234.

[0145] Figures 5 to 28 A cross-sectional view of a method for forming an integrated chip having an SSTI structure below a gate structure in some embodiments is depicted. Figures 5 to 28 It is described in terms of method, but it should be understood that Figures 5 to 28 The structure described in is not limited to being produced by this method, but can exist independently as a structure independent of the method.

[0146] like Figure 5As shown in cross-sectional view 500 in FIG, a substrate 102 is provided. A pad oxide layer 502 is formed on the substrate 102. In some embodiments, the pad oxide layer 502 is a thermal oxide. A first nitride layer 504 is formed on the pad oxide layer 502. A first tetraethyl orthosilicate (TEOS) layer 506 is formed on the first nitride layer 504. A first anti-reflective layer 508 is formed on the first tetraethoxysilane layer 506. A first oxynitride layer 510 is formed on the first anti-reflective layer 508. In some embodiments, the first nitride layer 504, the first tetraethoxysilane layer 506, the first anti-reflective layer 508, and the first oxynitride layer 510 are formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), some other suitable deposition process, or a combination of the foregoing processes. In some embodiments, the first nitride layer 504 is or includes silicon nitride (Si3N4), etc. In some embodiments, the first oxynitride layer 510 includes silicon oxynitride (N2OSi2), etc.

[0147] like Figure 6 As shown in the cross-sectional view 600 of FIG, a first mask layer 604 is formed on the first oxynitride layer 510. In some embodiments, the first mask layer 604 is a photoresist. Then, the first mask layer 604 is patterned. In some embodiments, the first mask layer 604 is patterned using a photolithography process.

[0148] Then, a first etching process 602 is performed. During the first etching process 602, the first oxynitride layer 510, the first antireflective layer 508, the first tetraethoxysilane layer 506, the first nitride layer 504, the pad oxide layer 502, and the substrate 102 are etched in the areas exposed by the first mask layer 604. In some embodiments, the first etching process 602 may be a dry etch, such as a plasma etch. The first etching process 602 results in the formation of a first opening 606 in the substrate 102. The first opening 606 extends to a first depth d1 within the substrate 102. The first mask layer 604 is subsequently removed.

[0149] like Figure 7As shown in cross-sectional view 700 in FIG, a first conformal oxide layer 702 is deposited on the upper surface of the first oxynitride layer 510 to fill the first opening 606 (shown as a dashed line). In some embodiments, the first conformal oxide layer 702 can be deposited using one of thermal oxidation, CVD, PVD, ALD, some other suitable deposition process, or a combination of the foregoing processes. In some embodiments, the first conformal oxide layer 702 includes a lining oxide formed using thermal oxidation and a high aspect ratio process (HARP) oxide deposited using CVD. In some embodiments, the first conformal oxide layer 702 is or includes silicon dioxide (SiO2).

[0150] like Figure 8 As shown in the cross-sectional view 800, the first oxynitride layer 510 (see Figure 7 ), the first anti-reflection layer 508 (see Figure 7 ), the first tetraethoxysilane layer 506 (see Figure 7 ), the first nitride layer 504 (see Figure 7 ) is removed to expose the upper surface of the pad oxide layer 502. In some embodiments, a planarization process (eg, a chemical mechanical planarization (CMP) process) is used to remove the first oxynitride layer 510 (see Figure 7 ), the first anti-reflection layer 508 (see Figure 7 ) and the first tetraethoxysilane layer 506 (see Figure 7 In other embodiments, after the planarization process, phosphoric acid (H3PO4) is used to remove the first nitride layer 504. A portion of the first conformal oxide layer 702 above the pad oxide layer 502 is removed due to the planarization process (see Figure 7 ) results in the SSTI structure 122 remaining in the substrate 102 .

[0151] like Figure 9 As shown in cross-sectional view 900 in FIG. , a second nitride layer 902 is formed over the pad oxide layer 502. A second tetraethoxysilane layer 904 is formed over the second nitride layer 902. A second antireflective layer 906 is formed over the second tetraethoxysilane layer 904. A second oxynitride layer 908 is formed over the second antireflective layer 906. In some embodiments, the second nitride layer 902, the second tetraethoxysilane layer 904, the second antireflective layer 906, and the second oxynitride layer 908 are formed using CVD, PVD, ALD, or some other suitable deposition process, or a combination thereof. In some embodiments, the second nitride layer 902 is or includes silicon nitride (Si3N4), etc. In some embodiments, the second oxynitride layer 908 includes silicon oxynitride (N2OSi2), etc.

[0152] like Figure 10 As shown in cross-sectional view 1000 in FIG, a second mask layer 1004 is formed on the second oxynitride layer 908. In some embodiments, the second mask layer 1004 is a photoresist. Then, the second mask layer 1004 is patterned. In some embodiments, the second mask layer 1004 is patterned using a photolithography process.

[0153] Then, a second etching process 1002 is performed. During the second etching process 1002, the second oxynitride layer 908, the second antireflective layer 906, the second tetraethoxysilane layer 904, the second nitride layer 902, the pad oxide layer 502, and the substrate 102 are etched in the areas exposed by the second mask layer 1004. In some embodiments, the second etching process 1002 may be a dry etch, such as a plasma etch. The second etching process 1002 results in the formation of a second opening 1006 in the substrate 102. The second opening 1006 extends to a second depth d2 within the substrate 102. The second mask layer 1004 is then removed.

[0154] like Figure 11 As shown in the cross-sectional view 1100 of FIG, a second conformal oxide layer 1102 is deposited on the upper surface of the second oxynitride layer 908 to fill the second opening 1006 (shown as a dotted line). In some embodiments, the second conformal oxide layer 1102 can be deposited using one of thermal oxidation, CVD, PVD, ALD, some other suitable deposition process, or a combination of the foregoing processes. In some embodiments, the second conformal oxide layer 1102 includes a liner oxide formed using thermal oxidation and a high aspect ratio process (HARP) oxide deposited using CVD. In some embodiments, the second conformal oxide layer 1102 is or includes silicon dioxide (SiO2) or the like. In some embodiments, the second conformal oxide layer 1102 includes the same material as the first conformal oxide layer (see FIG. Figure 7 702).

[0155] like Figure 12 As shown in the cross-sectional view 1200, the second oxynitride layer 908 is removed (see Figure 11 ), the second anti-reflection layer 906 (see Figure 11 ), the second tetraethoxysilane layer 904 (see Figure 11 ), the second nitride layer 902 (see Figure 11 ) to expose the upper surface of the pad oxide layer 502. In some embodiments, a planarization process (eg, a CMP process) is used to remove the second oxynitride layer 908 (see Figure 11 ), the second anti-reflection layer 906 (see Figure 11 ) and a second tetraethoxysilane layer 904 (see Figure 11In other embodiments, after the planarization process, phosphoric acid (H3PO4) is used to remove the second nitride layer 902. A portion of the second conformal oxide layer 1102 above the pad oxide layer 502 is removed due to the planarization process (see Figure 11 ) results in the STI structure 120 remaining in the substrate 102 .

[0156] like Figure 13 As shown in cross-sectional view 1300 in FIG, a sacrificial oxide layer 1306 is formed on substrate 102. A third mask layer 1304 is formed on sacrificial oxide layer 1306. In some embodiments, third mask layer 1304 is a photoresist. Third mask layer 1304 is then patterned. In some embodiments, third mask layer 1304 is patterned using a photolithography process. A first implantation process 1302 is then performed. First implantation process 1302 implants dopants according to the pattern of third mask layer 1304, thereby forming first deep well 206 of the first doping type. Third mask layer 1304 is subsequently removed.

[0157] like Figure 14 As shown in cross-sectional view 1400 in FIG, a fourth mask layer 1404 is formed over the sacrificial oxide layer 1306. In some embodiments, the fourth mask layer 1404 is a photoresist. The fourth mask layer 1404 is then patterned. In some embodiments, the fourth mask layer 1404 is patterned using a photolithography process. A second implantation process 1402 is then performed. The second implantation process 1402 implants dopants according to the pattern of the fourth mask layer 1404 to form a second deep well 208 of the first doping type below the first deep well 206. The fourth mask layer 1404 is then removed.

[0158] like Figure 15 As shown in cross-sectional view 1500 in FIG, a fifth mask layer 1504 is formed over the sacrificial oxide layer 1306. In some embodiments, the fifth mask layer 1504 is a photoresist. The fifth mask layer 1504 is then patterned. In some embodiments, the fifth mask layer 1504 is patterned using a photolithography process. A third implantation process 1502 is then performed. The third implantation process 1502 implants dopants according to the pattern of the fifth mask layer 1504 to form a first high voltage well 114 of the first doping type surrounding the SSTI structure 122. The fifth mask layer 1504 is subsequently removed.

[0159] like Figure 16As shown in cross-sectional view 1600 in FIG, a sixth mask layer 1604 is formed over the sacrificial oxide layer 1306. In some embodiments, the sixth mask layer 1604 is a photoresist. The sixth mask layer 1604 is then patterned. In some embodiments, the sixth mask layer 1604 is patterned using a photolithography process. A fourth implantation process 1602 is then performed. The fourth implantation process 1602 implants dopants according to the pattern of the sixth mask layer 1604 to form a second high voltage well 127 of a second doping type directly below the first high voltage well 114 of a first doping type. The sixth mask layer 1604, the sacrificial oxide layer 1306, and the pad oxide layer 502 are then removed.

[0160] like Figure 17 As shown in cross-sectional view 1700 in FIG, a seventh mask layer 1704 is formed over substrate 102. In some embodiments, seventh mask layer 1704 is a photoresist. Seventh mask layer 1704 is then patterned. In some embodiments, seventh mask layer 1704 is patterned using a photolithography process. A fifth implantation process 1702 is then performed. Fifth implantation process 1702 implants dopants according to the pattern of seventh mask layer 1704 to form a first shallow well 126 of the second doping type and a first shallow ring 212 surrounding first high voltage well 114. Seventh mask layer 1704 is subsequently removed.

[0161] like Figure 18 As shown in cross-sectional view 1800 in FIG, an eighth mask layer 1804 is formed over substrate 102. In some embodiments, eighth mask layer 1804 is a photoresist. Eighth mask layer 1804 is then patterned. In some embodiments, eighth mask layer 1804 is patterned using a photolithography process. A sixth implantation process 1802 is then performed. Sixth implantation process 1802 implants dopants according to the pattern of eighth mask layer 1804 to form a second shallow ring 204 of the first doping type surrounding first shallow well 126 and directly above first deep well 206. Eighth mask layer 1804 is subsequently removed.

[0162] like Figure 19 As shown in cross-sectional view 1900 of , gate dielectric material 1904 and gate material 1902 are deposited over substrate 102. In some embodiments, gate dielectric material 1904 is or includes an oxide, a high-k dielectric, etc. In some embodiments, gate material 1902 is or includes polysilicon, a metal, etc.

[0163] like Figure 20As shown in the cross-sectional view 2000 of FIG, a ninth mask layer 2004 is formed over the gate material 1902. In some embodiments, the ninth mask layer 2004 is a photoresist. Then, the ninth mask layer 2004 is patterned. In some embodiments, the ninth mask layer 2004 is patterned using a photolithography process.

[0164] Then, a third etching process 2002 is performed. During the third etching process 2002, the gate dielectric material is etched in the area exposed by the ninth mask layer 2004 (see FIG. Figure 19 1904) and gate materials (see Figure 19 1902). In some embodiments, the third etch process 2002 can be a dry etch, such as a plasma etch. The third etch process 2002 forms the gate dielectric layer 108 and the conductive gate 106 remaining on the substrate 102, with the gate dielectric layer 108 and the conductive gate 106 having a first gate edge 104e directly above the SSTI structure 122. In some embodiments, the portion of the gate structure 104 directly above the SSTI structure 122 has a length between approximately 0.01 microns and 90% of the length of the SSTI structure 122. Subsequently, the ninth mask layer 2004 is removed.

[0165] In some embodiments, the first thickness t1 of the gate dielectric layer 108 is between approximately 20 angstroms and 100 angstroms, between approximately 10 angstroms and 70 angstroms, between approximately 30 angstroms and 150 angstroms, or another suitable range. In some embodiments, the second thickness t2 of the SSTI structure 122 is between approximately 200 angstroms and 1200 angstroms, between approximately 150 and 900 angstroms, between 250 and 1500 angstroms, or another suitable range. In some embodiments, the third thickness t3 of the STI structure 120 is between approximately 2000 angstroms and 4500 angstroms, between approximately 1600 and 3600 angstroms, between 2400 and 5400 angstroms, or another suitable range.

[0166] like Figure 21 As shown in the cross-sectional view 2100 of FIG, a conformal spacer layer 2102 is deposited on the substrate 102. In some embodiments, the conformal spacer layer 2102 is or includes an insulating material, such as an oxide (eg, silicon oxide).

[0167] like Figure 22 As shown in the cross-sectional view 2200 of FIG. 2 , a fourth etching process 2202 is performed to remove the conformal spacer layer (see FIG. Figure 21 2102) without removing the conformal spacer layer (see Figure 21 The remaining vertical portions (eg, portions located on the sidewalls of the conductive gate 106 and the gate dielectric layer 108 ) form spacers 110 .

[0168] like Figure 23 As shown in cross-sectional view 2300 of FIG, a tenth mask layer 2304 is formed over substrate 102. In some embodiments, tenth mask layer 2304 is a photoresist. Tenth mask layer 2304 is then patterned. In some embodiments, tenth mask layer 2304 is patterned using a photolithography process. Then, a seventh implantation process 2302 is performed. Seventh implantation process 2302 implants dopants according to the pattern of tenth mask layer 2304 to form first body region 118, second body region 124, and first ring region 210 of the second doping type in first shallow well 126 and first shallow ring 212. Tenth mask layer 2304 is subsequently removed.

[0169] like Figure 24 As shown in the cross-sectional view 2400 of FIG, an eleventh mask layer 2404 is formed on the substrate 102. In some embodiments, the eleventh mask layer 2404 is a photoresist. The eleventh mask layer 2404 is then patterned. In some embodiments, the eleventh mask layer 2404 is patterned using a photolithography process. Then, an eighth implantation process 2402 is performed. The eighth implantation process 2402 implants dopants according to the pattern of the eleventh mask layer 2404 to form a first doped first source / drain region 116, a second source / drain region 112, and a second ring region 202 in the first shallow well 126, the first high voltage well 114, and the second shallow ring 204, respectively. The eleventh mask layer 2404 is subsequently removed.

[0170] like Figure 25 As shown in the cross-sectional view 2500 of , a conformal RPO 2502 is deposited on the substrate 102. In some embodiments, the conformal RPO 2502 is or includes an insulating material, such as an oxide (eg, silicon oxide).

[0171] like Figure 26 As shown in the cross-sectional view 2600 of FIG, a twelfth mask layer 2604 is formed on the substrate 102. In some embodiments, the twelfth mask layer 2604 is a photoresist. Then, the twelfth mask layer 2604 is patterned. In some embodiments, the twelfth mask layer 2604 is patterned using a photolithography process.

[0172] Then, a fifth etching process 2602 is performed. During the fifth etching process 2602, the conformal RPO (see Figure 252502) is etched in the area exposed by the twelfth mask layer 2604. In some embodiments, the fifth etching process 2602 can be dry etching, such as plasma etching. The fifth etching process 2602 forms an RPO layer 134 remaining on the substrate 102, and the RPO layer 134 extends along the sidewall of the spacer 110. From the cross-sectional view direction, the RPO layer 134 has an "L"-shaped profile. The twelfth mask layer 2604 is then removed. After removing the twelfth mask layer 2604, a silicide layer is formed over the substrate 102 and the conductive gate 106. The silicide layer is configured to reduce the substrate 102 and the contact conductor to be formed later (see Figure 28 The contact resistance between 128).

[0173] like Figure 27 As shown in the cross-sectional view 2700 of FIG. 2 , a dielectric layer 130 is formed on the substrate 102. In some embodiments, the dielectric layer 130 is or includes an oxide (e.g., silicon oxide (SiO2)). i In some embodiments, the dielectric layer 130 is formed using a deposition process (eg, a CVD process).

[0174] like Figure 28 As shown in cross-sectional view 2800 in FIG, contact conductor 128 and first wiring level 132 are formed in dielectric layer 130. In some embodiments, contact conductor 128 and first wiring level 132 include conductive materials such as copper (Cu), nickel (Ni), titanium (Ti), etc.

[0175] Figure 29 A flow chart 2900 is shown illustrating a method for forming an integrated chip having an SSTI structure below a gate structure in some embodiments.

[0176] Although method 2900 is illustrated and described as a series of actions or events below, it should be understood that the order of the aforementioned series of actions or events should not be interpreted as limiting. For example, some actions can occur in different orders and / or occur simultaneously with other actions or events other than those shown and / or described herein. In addition, in one or more aspects or embodiments described herein, not all illustrated actions need to be implemented. In addition, one or more actions described herein can be performed in one or more separate actions and / or stages.

[0177] At 2902 , a SSTI structure is formed in a substrate, and the SSTI structure has a first thickness. Figures 5 to 8 Cross-sectional views 500 - 800 corresponding to some embodiments of act 2902 are depicted.

[0178] At 2904 , an STI structure is formed in the substrate, spaced apart from the SSTI structure, and the STI structure has a second thickness greater than the first thickness. Figures 9 to 12 Cross-sectional views 900 - 1200 are depicted corresponding to some embodiments of act 2904 .

[0179] At 2906 , a gate structure is formed over the substrate between the STI structure and the SSTI structure, with the gate structure having a first gate edge overlying the SSTI structure. Figures 19 to 20 Cross-sectional views 1900 - 2000 are depicted corresponding to some embodiments of act 2906 .

[0180] At 2908 , a first source / drain region is formed between the STI structure and the gate structure adjacent to the STI structure. Figure 24 Cross-sectional view 2400 is depicted corresponding to some embodiments of act 2908 .

[0181] At 2910 , a second source / drain region is formed adjacent to the SSTI structure while the first source / drain region is formed, and the second source / drain region is separated from the first source / drain region by the SSTI structure and the gate structure. Figure 24 Cross-sectional view 2400 is depicted corresponding to some embodiments of act 2910 .

[0182] Therefore, the present invention is directed to a novel method for forming an integrated circuit chip having a plurality of capacitors with a plurality of bottom electrode structures having different depths and widths.

[0183] Accordingly, in some embodiments, the present invention relates to an integrated circuit component, which includes a substrate including a channel region; a gate structure configured on the substrate and located above the channel region; a first doping region of a first doping type located on a first side of the gate structure; a second doping region of the first doping type located on a second side of the gate structure; a shallow trench isolation structure configured on an opposite side of the gate structure as the first doping region, and the shallow trench isolation structure has a bottom surface located at a first depth below the top surface of the substrate; a shallow trench isolation structure extending from the second doping region to the gate structure, the shallow trench isolation structure having a bottom surface located at a second depth below the top surface of the substrate, wherein the second depth is less than the first depth.

[0184] In other embodiments, the present invention relates to an integrated circuit component, which includes a substrate; a conductive gate configured on the substrate; a gate dielectric layer separating the conductive gate from the substrate, and the gate dielectric layer has a first thickness; a first source / drain region located on a first side of the conductive gate; a second source / drain region located on a second side of the conductive gate; a shallow trench isolation structure adjacent to the first source / drain region, and the shallow trench isolation structure has a second thickness greater than the first thickness; a shallow trench isolation structure located between the second source / drain region and the conductive gate, and the shallow trench isolation structure has a third thickness between the first thickness and the second thickness.

[0185] In another embodiment, the present invention relates to a method for an integrated circuit component, which includes: receiving a substrate; forming a shallow trench isolation structure in the substrate, the shallow trench isolation structure having a first thickness; forming a shallow trench isolation structure separated from the shallow trench isolation structure in the substrate, the shallow trench isolation structure having a second thickness greater than the first thickness; forming a gate structure on the substrate between the shallow trench isolation structure and the shallow trench isolation structure, the gate structure having a first sidewall overlying the shallow trench isolation structure; forming a first source / drain region adjacent to the shallow trench isolation structure between the shallow trench isolation structure and the gate structure; and simultaneously with the formation of the first source / drain region, forming a second source / drain region adjacent to the shallow trench isolation structure, and the second source / drain region is separated from the first source / drain region by the shallow trench isolation structure and the gate structure.

[0186] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art will understand that they can easily use this invention as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that various changes, substitutions, and modifications can be made to such equivalent structures without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit component, characterized in that: include: a substrate including a channel region; a gate structure, disposed on the substrate and located above the channel region; a first doping region of a first doping type, located on a first side of the gate structure; a second doping region of the first doping type located on a second side of the gate structure; a shallow trench isolation structure disposed on an opposite side of the gate structure from the first doped region, wherein the first doped region has a bottom surface located at a first depth below a top surface of the substrate; as well as A shallow trench isolation structure extends from the second doped region to the gate structure, wherein the shallow trench isolation structure has a bottom surface located at a second depth below the top surface of the substrate. 2 . The integrated circuit device according to claim 1 , wherein the first sidewall of the gate structure overlies the shallow trench isolation structure. 3 . The integrated circuit device according to claim 2 , wherein the gate structure extends beyond an outer sidewall of the shallow trench isolation structure.

4. The integrated circuit component according to claim 1, wherein the shallow trench isolation structure has a plurality of sidewalls at a first angle to the bottom surface of the substrate, and the shallow trench isolation structure has a plurality of sidewalls at a second angle to the bottom surface of the substrate, and wherein the first angle is smaller than the second angle. The integrated circuit component according to claim 1 , wherein the second depth is smaller than the first depth.

6. An integrated circuit component comprising: substrate; a conductive gate, disposed on the substrate; a gate dielectric layer separating the conductive gate from the substrate, wherein the gate dielectric layer has a first thickness; a first source / drain region located on a first side of the conductive gate; a second source / drain region located on a second side of the conductive gate; A shallow trench isolation structure is adjacent to the first source / drain region and has a second thickness greater than the first thickness; as well as A shallow trench isolation structure is located between the second source / drain region and the conductive gate, and the shallow trench isolation structure has a third thickness between the first thickness and the second thickness. 7 . The integrated circuit device according to claim 6 , wherein the shallow trench isolation structure contacts the second source / drain region and the gate dielectric layer. 8 . The integrated circuit device according to claim 6 , further comprising a source / drain extension, the source / drain extension contacting the second source / drain region, and the source / drain extension extending between the shallow trench isolation structure and the shallow trench isolation structure. 9 . The integrated circuit device of claim 6 , further comprising a field plate extending above the conductive gate, the field plate terminating above the shallow trench isolation structure between the second source / drain region and the conductive gate.

10. The integrated circuit assembly according to claim 9, further comprising: a first source / drain contact conductor coupled to the first source / drain region; as well as A doped region is adjacent to the first source / drain region in contact with the first source / drain contact conductor, wherein the doped region has a positive doping.

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