Chip circuit suitable for frequency detection and power management chip

Abstract

The utility model provides a chip circuit suitable for frequency detection and a power management chip, relates to the technical field of electronic circuits, and solves the problem that a test device or a probe is easily damaged when a chip is directly tested under a heavy load condition in the related technology. The chip circuit comprises the feedback input module, the sequential logic module, the comparator module and the power driving module, the circuit is simple in structure and easy to implement, the chip circuit does not need a chip with heavy load, the damage risk of test equipment is effectively avoided, the test cost is reduced, excessive extra test steps are not needed, and the test efficiency is improved. And the test efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a chip circuit and a power management chip suitable for frequency detection. Background Art

[0002] In order to find unqualified chips before packaging and improve the yield rate before leaving the factory, after chip manufacturing and before packaging, the exposed chip pins of the whole wafer that has not been divided and packaged are connected to the test machine through probes, and then chip testing, such as CP (Chip Probing) testing, is performed.

[0003] Some important parameters about the chip must be tested before the chip is packaged, such as the operating frequency of the chip. Traditional chips only have a PWM (Pulse width modulation) mode that can directly measure the frequency. However, since the efficiency of the PWM mode is too low under light load, related technologies usually use two modes to detect the frequency, such as PFM (Pulse frequency modulation) / PWM mode, that is, it is in PFM mode under light load and in PWM mode under heavy load. However, the operating frequency is a stable value only in PWM mode, so it is necessary to test under heavy load. In the CP test stage, the chip on the wafer has not been packaged yet and is in a bare state. If a heavy load test is performed directly, it may place too much burden on the test probe and equipment, thereby damaging the test equipment or probe. Utility Model Content

[0004] The present application provides a chip circuit and a power management chip suitable for frequency detection, which solves the problem in related technologies that the test equipment or probes are easily damaged when the chip is directly tested under heavy load conditions. The chip circuit of the present application can measure the operating frequency of the chip in normal mode, effectively avoiding the risk of damage to the test equipment and reducing the cost of testing.

[0005] In a first aspect, the present application provides a chip circuit suitable for frequency detection, which includes a feedback input module, a timing logic module, a comparator module and a power driving module.

[0006] The first input terminal of the feedback input module serves as a voltage feedback pin of the chip circuit to receive the feedback voltage, and the second input terminal of the feedback input module serves as a test input pin of the chip circuit to receive the grounded control switch.

[0007] The input end of the timing logic module is connected to the output end of the feedback input module. The timing logic module is used to output a time series control signal in combination with the set signal output by the feedback input module.

[0008] The first input terminal of the comparator module is connected to the power switching output pin of the chip circuit, and the second input terminal of the comparator module is grounded;

[0009] The first input end of the power driving module is connected to the output end of the timing logic module, the second input end of the power driving module is connected to the output end of the comparator module, the power supply end of the power driving module serves as the power input pin of the chip circuit, and the output end of the power driving module serves as the power switching output pin of the chip circuit. The power driving module is used to determine the voltage signal on the power switching output pin according to the output of the timing logic module and the comparator module.

[0010] In a second aspect, the present application also provides a power management chip, which includes the chip circuit suitable for frequency detection provided in the first aspect above.

[0011] The chip circuit of this application can measure the chip's operating frequency in normal mode, and its circuit structure is simple and easy to implement. Furthermore, the chip circuit does not require the chip to be overloaded, effectively avoiding the risk of damage to the test equipment and reducing testing costs. It also eliminates the need for excessive additional testing steps, helping to improve test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A circuit structure diagram of a chip circuit suitable for frequency detection is provided for an embodiment of the present application;

[0013] Figure 2 A schematic diagram of a circuit for testing a chip circuit provided in one embodiment of the present application. DETAILED DESCRIPTION

[0014] The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and examples. It will be understood that the specific embodiments described herein are merely used to explain the embodiments of the present application, rather than to limit the embodiments of the present application. It should also be noted that, for ease of description, only portions related to the embodiments of the present application, rather than all structures, are shown in the accompanying drawings. After reading this specification, those skilled in the art should be able to understand that, as long as the technical features do not contradict each other, any combination of the technical features may constitute an optional embodiment.

[0015] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the description of this application, "multiple" means two or more, and "several" means one or more.

[0016] To identify defective chips before packaging and improve the yield rate, after wafer fabrication and before packaging, the exposed chip pins of the undivided wafer are connected to a tester using probes for chip testing, such as CP testing. CP testing involves multiple tasks, and these tests can uncover issues that might not be detected during functional testing, such as ESD (electrostatic discharge) damage. The primary challenge of CP testing lies in identifying and repairing defective chips as quickly as possible.

[0017] Testing plays a very important role in the entire chip production process, and testing costs also account for a large part of the production cost, about 15% to 20% of the total investment. Therefore, reasonable testing methods, concise testing processes, and reasonable testing algorithms can help reduce testing time and save testing costs.

[0018] Traditional chips only have one PWM (Pulse width modulation) mode to directly measure the frequency. However, because the efficiency of the PWM mode is too low under light load, related technologies usually use two modes to detect the frequency, such as PFM (Pulse frequency modulation) / PWM mode, that is, it is in PFM mode under light load and in PWM mode under heavy load. However, the operating frequency is a stable value only in PWM mode, so it is necessary to test under heavy load. In the CP test stage, the chip on the wafer has not been packaged yet and is in a bare state. If a heavy load test is performed directly, it may place too much burden on the test probe and equipment, thereby damaging the test equipment or probe.

[0019] To this end, the present application provides a chip circuit suitable for frequency testing. This chip circuit can accurately test the operating frequency of the chip without a load when a fixed voltage is applied externally. The chip circuit of the present application includes a feedback input module, a timing logic module, a comparator module, and a power drive module.

[0020] The first input of the feedback input module serves as the voltage feedback pin of the chip circuit, the second input of the feedback input module serves as the test input pin of the chip circuit, and the output of the feedback input module is connected to the input of the sequential logic module. The first input of the feedback input module is used to receive the feedback voltage, and the second input of the feedback input module is used to receive the grounded control switch. During testing, the first input of the feedback input module receives the feedback voltage, and the control switch is closed, so that the second input of the feedback input module receives a low level.

[0021] Optionally, in one embodiment, the feedback input module includes a comparator unit and a gate circuit unit, wherein the comparator unit includes two input terminals and the gate circuit unit includes three input terminals. The first input terminal of the comparator unit serves as the first input terminal of the feedback input module and is used to receive the feedback voltage. The second input terminal of the comparator unit receives the sampled voltage, and the output terminal of the comparator unit is connected to the first input terminal of the gate circuit unit. The comparator unit compares the received feedback voltage with the sampled voltage to provide an input signal to the gate circuit unit.

[0022] Furthermore, the second input of the gate unit serves as the second input of the feedback input module and is intended to be grounded or left floating. It is conceivable that the second input of the gate unit is connected to a grounded control switch. Therefore, during testing, when the control switch is closed, the second input of the gate unit is effectively grounded. The third input of the gate unit is connected to a minimum on-time signal, and the output of the gate unit is connected to the input of the sequential logic module. Logical operations are performed on the electrical signals received by the gate unit, providing a set signal to the sequential logic module, which then outputs the corresponding sequential control signal.

[0023] The timing logic module is connected to the feedback input module and the power drive module. The timing logic module is used to output a time series control signal in combination with the set signal output by the feedback input module. The first input end of the comparator module is connected to the power switching output pin of the chip circuit, and the second input end of the comparator module is grounded. Optionally, in one embodiment, the comparator module includes a second comparator, the first input end of the second comparator serves as the first input end of the comparator module, the first input end of the second comparator is connected to the output end of the first power switch tube, and the second input end of the second comparator is grounded.

[0024] The first input of the power driver module is connected to the output of the sequential logic module, and the second input of the power driver module is connected to the output of the comparator module. The power supply terminal of the power driver module serves as the power input pin of the chip circuit, and the output terminal of the power driver module serves as the power switching output pin of the chip circuit. The power driver module is used to determine the voltage signal on the power switching output pin based on the outputs of the sequential logic module and the comparator module. It is conceivable that by connecting this voltage signal to the test equipment through a probe, the operating frequency of the chip can be determined.

[0025] As can be seen from the above scheme, the chip circuit of the present application can measure the chip's operating frequency in normal mode, and the circuit structure is simple and easy to implement. In addition, the chip circuit does not require the chip to be overloaded, effectively avoiding the risk of damage to the test equipment, reducing testing costs, and eliminating the need for excessive additional testing steps, which helps improve test efficiency.

[0026] In one embodiment, the comparator unit includes an error amplifier and a first comparator. The positive input of the error comparator is connected to a reference voltage, while the negative input of the error amplifier serves as the first input of the comparator unit and is connected to a feedback voltage. The output of the error amplifier is connected to the non-inverting input of the first comparator. The inverting input of the first comparator serves as the second input of the comparator unit, and the inverting input of the first comparator is used to receive a sampling voltage. In addition, the output of the first comparator serves as the output of the comparator unit and is connected to the first input of the gate circuit unit.

[0027] It is understood that the error amplifier amplifies small signals by comparing input signals (such as the feedback voltage and the reference voltage mentioned above) to determine the difference between the two. The signal is then transmitted to the first comparator, which compares the signals and outputs a corresponding signal to the gate circuit unit.

[0028] Therefore, through the error amplifier and the first comparator, the chip circuit can utilize the provided feedback voltage to enable the chip circuit to stably output a corresponding voltage signal, thereby realizing detection of the operating frequency provided by the internal oscillator of the chip.

[0029] In one embodiment, the gate circuit unit includes an AND gate and a NOR gate, wherein the first input terminal of the AND gate is connected to the output terminal of the comparator unit, the second input terminal of the AND gate is connected to the power supply voltage through a pull-up resistor, and the second input terminal of the AND gate also serves as the second input terminal of the gate circuit unit, which is used to connect to the grounded control switch. It can be imagined that when testing, when the control switch is closed, the second input terminal of the AND gate is directly grounded.

[0030] The output of the AND gate is connected to the first input of the NOR gate. The AND gate performs an AND logic operation on the signals connected to its two inputs, providing the result of the logic operation to the NOR gate. Furthermore, the second input of the NAND gate serves as the third input of the gate circuit unit, receiving the minimum on-time signal. The output of the NAND gate is connected to the input of the sequential logic module. The NOR gate performs a NOR logic operation on the signals connected to its two inputs, providing the corresponding set signal to the sequential logic module, which then outputs the corresponding timing control signal.

[0031] Therefore, by connecting the AND gate and the NOR gate, and performing an AND logic operation on the signal input to the AND gate, during testing, the power driving module in the chip circuit can output a stable voltage signal, thereby enabling the detection of the operating frequency provided by the internal oscillator of the chip without affecting the use of the chip circuit.

[0032] In one embodiment, the sequential logic module includes an RS flip-flop and a clock generator. The reset input of the RS flip-flop is connected to the output of the clock generator. The set input of the RS flip-flop serves as the input of the sequential logic module and is connected to the output of the feedback input module. The output of the RS flip-flop serves as the output of the sequential logic module. The clock generator is configured to output a clock signal to the reset input of the RS flip-flop. It is understood that by providing corresponding clock signals and timing control signals to the two inputs of the RS flip-flop, the RS flip-flop can store and control signal changes, thereby providing corresponding input signals to the power drive module to control the corresponding drive signals, thereby controlling the voltage signal on the power switching output pin, thereby facilitating operating frequency testing.

[0033] It should be noted that the clock generator is a device for generating a clock signal. In some embodiments, the clock signal connected to the RS trigger may also be provided by an external clock circuit (such as an external crystal oscillator).

[0034] In one embodiment, the power driving module includes a logic chip, a first inverting driver, a second inverting driver, a first power switch tube, and a second power switch tube.

[0035] The logic chip has two input terminals and two output terminals, wherein the first input terminal of the logic chip serves as the first input terminal of the power driving module, the second input terminal of the logic chip serves as the second input terminal of the power driving module, the first output terminal of the logic chip is connected to the input terminal of the first inverting driver, and the second output terminal of the logic chip is connected to the input terminal of the second inverting driver.

[0036] The output of the first inverting driver is connected to the control terminal of the first power switch, the output of the second inverting driver is connected to the control terminal of the second power switch, and the input of the first power switch is connected to the power supply voltage. The output of the first power switch is connected to the input of the second power switch and serves as the power switching output pin of the chip circuit, and the output of the second power switch is grounded. Optionally, in one embodiment, the first power switch is a PMOS transistor and the second power switch is an NMOS transistor. Specifically, the gate of the PMOS transistor serves as the control terminal of the first power switch and is connected to the output of the first inverting driver; the source of the PMOS transistor serves as the input of the first power switch and is connected to the power supply voltage; and the drain of the PMOS transistor serves as the output of the first power switch. Alternatively, the gate of the NMOS transistor serves as the control terminal of the second power switch and is connected to the output of the second inverting driver; the drain of the NMOS transistor serves as the input of the second power switch and is connected to the output of the first power switch; and the source of the NMOS transistor serves as the output of the second power switch.

[0037] To this end, the logic chip controls the first inverting driver and the second inverting driver to output corresponding voltage signals, thereby controlling the conduction state of the first power switch tube and the second power switch tube, and then being able to stably generate a shutdown signal, so that the operating frequency of the chip can be measured at the power switching output pin.

[0038] It should be noted that in some embodiments, the first power switch and the second power switch can both be NMOS transistors. The gate terminal of one NMOS transistor is connected to the first inverting driver, the drain terminal of one NMOS transistor is connected to the power supply voltage, and the source terminal of the NMOS transistor is connected to the drain terminal of the other NMOS transistor, serving as the power switching output pin of the chip circuit. The gate terminal of the other NMOS transistor is connected to the second inverting driver, and the source terminal is grounded.

[0039] Figure 1 A circuit structure diagram of a chip circuit suitable for frequency detection is provided for an embodiment of the present application, such as Figure 1 As shown, the chip circuit includes a feedback input module 110 , a timing logic module 120 , a comparator module 130 and a power driving module 140 .

[0040] The feedback input module 110 includes a comparator unit 111 and a gate circuit unit 112. The comparator unit 111 includes an error amplifier A1 and a first comparator COM1, while the gate circuit unit 112 includes an AND gate A2 and a NOR gate A3. Specifically, the positive input of the error amplifier A1 is connected to the reference voltage, the negative input of the error amplifier A1 is used to connect to the feedback voltage, the non-inverting input of the first comparator COM1 is connected to the output of the error amplifier A1, the inverting input of the first comparator COM1 is used to connect to the sampling voltage, the output of the first comparator COM1 is connected to the first input of the AND gate A2, the second input of the AND gate A2 is connected to the power supply voltage via a pull-up resistor R1, the first input of the NOR gate A3 is connected to the output of the AND gate A3, the second input of the NOR gate A3 serves as the third input of the gate circuit unit 112, and the output of the NOR gate A3 is connected to the input of the sequential logic module 120.

[0041] The sequential logic module 120 includes an RS flip-flop U1 and a clock generator U2. Specifically, the reset input (R) of the RS flip-flop U1 is connected to the output of the clock generator U2. The clock generator U2 is configured to output a clock signal to the reset input of the RS flip-flop U1. The set input (S) of the RS flip-flop U1 is connected to the output of the NOR gate A3. The output of the RS flip-flop U1 serves as the output of the sequential logic module 120.

[0042] The comparator module 130 includes a second comparator COM2, a first input terminal of the second comparator COM2 serving as the first input terminal of the comparator module 130, the first input terminal of the second comparator COM2 being connected to the power switching output pin SW of the chip circuit, and a second input terminal of the second comparator COM2 being grounded.

[0043] The power driver module 140 includes a logic chip U3, a first inverter driver M1, a second inverter driver M2, a PMOS transistor Q1 serving as a first power switch, and an NMOS transistor Q2 serving as a second power switch. Specifically, the first input of the logic chip U3 is connected to the output of the RS trigger U1, and the second input of the logic chip U3 is connected to the output of the second comparator COM2. The input of the first inverter driver M1 is connected to the first output of the logic chip U3, and the output of the first inverter driver M1 is connected to the gate of the PMOS transistor Q1. The input of the second inverter driver M2 is connected to the second output of the logic chip U3, and the output of the second inverter driver M2 is connected to the gate of the NMOS transistor Q2. The source of the PMOS transistor Q1 is connected to the power supply voltage, and the drain of the PMOS transistor Q1 is connected to the drain of the NMOS transistor Q2, serving as the power switching output pin SW of the chip circuit. The source of the NMOS transistor Q2 is grounded.

[0044] Figure 2A circuit diagram for testing a chip circuit provided in an embodiment of the present application is shown in the figure. In the figure, U4 represents the chip circuit, which includes a power input pin VIN, an enable pin EN, a test input pin TEST, a power switch output pin SW, a start pin BOOT, a voltage feedback pin FB, and a ground pin GND. Among them, the power input pin VIN and the enable pin EN are both connected to the power supply voltage V in , the test input pin TEST is connected to the grounded control switch S1, and the voltage feedback pin FB is connected to the feedback voltage V FB The power switching output pin SW is used to output a signal, and the startup pin BOOT is connected to the power switching output pin SW through a capacitor.

[0045] It is understandable that in PFM mode, the switch tube is mostly in an inoperative state, the circuit is in an intermittent on and off state, and the frequency is not fixed; while in PWM mode, the switch tube is continuously working. To this end, the chip circuit of this solution can connect the control switch S1 to the ground through the test input pin TEST, and the voltage feedback pin FB is connected to a fixed feedback voltage V FB It can be imagined that the feedback voltage Vfb is greater than the short-circuit protection voltage so that the chip does not enter short-circuit protection, and it is also lower than the voltage threshold of the output overvoltage detection, thereby ensuring that the chip is in normal working mode. In addition, the test input pin TEST is only used when grounded at the test frequency, and finally it does not need to be packaged.

[0046] Since the power switching output pin SW disconnects the inductor, load capacitor, etc., the power switching output pin SW is left floating, and the inductor current cannot be detected inside the chip, resulting in the chip lacking an OFF signal to shut down the upper tube.

[0047] To address this, an AND gate is included in the chip circuit. One input of the AND gate is connected to the power supply voltage through a pull-up resistor. This input also serves as the test input pin TEST. When the chip is operating normally, the test input pin TEST is left floating, allowing the AND gate to connect to a high level without affecting the normal operation of the chip.

[0048] When testing is required, the control switch S1 is closed, and then the test input pin TEST is grounded, and the AND gate is connected to a low level, so that the chip can stably generate a shutdown signal after the upper tube (i.e., PMOS tube) is turned on. Therefore, the normal operating frequency of the internal oscillator can be measured at the power switching output pin SW.

[0049] As can be seen from the above scheme, the chip circuit of the present application can measure the chip's operating frequency in normal mode, and the circuit structure is simple and easy to implement. In addition, the chip circuit does not require the chip to be overloaded, effectively avoiding the risk of damage to the test equipment, reducing testing costs, and eliminating the need for excessive additional testing steps, which helps improve test efficiency.

[0050] The present application also provides a power management chip, which includes the above-mentioned chip circuit. The power management chip has the beneficial effects of the chip circuit. It can be tested without the need for the chip to be overloaded, effectively avoiding the risk of damage to the test equipment, reducing the cost of testing, and does not require too many additional testing steps, which helps to improve testing efficiency.

[0051] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0052] Note that the above are only preferred embodiments of the present application and the technical principles employed. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present application. The scope of the present application is determined by the scope of the appended claims.

Claims

1. A chip circuit suitable for frequency detection, characterized in that: include: A feedback input module, wherein a first input end of the feedback input module serves as a voltage feedback pin of the chip circuit to receive a feedback voltage, and a second input end of the feedback input module serves as a test input pin of the chip circuit to receive a grounded control switch; a sequential logic module, wherein an input end of the sequential logic module is connected to an output end of the feedback input module, and the sequential logic module is configured to output a time series control signal in combination with a set signal output by the feedback input module; a comparator module, wherein a first input terminal of the comparator module is connected to a power switching output pin of the chip circuit, and a second input terminal of the comparator module is grounded; A power driving module, wherein a first input end of the power driving module is connected to the output end of the timing logic module, a second input end of the power driving module is connected to the output end of the comparator module, a power supply end of the power driving module serves as a power input pin of the chip circuit, and an output end of the power driving module serves as a power switching output pin of the chip circuit. The power driving module is used to determine the voltage signal on the power switching output pin according to the outputs of the timing logic module and the comparator module.

2. The chip circuit suitable for frequency detection according to claim 1, characterized in that: The feedback input module includes a comparator unit and a gate circuit unit; The first input terminal of the comparator unit serves as the first input terminal of the feedback input module for receiving the feedback voltage, and the second input terminal of the comparator unit receives the sampling voltage; The first input end of the gate circuit unit is connected to the output end of the comparator unit, the second input end of the gate circuit unit is used to be grounded during testing, the third input end of the gate circuit unit is connected to the minimum conduction time signal, and the output end of the gate circuit unit is connected to the input end of the timing logic module.

3. The chip circuit suitable for frequency detection according to claim 2, characterized in that: The comparator unit includes an error amplifier and a first comparator; The positive input terminal of the error amplifier is connected to the reference voltage, and the negative input terminal of the error amplifier serves as the first input terminal of the comparator unit to be connected to the feedback voltage; The non-inverting input of the first comparator is connected to the output of the error amplifier, the inverting input of the first comparator serves as the second input of the comparator unit and is connected to the sampling voltage, and the output of the first comparator serves as the output of the comparator unit.

4. The chip circuit suitable for frequency detection according to claim 2 or 3, characterized in that: The gate circuit unit includes an AND gate and a NOR gate; The first input end of the AND gate is connected to the output end of the comparator unit, the second input end of the AND gate serves as the second input end of the gate circuit unit, and the second input end of the AND gate is also connected to the power supply voltage through a pull-up resistor; The first input end of the NOR gate is connected to the output end of the AND gate, the second input end of the NOR gate serves as the third input end of the gate circuit unit, and the output end of the NOR gate is connected to the input end of the sequential logic module.

5. The chip circuit suitable for frequency detection according to claim 1, characterized in that: The sequential logic module includes an RS trigger and a clock generator; The reset input terminal of the RS trigger is connected to the output terminal of the clock generator, the set input terminal of the RS trigger serves as the input terminal of the sequential logic module and is connected to the output terminal of the feedback input module, and the output terminal of the RS trigger serves as the output terminal of the sequential logic module; The clock generator is used to output a clock signal to the reset input terminal of the RS trigger.

6. The chip circuit suitable for frequency detection according to claim 1, characterized in that: The power driving module includes a logic chip, a first inverting driver, a second inverting driver, a first power switch tube and a second power switch tube; The first input terminal of the logic chip serves as the first input terminal of the power driving module, and the second input terminal of the logic chip serves as the second input terminal of the power driving module; The input end of the first inverting driver is connected to the first output end of the logic chip, and the output end of the first inverting driver is connected to the control end of the first power switch tube; The input end of the second inverting driver is connected to the second output end of the logic chip, and the output end of the second inverting driver is connected to the control end of the second power switch tube; The input end of the first power switch tube is connected to the power supply voltage, the output end of the first power switch tube is connected to the input end of the second power switch tube and serves as the power switching output pin of the chip circuit, and the output end of the second power switch tube is grounded.

7. The chip circuit suitable for frequency detection according to claim 6, characterized in that: The first power switch tube is a PMOS tube, the gate terminal of the PMOS tube serves as the control terminal of the first power switch tube and is connected to the output terminal of the first inverting driver; the source terminal of the PMOS tube serves as the input terminal of the first power switch tube and is connected to the power supply voltage; and the drain terminal of the PMOS tube serves as the output terminal of the first power switch tube.

8. The chip circuit suitable for frequency detection according to claim 6 or 7, characterized in that: The second power switch tube is an NMOS tube, the gate terminal of the NMOS tube serves as the control terminal of the second power switch tube and is connected to the output terminal of the second inverting driver; the drain terminal of the NMOS tube serves as the input terminal of the second power switch tube and is connected to the output terminal of the first power switch tube; and the source terminal of the NMOS tube serves as the output terminal of the second power switch tube.

9. The chip circuit suitable for frequency detection according to claim 6, characterized in that: The comparator module includes a second comparator, a first input end of the second comparator serves as the first input end of the comparator module, the first input end of the second comparator is connected to the output end of the first power switch tube, and a second input end of the second comparator is grounded.

10. A power management chip, characterized in that: The invention comprises a chip circuit suitable for frequency detection as described in any one of claims 1 to 9.

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