Band-gap reference power supply circuit and electronic equipment

Abstract

The utility model discloses a band-gap reference power supply circuit and electronic equipment, which are applied to the field of integrated circuit design. The circuit comprises a pre-bias circuit, a core circuit and a starting circuit. The pre-bias circuit comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a fifth MOS tube. The electronic devices of the pre-bias circuit and the third end of the core circuit jointly form a negative feedback loop, and the band-gap reference power supply circuit can clamp and control the voltages at the first end and the second end of the core circuit to be equal through the negative feedback loop, so that the stability of the pre-bias voltage generated by the pre-bias circuit is ensured; according to the band-gap reference power supply circuit, the power supply rejection ratio of the pre-bias voltage is increased, and further, the power supply rejection ratio of the output reference voltage is increased while the power supply rejection ratio of the pre-bias voltage is increased, so that the power supply rejection ratio of the output reference voltage can be increased without an external circuit, and the power consumption can be effectively reduced.

Description

Technical Field

[0001] The utility model relates to the field of integrated circuit design, in particular to a bandgap reference power supply circuit and electronic equipment. Background Art

[0002] The bandgap reference circuit is one of the basic analog unit circuits in integrated circuit design. It can provide a voltage that does not change with temperature or power supply voltage for other modules of the system. It is mostly composed of transistors, operational amplifiers, and resistors. However, during application, due to the poor isolation between the collector of the transistor of the bandgap reference circuit and the power supply, the power supply rejection ratio of the reference voltage generated by the bandgap reference circuit is not ideal. As a result, a slight instability of the power supply voltage often affects the reference voltage signal and even causes the back-end circuit to malfunction. In related technologies, a bandgap reference circuit is usually connected to a pre-stabilizer circuit to provide a stable power supply voltage for the bandgap reference circuit. However, this requires the separate pre-stabilizer circuit to consume additional current, increasing the power consumption of the circuit.

[0003] In view of the above technologies, it is an urgent problem to be solved by those skilled in the art to seek a bandgap reference power supply circuit with improved power supply rejection ratio and low power consumption. Utility Model Content

[0004] The purpose of the utility model is to provide a bandgap reference power supply circuit and electronic equipment, which can solve the problem of increasing circuit power consumption in order to improve the power supply rejection ratio in the related art.

[0005] To solve the above technical problems, the present invention provides a bandgap reference power supply circuit, comprising: a pre-bias circuit, a core circuit and a startup circuit; wherein the pre-bias circuit comprises: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor and a fifth MOS transistor;

[0006] The gate of the first MOS transistor is connected to the first end of the core circuit as the first end of the pre-bias circuit; the source of the first MOS transistor is connected to the source of the second MOS transistor, and together serve as the second end of the pre-bias circuit and are connected to the bias current source; the drain of the first MOS transistor is connected to the gate of the third MOS transistor, and the drain of the third MOS transistor is connected to the gate of the fourth MOS transistor;

[0007] The gate of the second MOS transistor is connected to the second end of the core circuit as the third end of the pre-bias circuit; the drain of the second MOS transistor is connected to the drain of the fourth MOS transistor and the gate of the fifth MOS transistor;

[0008] The source of the third MOS transistor is connected to the source of the fourth MOS transistor and the source of the fifth MOS transistor, and together serve as a fourth end of the pre-bias circuit and are connected to the third end of the core circuit, the first end of the startup circuit, the second end of the startup circuit, and the preset voltage source;

[0009] The drain of the fifth MOS tube is grounded.

[0010] Preferably, the pre-bias circuit further includes: a sixth MOS transistor and a seventh MOS transistor;

[0011] The source of the sixth MOS transistor is connected to a preset voltage source and a first end of the startup circuit; the gate of the sixth MOS transistor is connected to a second end of the startup circuit; the drain of the sixth MOS transistor is connected to the source of the third MOS transistor, the source of the fourth MOS transistor, the source of the fifth MOS transistor, and the third end of the core circuit;

[0012] The drain of the seventh MOS tube is connected to the drain of the fifth MOS tube and the gate of the seventh MOS tube, and together serve as the fifth end of the pre-bias circuit and are connected to the third end of the startup circuit; the source of the seventh MOS tube is grounded.

[0013] Preferably, it further comprises: a low-pass filter circuit; wherein the low-pass filter circuit comprises: a first resistor and a first capacitor;

[0014] Wherein, the first end of the first resistor is connected to the fourth end of the core circuit; the second end of the first resistor is connected to the first end of the first capacitor and the reference voltage output end;

[0015] The second terminal of the first capacitor is grounded.

[0016] Preferably, the core circuit includes: an eighth MOS transistor, a ninth MOS transistor, a first triode, a second triode, a third triode, a fourth triode, a second resistor, and a third resistor;

[0017] The base of the first transistor is connected to the collector of the first transistor and the first end of the second resistor, and together they serve as the first end of the core circuit and are connected to the gate of the first MOS transistor; the emitter of the first transistor is connected to the collector of the second transistor and the base of the second transistor; the emitter of the second transistor is grounded;

[0018] The base of the third transistor is connected to the collector of the third transistor and the first end of the third resistor; the emitter of the third transistor is connected to the base of the fourth transistor and the collector of the fourth transistor; the emitter of the fourth transistor is grounded;

[0019] The second end of the third resistor serves as the second end of the core circuit and is connected to the gate of the second MOS transistor;

[0020] The second end of the second resistor is connected to the second end of the third resistor, the gate of the eighth MOS transistor, the drain of the eighth MOS transistor, and the gate of the ninth MOS transistor;

[0021] The source of the eighth MOS transistor is connected to the preset voltage source and the source of the ninth MOS transistor, and together serves as the third end of the core circuit and is connected to the first end of the startup circuit, the second end of the startup circuit, the source of the third MOS transistor, the source of the fourth MOS transistor, and the source of the fifth MOS transistor;

[0022] The drain of the ninth MOS tube is grounded.

[0023] Preferably, the core circuit further comprises: a fourth resistor;

[0024] The first end of the fourth resistor is connected to the second end of the third resistor; the second end of the fourth resistor is connected to the second end of the second resistor, the gate of the eighth MOS transistor, the drain of the eighth MOS transistor and the gate of the ninth MOS transistor.

[0025] Preferably, the core circuit further includes: a tenth MOS transistor;

[0026] The drain of the tenth MOS tube is connected to the drain of the ninth MOS tube; the source of the tenth MOS tube is grounded; and the gate of the tenth MOS tube is connected to the fifth end of the pre-bias circuit and the third end of the startup circuit.

[0027] Preferably, the startup circuit includes: a fifth transistor, a fifth resistor, a sixth transistor, a seventh transistor, an eleventh MOS transistor and a twelfth MOS transistor;

[0028] The base of the fifth transistor is connected to the collector of the fifth transistor and the first end of the fifth resistor; the emitter of the fifth transistor is connected to the collector of the sixth transistor and the drain of the eleventh MOS transistor;

[0029] The second end of the fifth resistor is connected to the source of the eleventh MOS transistor and the source of the twelfth MOS transistor, and together serves as the first end of the startup circuit and is connected to the fourth end of the pre-bias circuit, the third end of the core circuit, and the preset voltage source;

[0030] The gate of the eleventh MOS transistor is connected to the gate of the twelfth MOS transistor, the drain of the twelfth MOS transistor, the collector of the seventh transistor, the base of the seventh transistor, and the base of the sixth transistor, and together serve as the second end of the startup circuit and are connected to the fourth end of the pre-bias circuit, the third end of the core circuit, and the preset voltage source;

[0031] The emitter of the seventh transistor is connected to the emitter of the sixth transistor and is grounded.

[0032] Preferably, the startup circuit further includes: a thirteenth MOS transistor, a fourteenth MOS transistor and a sixth resistor;

[0033] The gate of the thirteenth MOS transistor is connected to the emitter of the fifth transistor, the collector of the sixth transistor, and the drain of the eleventh MOS transistor; the drain of the thirteenth MOS transistor is connected to the gate of the twelfth MOS transistor, the drain of the twelfth MOS transistor, and the gate of the eleventh MOS transistor; the source of the thirteenth MOS transistor is connected to the base of the seventh transistor, the collector of the seventh transistor, and the base of the sixth transistor;

[0034] A first end of the sixth resistor is connected to the emitter of the seventh transistor; a second end of the sixth resistor is connected to the emitter of the sixth transistor and is grounded;

[0035] The drain of the fourteenth MOS transistor is connected to the first end of the fifth resistor, the collector of the fifth transistor, and the base of the fifth transistor; the source of the fourteenth MOS transistor is grounded; and the gate of the fourteenth MOS transistor serves as the third end of the startup circuit and is connected to the fifth end of the pre-bias circuit.

[0036] Preferably, it further includes: a fifteenth MOS transistor and a sixteenth MOS transistor;

[0037] The gate of the fifteenth MOS transistor is connected to the drain of the fifteenth MOS transistor, the gate of the sixteenth MOS transistor and the bias current source; the source of the fifteenth MOS transistor is grounded;

[0038] The drain of the sixteenth MOS tube is connected to the source of the first MOS tube and the source of the second MOS tube; the source of the sixteenth MOS tube is grounded.

[0039] On the other hand, the present application also provides an electronic device, comprising the above-mentioned bandgap reference power supply circuit.

[0040] The utility model provides a bandgap reference power supply circuit, comprising: a pre-bias circuit, a core circuit, and a startup circuit; wherein the pre-bias circuit comprises: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a fifth MOS transistor; wherein the gate of the first MOS transistor is connected to the first end of the core circuit as a first end of the pre-bias circuit; the source of the first MOS transistor is connected to the source of the second MOS transistor, and together they serve as the second end of the pre-bias circuit and are connected to a bias current source; the drain of the first MOS transistor is connected to the gate of the third MOS transistor, the drain of the third MOS transistor, and the gate of the fourth MOS transistor; the gate of the second MOS transistor is connected to the second end of the core circuit as a third end of the pre-bias circuit; the drain of the second MOS transistor is connected to the drain of the fourth MOS transistor and the gate of the fifth MOS transistor; the source of the third MOS transistor is connected to the source of the fourth MOS transistor and the source of the fifth MOS transistor, and together they serve as the fourth end of the pre-bias circuit and are connected to the third end of the core circuit, the first end of the startup circuit, the second end of the startup circuit, and a preset voltage source; and the drain of the fifth MOS transistor is grounded. It can be seen that in the bandgap reference power supply circuit of the present application, the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor of the pre-bias circuit and the third end of the core circuit together constitute a negative feedback loop. The bandgap reference power supply circuit can clamp and control the voltages at the first and second ends of the core circuit to be equal through the negative feedback loop, and set the pre-bias voltage in the negative feedback loop, thereby ensuring the stability of the pre-bias voltage generated by the pre-bias circuit, that is, improving the power supply rejection ratio of the pre-bias voltage. Furthermore, a linear relationship between the pre-bias voltage and the output reference voltage is established in the bandgap reference power supply circuit, so that while the power supply rejection ratio of the pre-bias voltage is improved, the power supply rejection ratio of the output reference voltage is also synchronously improved. Therefore, the bandgap reference power supply circuit no longer requires an external circuit to improve the power supply rejection ratio of the output reference voltage, and can effectively reduce power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 A structural diagram of a bandgap reference power supply circuit provided in an embodiment of the present application;

[0043] Figure 2 A complete circuit diagram of a bandgap reference power supply circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0045] The core of the utility model is to provide a bandgap reference power supply circuit and electronic equipment.

[0046] In order to enable those skilled in the art to better understand the present invention, the present invention will be described in further detail below with reference to the accompanying drawings and specific implementation methods.

[0047] Figure 1 A structural diagram of a bandgap reference power supply circuit provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, it includes: a pre-bias circuit 1, a core circuit 2 and a startup circuit 3. In addition, it also includes: a bias current source I and a preset voltage source VS. The pre-bias circuit 1 includes: a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4 and a fifth MOS transistor M5. The connection relationship of the circuit is as follows: the gate of the first MOS transistor M1 is connected to the first end of the core circuit 2 as the first end of the pre-bias circuit 1; the source of the first MOS transistor M1 is connected to the source of the second MOS transistor M2, and together they serve as the second end of the pre-bias circuit 1 and are connected to the bias current source I; the drain of the first MOS transistor M1 is connected to the gate of the third MOS transistor M3, the drain of the third MOS transistor M3, and the gate of the fourth MOS transistor M4; the gate of the second MOS transistor M2 is connected to the second end of the core circuit 2 as the third end of the pre-bias circuit 1; the drain of the second MOS transistor M2 is connected to the drain of the fourth MOS transistor M4 and the gate of the fifth MOS transistor M5; the source of the third MOS transistor M3 is connected to the source of the fourth MOS transistor M4 and the source of the fifth MOS transistor M5, and together they serve as the fourth end of the pre-bias circuit 1 and are connected to the third end of the core circuit 2, the first end of the startup circuit 3, the second end of the startup circuit 3, and the preset voltage source VS; the drain of the fifth MOS transistor M5 is grounded.

[0048] The circuit's principle is as follows: pre-bias circuit 1 primarily consists of a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, and a fifth MOS transistor M5. These transistors, together with the third terminal of core circuit 2, form a negative feedback loop. This negative feedback loop clamps the voltages at the first and second terminals of core circuit 2, ensuring that the voltages at both terminals are equal. Simultaneously, in the circuit, the current flowing through startup circuit 3 should be greater than the current flowing through core circuit 2. In this case, the excess current branches to ground through the fifth MOS transistor M5. Pre-bias circuit 1, based on its clamped op amp operation, generates a pre-bias voltage VP. The pre-bias voltage VP node is located within the negative feedback loop, specifically at the junction of the source of the third MOS transistor M3, the source of the fourth MOS transistor M4, and the core circuit 2. When the pre-bias voltage VP increases, the gate voltage of the first MOS transistor M1 and the gate voltage of the second MOS transistor M2 increase, but the gate voltage of the fifth MOS transistor M5 decreases, thereby lowering the source voltage of the fifth MOS transistor M5. Therefore, the pre-bias voltage VP can establish a linear relationship with the output reference voltage VBG in the bandgap reference power supply circuit, thereby improving the power supply rejection ratio (PSRR) of the pre-bias voltage VP. The power supply rejection ratio of the output reference voltage VBG can also be effectively guaranteed within the bandwidth of the MOS transistors in the pre-bias circuit 1.

[0049] It should be noted that the core circuit 2 and the startup circuit 3 are conventional circuits and will not be described in detail in this application.

[0050] The utility model provides a bandgap reference power supply circuit, comprising: a pre-bias circuit 1, a core circuit 2 and a startup circuit 3; wherein the pre-bias circuit 1 comprises: a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4 and a fifth MOS transistor M5; wherein the gate of the first MOS transistor M1 is connected to the first end of the core circuit 2 as the first end of the pre-bias circuit 1; the source of the first MOS transistor M1 is connected to the source of the second MOS transistor M2, and both serve as the second end of the pre-bias circuit 1 and are connected to the bias current source I; the drain of the first MOS transistor M1 is connected to the drain of the third MOS transistor M3. The gate of the third MOS transistor M3 is connected to the drain of the third MOS transistor M3 and the gate of the fourth MOS transistor M4; the gate of the second MOS transistor M2 is connected to the second end of the core circuit 2 as the third end of the pre-bias circuit 1; the drain of the second MOS transistor M2 is connected to the drain of the fourth MOS transistor M4 and the gate of the fifth MOS transistor M5; the source of the third MOS transistor M3 is connected to the source of the fourth MOS transistor M4 and the source of the fifth MOS transistor M5, and together serve as the fourth end of the pre-bias circuit 1 and are connected to the third end of the core circuit 2, the first end of the startup circuit 3, the second end of the startup circuit 3 and the preset voltage source VS; the drain of the fifth MOS transistor M5 is grounded. It can be seen that in the bandgap reference power supply circuit of the present application, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, and the fifth MOS transistor M5 of the pre-bias circuit and the third terminal of the core circuit 2 together constitute a negative feedback loop. The bandgap reference power supply circuit can clamp and control the voltages at the first and second terminals of the core circuit 2 to be equal through the negative feedback loop, and set the pre-bias voltage VP in the negative feedback loop, thereby ensuring the stability of the pre-bias voltage VP generated by the pre-bias circuit, that is, improving the power supply rejection ratio of the pre-bias voltage VP. Furthermore, the circuit establishes a linear relationship between the pre-bias voltage VP and the output reference voltage VBG, so that while the power supply rejection ratio of the pre-bias voltage is improved, the power supply rejection ratio of the output reference voltage VBG is also synchronously improved. Therefore, the bandgap reference power supply circuit can improve the power supply rejection ratio of the output reference voltage VBG without the need for an external circuit, and can effectively reduce power consumption.

[0051] In a specific embodiment, Figure 2As shown, the pre-bias circuit 1 further includes a sixth MOS transistor M6 and a seventh MOS transistor M7. The specific circuit connection relationship is as follows: the source of the sixth MOS transistor M6 is connected to the preset voltage source VS and the first end of the startup circuit 3; the gate of the sixth MOS transistor M6 is connected to the second end of the startup circuit 3; the drain of the sixth MOS transistor M6 is connected to the source of the third MOS transistor M3, the source of the fourth MOS transistor M4, the source of the fifth MOS transistor M5, and the third end of the core circuit 2; the drain of the seventh MOS transistor M7 is connected to the drain of the fifth MOS transistor M5 and the gate of the seventh MOS transistor M7, and together serve as the fifth end of the pre-bias circuit 1 and are connected to the third end of the startup circuit 3; the source of the seventh MOS transistor M7 is grounded.

[0052] besides, Figure 2 The low-pass filter circuit also includes a first resistor R1 and a first capacitor C1. The circuit is connected as follows: a first end of the first resistor R1 is connected to the fourth end of the core circuit 2; a second end of the first resistor R1 is connected to the first end of the first capacitor C1 and the reference voltage output end; and a second end of the first capacitor C1 is grounded.

[0053] In a specific embodiment, the circuit principle is as follows: pre-bias circuit 1 comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, and a seventh MOS transistor M7. The first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, and the circuit connections form a negative feedback loop. This negative feedback loop clamps the voltage at the first terminal A and the second terminal B of the core circuit 2, so that the voltages at points A and B are equal. Simultaneously, in the circuit, the current flowing through the startup circuit 3 should be greater than the current flowing through the core circuit 2. In this case, the excess current branches to ground through the fifth MOS transistor M5. The pre-bias circuit 1 generates a pre-bias voltage VP based on its clamping operational amplifier operation. The pre-bias voltage VP node is located within the negative feedback loop, specifically at the connection between the source of the third MOS transistor M3, the source of the fourth MOS transistor M4, and the core circuit 2. When the pre-bias voltage VP increases, the gate voltages of the first and second MOS transistors M1 and M2 increase, but the gate voltage of the fifth MOS transistor M5 decreases, thereby lowering the source voltage of the fifth MOS transistor M5. The pre-bias voltage VP can establish a linear relationship with the output reference voltage VBG. As can be seen from the connection relationship, VP and VBG establish a linear relationship: that is, after the circuit is stabilized, VP = VBG + VGS2 (the core startup voltage in core circuit 2). Based on this linear relationship, the power supply rejection ratio of the output reference voltage VBG is equivalent to that of the pre-bias voltage VP. Therefore, increasing the power supply rejection ratio of the pre-bias voltage VP can effectively improve the power supply rejection ratio of the output reference voltage VBG. The power supply rejection ratio can also be effectively maintained within the bandwidth of the MOS transistors in the pre-bias circuit 1.

[0054] As a preferred embodiment, the sixth MOS transistor M6 is a high-voltage MOS transistor, which can further meet the requirement of stable output of reference voltage under high-voltage environment. However, this application is not limited and can be set according to user needs.

[0055] The structure described above can effectively improve the power supply ripple rejection capability of the bandgap reference power supply circuit. The principle is: the power supply rejection ratio is regarded as the voltage divided by the input voltage, and the power supply rejection ratio is determined by the impedance of the output node to ground and the impedance of the output node to the power supply. The corresponding formula is:

[0056] ;

[0057] And Z OUT It represents the output impedance of the output node to ground, and its expression is:

[0058] ;

[0059] where R dsp Represents the channel resistance of the sixth MOS tube M6, A OL The open-loop gain of the overall bandgap reference power supply circuit, Z CL represents the equivalent impedance of the first capacitor C1 in the low-pass filter circuit, β represents the feedback coefficient, V IN Indicates the input voltage, V OUT Indicates the output voltage, g m Indicates gain. OL and Z OUT is the frequency dependent function.

[0060] According to the above formula, the power supply rejection ratio in the low and medium frequency bands is inversely proportional to the loop gain. The loop gain can be increased and the equivalent impedance of the pre-regulator circuit can be increased, that is, the channel resistance R of the sixth MOS tube M6 can be increased. dsp Optimize the power supply rejection ratio in the low and medium frequency bands. The equivalent impedance R of the low-pass filter circuit and the pre-bias circuit 1 at high frequencies dsp Determines the power supply rejection ratio of the circuit at high frequencies. The zero point introduced by the low-pass filter circuit can effectively achieve excellent power supply rejection ratio in the entire frequency band.

[0061] It should be noted that the structure provided in this application is only one possible implementation method, but is not limited to this implementation method and can be set according to user needs.

[0062] The present application provides a complete pre-bias circuit and low-pass filter circuit, under which the power supply rejection ratio of the bandgap reference power supply circuit is improved.

[0063] On the basis of the above embodiments, as a preferred embodiment, Figure 2As shown, the core circuit 2 includes: an eighth MOS transistor M8, a ninth MOS transistor M9, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a second resistor R2, and a third resistor R3; the connection relationship of the circuit is as follows: the base of the first transistor Q1 is connected to the collector of the first transistor Q1 and the first end of the second resistor R2, and both serve as the first end of the core circuit 2 and are connected to the gate of the first MOS transistor M1; the emitter of the first transistor Q1 is connected to the collector of the second transistor Q2 and the base of the second transistor Q2; the emitter of the second transistor Q2 is grounded; the base of the third transistor Q3 is connected to the collector of the third transistor Q3 and the first end of the third resistor R3; the emitter of the third transistor Q3 is connected to the fourth transistor The base of the transistor Q4 is connected to the collector of the fourth transistor Q4; the emitter of the fourth transistor Q4 is grounded; the second end of the third resistor R3 is connected to the gate of the second MOS transistor M2 as the second end of the core circuit 2; the second end of the second resistor R2 is connected to the second end of the third resistor R3, the gate of the eighth MOS transistor M8, the drain of the eighth MOS transistor M8, and the gate of the ninth MOS transistor M9; the source of the eighth MOS transistor M8 is connected to the preset voltage source VS and the source of the ninth MOS transistor M9, and together serve as the third end of the core circuit 2 and are connected to the first end of the startup circuit 3, the second end of the startup circuit 3, the source of the third MOS transistor M3, the source of the fourth MOS transistor M4, and the source of the fifth MOS transistor M5; the drain of the ninth MOS transistor M9 is grounded.

[0064] besides, Figure 2 The core circuit 2 shown in FIG. 1 further includes: a fourth resistor R4 and a tenth MOS transistor M10; the circuit connections are as follows: a first end of the fourth resistor R4 is connected to the second end of the third resistor R3; a second end of the fourth resistor R4 is connected to the second end of the second resistor R2, the gate of the eighth MOS transistor M8, the drain of the eighth MOS transistor M8, and the gate of the ninth MOS transistor M9. The drain of the tenth MOS transistor M10 is connected to the drain of the ninth MOS transistor M9; the source of the tenth MOS transistor M10 is grounded; and the gate of the tenth MOS transistor M10 is connected to the fifth end of the pre-bias circuit 1 and the third end of the startup circuit 3.

[0065] In a specific embodiment, the complete core circuit 2 includes: an eighth MOS transistor M8, a ninth MOS transistor M9, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a second resistor R2, a third resistor R3, a fourth resistor R4 and a tenth MOS transistor M10. The principle of the circuit is as follows: a current proportional to the temperature is generated by the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4 and the third resistor R3, and then converted into a voltage proportional to the temperature by the second resistor R2. The voltage is weighted and superimposed with the transistor voltage drop VBE to obtain the output reference voltage VBG. The virtual short characteristic of the error amplifier ensures that the collector currents of the first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 are approximately equal. The first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4 with different areas are used to ensure that the bipolar transistors operate at different current densities, thereby obtaining a voltage drop difference with a positive temperature coefficient. Among them, the output reference voltage formula of the bandgap reference power supply circuit provided by the present application is:

[0066] ;

[0067] Among them, VB G is the output reference voltage, V BE1 is the voltage drop of any transistor among the first transistor Q1, the second transistor Q2, the third transistor Q3 and the fourth transistor Q4, V T is the temperature voltage, n is the coefficient, R2 is the resistance value of the second resistor R2, and R3 is the resistance value of the third resistor R3.

[0068] It should be noted that the VGS2 mentioned above is the core startup voltage in the core circuit 2, that is, the gate-source voltage of the eighth MOS transistor M8.

[0069] It should be noted that this application is only one possible implementation method, but is not limited to this implementation method and can be set up according to user needs.

[0070] On the basis of the above embodiments, as a preferred embodiment, Figure 2As shown, the startup circuit includes: a fifth transistor Q5, a fifth resistor R5, a sixth transistor Q6, a seventh transistor Q7, an eleventh MOS transistor M11, and a twelfth MOS transistor M12; the connection relationship of the circuit is as follows: the base of the fifth transistor Q5 is connected to the collector of the fifth transistor Q5 and the first end of the fifth resistor R5; the emitter of the fifth transistor Q5 is connected to the collector of the sixth transistor Q6 and the drain of the eleventh MOS transistor M11; the second end of the fifth resistor R5 is connected to the source of the eleventh MOS transistor M11 and the source of the twelfth MOS transistor M12, and together serve as A first end of the startup circuit 3 is connected to the fourth end of the pre-bias circuit 1, the third end of the core circuit 2, and the preset voltage source VS; a gate of the eleventh MOS transistor M11 is connected to the gate of the twelfth MOS transistor M12, the drain of the twelfth MOS transistor M12, the collector of the seventh transistor Q7, the base of the seventh transistor Q7, and the base of the sixth transistor Q6, and collectively serve as the second end of the startup circuit 3, which is connected to the fourth end of the pre-bias circuit 1, the third end of the core circuit 2, and the preset voltage source VS; an emitter of the seventh transistor Q7 is connected to the emitter of the sixth transistor Q6, and is grounded.

[0071] besides, Figure 2 The startup circuit shown also includes: a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, and a sixth resistor R6; the connection relationship of the circuit is: the gate of the thirteenth MOS transistor M13 is connected to the emitter of the fifth transistor Q5, the collector of the sixth transistor Q6, and the drain of the eleventh MOS transistor M11; the drain of the thirteenth MOS transistor M13 is connected to the gate of the twelfth MOS transistor M12, the drain of the twelfth MOS transistor M12, and the gate of the eleventh MOS transistor M11; the source of the thirteenth MOS transistor M13 is connected to the emitter of the fifth transistor Q5, the collector of the sixth transistor Q6, and the drain of the eleventh MOS transistor M11; The base, the collector of the seventh transistor Q7, and the base of the sixth transistor Q6 are connected; the first end of the sixth resistor R6 is connected to the emitter of the seventh transistor Q7; the second end of the sixth resistor R6 is connected to the emitter of the sixth transistor Q6 and is grounded; the drain of the fourteenth MOS transistor M14 is connected to the first end of the fifth resistor R5, the collector of the fifth transistor Q5, and the base of the fifth transistor Q5; the source of the fourteenth MOS transistor M14 is grounded; and the gate of the fourteenth MOS transistor M14, serving as the third end of the startup circuit 3, is connected to the fifth end of the pre-bias circuit 1.

[0072] In a specific embodiment, a complete startup circuit includes: a fifth transistor Q5, a fifth resistor R5, a sixth transistor Q6, a seventh transistor Q7, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, and a sixth resistor R6. The circuit operates as follows: when the circuit is at a zero-state degenerate point, the emitter voltage of the fifth transistor Q5 is approximately zero. At this point, the current flowing through the fifth resistor R5 is expressed as: I5 = (VS - VBE5) / R5; where I5 ​​is the current flowing through the fifth resistor R5, VS is the voltage corresponding to the preset voltage source, VBE5 is the voltage drop across the fifth transistor Q5, and R5 is the resistance value of the fifth resistor R5. At this point, current I5 flows through the sixth transistor Q6, generating a base voltage. The current equation for determining the current flowing through the seventh transistor Q3 is: I7 = ΔVBE / R6. Here, I7 is the current flowing through the seventh transistor Q7, ΔVBE is the difference between the voltage drop across the sixth transistor Q6 and the voltage drop across the seventh transistor Q7, and R6 is the resistance of the sixth resistor R6. This current is then mirrored to the sixth MOS transistor M6 through the twelfth and eleventh MOS transistors M12 and M11, generating a startup current I6. When the reference voltage in startup circuit 3 is established properly, the fourteenth MOS transistor M14 turns on, and the current generated by the fifth resistor R5 flows through the fourteenth MOS transistor M14 to ground, turning off the fifth transistor Q5 and shutting down startup circuit 3.

[0073] In order to ensure stable output of the reference voltage under a high-voltage environment, the sixth MOS transistor M6 , the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are high-voltage MOS transistors.

[0074] It should be noted that the embodiment provided in this application is only one possible implementation method, but is not limited to this implementation method and can be set according to user needs.

[0075] An embodiment of the present application provides a complete startup circuit. Under this structure, the startup circuit can realize the opening and closing of the entire bandgap reference power supply circuit, and the startup circuit ensures that the bandgap reference power supply circuit can get rid of the degeneracy point and normally establish the reference voltage when the power is turned on.

[0076] Among them, Figure 2The illustrated bandgap reference power supply circuit further includes a fifteenth MOS transistor M15 and a sixteenth MOS transistor M16. The circuit connection relationship is as follows: the gate of the fifteenth MOS transistor M15 is connected to the drain of the fifteenth MOS transistor M15, the gate of the sixteenth MOS transistor M16 is connected to the bias current source I; the source of the fifteenth MOS transistor M15 is grounded; the drain of the sixteenth MOS transistor M16 is connected to the source of the first MOS transistor M1 and the source of the second MOS transistor M2; and the source of the sixteenth MOS transistor M16 is grounded to ensure that a stable bias current source I is sent to the pre-bias circuit 4.

[0077] The utility model provides a bandgap reference power supply circuit, comprising: a pre-bias circuit 1, a core circuit 2 and a startup circuit 3; wherein the pre-bias circuit 1 comprises: a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4 and a fifth MOS transistor M5; wherein the gate of the first MOS transistor M1 is connected to the first end of the core circuit 2 as the first end of the pre-bias circuit 1; the source of the first MOS transistor M1 is connected to the source of the second MOS transistor M2, and both serve as the second end of the pre-bias circuit 1 and are connected to the bias current source I; the drain of the first MOS transistor M1 is connected to the drain of the third MOS transistor M3. The gate, the drain of the third MOS transistor M3 and the gate of the fourth MOS transistor M4 are connected; the gate of the second MOS transistor M2 is connected to the second end of the core circuit 2 as the third end of the pre-bias circuit 1; the drain of the second MOS transistor M2 is connected to the drain of the fourth MOS transistor M4 and the gate of the fifth MOS transistor M5; the source of the third MOS transistor M3 is connected to the source of the fourth MOS transistor M4 and the source of the fifth MOS transistor M5, and together serve as the fourth end of the pre-bias circuit 1 and are connected to the third end of the core circuit 2, the first end of the startup circuit 3, the second end of the startup circuit 3 and the preset voltage source VS; the drain of the fifth MOS transistor M5 is grounded. It can be seen that in the bandgap reference power supply circuit of the present application, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, and the fifth MOS transistor M5 of the pre-bias circuit 1 and the eighth MOS transistor M8 of the core circuit 2 form a negative feedback loop. The bandgap reference power supply circuit can clamp and control the voltages at the first and second ends of the core circuit to be equal through the negative feedback loop, and set the pre-bias voltage VP in the negative feedback loop, thereby ensuring the stability of the pre-bias voltage VP generated by the pre-bias circuit 1, that is, improving the power supply rejection ratio of the pre-bias voltage VP. Furthermore, the bandgap reference power supply circuit establishes a linear relationship between the pre-bias voltage VP and the output reference voltage VBG, so that while the power supply rejection ratio of the pre-bias voltage VP is improved, the power supply rejection ratio of the output reference voltage VBG is also synchronously improved. Therefore, the bandgap reference power supply circuit can improve the power supply rejection ratio of the output reference voltage VBG without the need for an external circuit, and can effectively reduce power consumption.

[0078] On the other hand, the present application also provides an electronic device, comprising the above-mentioned bandgap reference power supply circuit, and having the same beneficial effects.

[0079] The embodiment of the electronic device is the same as the embodiment of the bandgap reference power supply circuit described above, and therefore is not described in detail herein.

[0080] The above is a detailed introduction to a bandgap reference power supply circuit and electronic equipment provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

[0081] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

Claims

1. A bandgap reference power supply circuit, characterized in that: include: A pre-bias circuit, a core circuit and a startup circuit; wherein the pre-bias circuit includes: a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor and a fifth MOS transistor; The gate of the first MOS transistor is connected to the first end of the core circuit as the first end of the pre-bias circuit; the source of the first MOS transistor is connected to the source of the second MOS transistor, and both serve as the second end of the pre-bias circuit and are connected to the bias current source; the drain of the first MOS transistor is connected to the gate of the third MOS transistor, and the drain of the third MOS transistor is connected to the gate of the fourth MOS transistor; The gate of the second MOS transistor is connected to the second end of the core circuit as the third end of the pre-bias circuit; the drain of the second MOS transistor is connected to the drain of the fourth MOS transistor and the gate of the fifth MOS transistor; The source of the third MOS transistor is connected to the source of the fourth MOS transistor and the source of the fifth MOS transistor, and together serve as the fourth end of the pre-bias circuit and are connected to the third end of the core circuit, the first end of the startup circuit, the second end of the startup circuit, and a preset voltage source; The drain of the fifth MOS transistor is grounded.

2. The bandgap reference power supply circuit according to claim 1, wherein: The pre-bias circuit further includes: a sixth MOS transistor and a seventh MOS transistor; The source of the sixth MOS transistor is connected to the preset voltage source and the first end of the startup circuit; the gate of the sixth MOS transistor is connected to the second end of the startup circuit; the drain of the sixth MOS transistor is connected to the source of the third MOS transistor, the source of the fourth MOS transistor, the source of the fifth MOS transistor, and the third end of the core circuit; The drain of the seventh MOS transistor is connected to the drain of the fifth MOS transistor and the gate of the seventh MOS transistor, and together serve as the fifth end of the pre-bias circuit and are connected to the third end of the startup circuit; the source of the seventh MOS transistor is grounded.

3. The bandgap reference power supply circuit according to claim 1, wherein: Also includes: A low-pass filter circuit; wherein the low-pass filter circuit comprises: a first resistor and a first capacitor; Wherein, the first end of the first resistor is connected to the fourth end of the core circuit; the second end of the first resistor is connected to the first end of the first capacitor and the reference voltage output end; The second terminal of the first capacitor is grounded.

4. The bandgap reference power supply circuit according to claim 1, wherein: The core circuit includes: an eighth MOS transistor, a ninth MOS transistor, a first triode, a second triode, a third triode, a fourth triode, a second resistor and a third resistor; The base of the first transistor is connected to the collector of the first transistor and the first end of the second resistor, and together serve as the first end of the core circuit and are connected to the gate of the first MOS transistor; the emitter of the first transistor is connected to the collector of the second transistor and the base of the second transistor; and the emitter of the second transistor is grounded. The base of the third transistor is connected to the collector of the third transistor and the first end of the third resistor; the emitter of the third transistor is connected to the base of the fourth transistor and the collector of the fourth transistor; the emitter of the fourth transistor is grounded; The second end of the third resistor serves as the second end of the core circuit and is connected to the gate of the second MOS transistor; The second end of the second resistor is connected to the second end of the third resistor, the gate of the eighth MOS transistor, the drain of the eighth MOS transistor, and the gate of the ninth MOS transistor; The source of the eighth MOS transistor is connected to the preset voltage source and the source of the ninth MOS transistor, and together serves as the third end of the core circuit and is connected to the first end of the startup circuit, the second end of the startup circuit, the source of the third MOS transistor, the source of the fourth MOS transistor, and the source of the fifth MOS transistor; The drain of the ninth MOS tube is grounded.

5. The bandgap reference power supply circuit according to claim 4, wherein: The core circuit further includes: a fourth resistor; The first end of the fourth resistor is connected to the second end of the third resistor; the second end of the fourth resistor is connected to the second end of the second resistor, the gate of the eighth MOS transistor, the drain of the eighth MOS transistor and the gate of the ninth MOS transistor.

6. The bandgap reference power supply circuit according to claim 5, wherein: The core circuit further includes: a tenth MOS transistor; The drain of the tenth MOS transistor is connected to the drain of the ninth MOS transistor; the source of the tenth MOS transistor is grounded; and the gate of the tenth MOS transistor is connected to the fifth end of the pre-bias circuit and the third end of the startup circuit.

7. The bandgap reference power supply circuit according to claim 1, wherein: The startup circuit includes: a fifth transistor, a fifth resistor, a sixth transistor, a seventh transistor, an eleventh MOS transistor and a twelfth MOS transistor; The base of the fifth transistor is connected to the collector of the fifth transistor and the first end of the fifth resistor; the emitter of the fifth transistor is connected to the collector of the sixth transistor and the drain of the eleventh MOS transistor; The second end of the fifth resistor is connected to the source of the eleventh MOS transistor and the source of the twelfth MOS transistor, and together serves as the first end of the startup circuit and is connected to the fourth end of the pre-bias circuit, the third end of the core circuit, and the preset voltage source; The gate of the eleventh MOS transistor is connected to the gate of the twelfth MOS transistor, the drain of the twelfth MOS transistor, the collector of the seventh transistor, the base of the seventh transistor, and the base of the sixth transistor, and collectively serves as the second end of the startup circuit and is connected to the fourth end of the pre-bias circuit, the third end of the core circuit, and the preset voltage source; The emitter of the seventh transistor is connected to the emitter of the sixth transistor and is grounded.

8. The bandgap reference power supply circuit according to claim 7, wherein: The startup circuit further includes: a thirteenth MOS transistor, a fourteenth MOS transistor and a sixth resistor; The gate of the thirteenth MOS transistor is connected to the emitter of the fifth transistor, the collector of the sixth transistor, and the drain of the eleventh MOS transistor; the drain of the thirteenth MOS transistor is connected to the gate of the twelfth MOS transistor, the drain of the twelfth MOS transistor, and the gate of the eleventh MOS transistor; the source of the thirteenth MOS transistor is connected to the base of the seventh transistor, the collector of the seventh transistor, and the base of the sixth transistor; A first end of the sixth resistor is connected to the emitter of the seventh transistor; a second end of the sixth resistor is connected to the emitter of the sixth transistor and is grounded; The drain of the fourteenth MOS transistor is connected to the first end of the fifth resistor, the collector of the fifth transistor, and the base of the fifth transistor; the source of the fourteenth MOS transistor is grounded; and the gate of the fourteenth MOS transistor serves as the third end of the startup circuit and is connected to the fifth end of the pre-bias circuit.

9. The bandgap reference power supply circuit according to any one of claims 1 to 8, wherein: Also includes: The fifteenth MOS tube and the sixteenth MOS tube; The gate of the fifteenth MOS transistor is connected to the drain of the fifteenth MOS transistor, the gate of the sixteenth MOS transistor and the bias current source; the source of the fifteenth MOS transistor is grounded; The drain of the sixteenth MOS transistor is connected to the source of the first MOS transistor and the source of the second MOS transistor; the source of the sixteenth MOS transistor is grounded.

10. An electronic device, characterized in that: The invention comprises the bandgap reference power supply circuit according to any one of claims 1 to 9.

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