Self-biased low-temperature-drift band-gap reference voltage source

Abstract

The utility model discloses a self-biased low-temperature-drift band-gap reference voltage source, which isolates a power supply voltage from a self-biased operational amplifier and a band-gap reference core circuit by introducing a pre-voltage-stabilizing circuit, so that the bias current and the output voltage of the band-gap reference voltage source do not depend on the change of the power supply voltage. The low-frequency power supply rejection ratio of the band-gap reference voltage source is improved; a biasing circuit of the operational amplifier is simplified by utilizing a self-biasing technology, and reference voltage which is less influenced by temperature drift is provided for the pre-voltage-stabilizing circuit; considering that the temperature drift coefficient of the first-order reference voltage output by the band-gap reference core circuit is large, a low-power-consumption segmented compensation circuit with a simple structure is adopted, high and low temperature compensation currents with different magnitudes are output in set high and low temperature intervals, high-order compensation of the first-order reference voltage is achieved, the temperature range of the reference voltage is widened, and meanwhile the temperature drift coefficient of the first-order reference voltage is increased. The temperature drift coefficient of the reference voltage is greatly reduced, and the precision of the output reference voltage is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuits, in particular to a self-biased, low-temperature drift bandgap reference voltage source. Background Art

[0002] With the rapid development of microelectronics technology, the performance requirements for analog circuits are becoming increasingly stringent. Bandgap voltage references are one of the most important modules in analog circuits. Their principle is to add positive and negative voltages with different temperature coefficients to produce a reference voltage that is approximately independent of temperature and power supply. Bandgap voltage references are widely used in circuits such as low-dropout linear regulators (LDOs), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). Traditional first-order bandgap voltage references suffer from significant output voltage drift over a wide temperature range. Their power supply rejection ratio (PSRR) cannot be increased sufficiently at low frequencies due to the limited loop gain, resulting in a failure to meet the reference voltage accuracy requirements in practical applications. Therefore, reducing temperature drift and improving the PSRR are key issues in the research of bandgap voltage references. Utility Model Content

[0003] The utility model aims to solve the problems of large temperature drift of the output voltage of a first-order bandgap reference voltage source and poor low-frequency power supply suppression, and provides a self-biased, low-temperature drift bandgap reference voltage source.

[0004] In order to solve the above problems, the present invention is achieved through the following technical solutions:

[0005] A self-biased, low-temperature drift bandgap reference voltage source is characterized in that it is composed of a pre-stabilizing circuit, a self-biased operational amplifier, a bandgap reference core circuit, and a segmented compensation circuit; the input of the pre-stabilizing circuit is connected to a power supply VDD, a ground GND, and an internal feedback reference voltage VBN of the self-biased operational amplifier, and the output of the pre-stabilizing circuit sends out a pre-stabilized voltage VDDA; the input of the self-biased operational amplifier is connected to the pre-stabilized voltage VDDA of the pre-stabilizing circuit, the ground GND, and the in-phase voltage VNP and the inverting voltage VNM of the bandgap reference core circuit; the output of the self-biased operational amplifier sends out the internal feedback reference voltage VBN and the positive temperature coefficient voltage VPTAT; the bandgap reference The input of the core circuit is connected to the pre-regulated voltage VDDA of the pre-regulated circuit, the ground GND, the positive temperature coefficient voltage VPTAT of the self-biased operational amplifier, and the high-order compensation current IBC of the segmented compensation circuit. The output of the bandgap reference core circuit sends out the common-phase voltage VNP, the reverse-phase voltage VNM, the negative temperature coefficient voltage VCTAT, and the output reference voltage VREF. The input of the segmented compensation circuit is connected to the pre-regulated voltage VDDA of the pre-regulated circuit, the ground GND, the positive temperature coefficient voltage VPTAT of the self-biased operational amplifier, and the negative temperature coefficient voltage VCTAT of the bandgap reference core circuit. The output of the segmented compensation circuit sends out the high-order compensation current IBC.

[0006] In the above scheme, the pre-regulator circuit is composed of a PMOS transistor MP1, resistors R1 and R2, and an error amplifier OPAMP; the source of the PMOS transistor MP1 is connected to the power supply VDD; one end of the resistor R2 is connected to the ground GND; the inverting input of the error amplifier OPAMP is connected to the internal feedback reference voltage VBN; the non-inverting input of the error amplifier OPAMP, the other end of the resistor R2, and one end of the resistor R1 are connected; the output of the error amplifier OPAMP is connected to the gate of the PMOS transistor MP1; the drain of the PMOS transistor MP1 is connected to the other end of the resistor R1 to output the pre-regulated voltage VDDA.

[0007] In the above scheme, the self-biased operational amplifier is composed of NMOS transistors MN1 to MN8, PMOS transistors MP2 to MP7, and resistor R3; the sources of the PMOS transistors MP2, MP4, and MP6 are connected and then connected to the pre-regulated voltage VDDA; the sources of the NMOS transistors MN1, MN4, MN6, and MN8 are connected and then connected to the ground GND; the gate of the NMOS transistor MN2 is connected to the in-phase voltage VNP; the gate of the NMOS transistor MN3 is connected to the inverting voltage VNM; the source of the PMOS transistor MP3 is connected to the drain of the PMOS transistor MP2; the gates of the PMOS transistors MP2, MP3, MP5, and MP7 are connected to the drains of the PMOS transistor MP3 and the NMOS transistor MN1; the source of the PMOS transistor MP5 is connected to the drains of the PMOS transistors MP4 and the NMOS transistor MN2 The gates of the NMOS transistors MN5 and MN7, the drain of the PMOS transistor MP5, and one end of the resistor R3 are connected; the gates of the NMOS transistors MN1, MN4, MN6, and MN8 are connected to the other end of the resistor R3 to output an internal feedback reference voltage VBN; the gates of the PMOS transistors MP4 and MP6 and the drains of the PMOS transistors MP7 and NMOS transistor MN7 are connected to output a positive temperature coefficient voltage VPTAT.

[0008] In the above scheme, the bandgap reference core circuit is composed of PMOS transistors MP8 to MP10, NMOS transistors MN9 and MN10, PNP transistors Q1 to Q3 and resistors R4 to R6; the sources of the PMOS transistors MP8, MP9 and MP10 are connected and then connected to the pre-regulated voltage VDDA; the bases and collectors of the PNP transistors Q1, Q2 and Q3 are connected and then connected to the ground GND; the gates of the PMOS transistors MP8, MP9 and MP10 are connected and then connected to the positive temperature coefficient voltage VPTAT; one end of the resistor R5 and one end of the resistor R6 are connected and then connected to the high-order compensation current IBC; the PMOS transistor MP8 and the NMOS transistor MN9 are connected. The drain of the PNP transistor Q2 is connected to one end of the resistor R4; the emitter of the PNP transistor Q3 is connected to the other end of the resistor R6; the source of the NMOS transistor MN10 is connected to the other end of the resistor R4 to output a common-mode voltage VNP; the source of the NMOS transistor MN9 is connected to the emitter of the PNP transistor Q1 to output a negative-mode voltage VNM; the gates of the NMOS transistors MN9 and MN10 and the drains of the NMOS transistor MN10 and the PMOS transistor MP9 are connected to output a negative temperature coefficient voltage VCTAT; the drain of the PMOS transistor MP10 is connected to the other end of the resistor R5 to output an output reference voltage VREF.

[0009] In the above scheme, the segmented compensation circuit is composed of NMOS transistors MN11 to MN15, a PMOS transistor MP11, and a resistor R7. The source of the PMOS transistor MP11 is connected to the pre-regulated voltage VDDA; the sources of the NMOS transistors MN12 and MN15 are connected to the ground GND; the gate of the PMOS transistor MP11 is connected to the positive temperature coefficient voltage VPTAT; the gate of the NMOS transistor MN13 is connected to the negative temperature coefficient voltage VCTAT; the PMOS transistor MP11 is connected to the drain of the NMOS transistor MN13; the gates of the NMOS transistors MN11 and MN14, the source of the NMOS transistor MN13, and one end of the resistor R7 are connected; the gates of the NMOS transistors MN12 and MN15, the drain of the NMOS transistor MN14, and the other end of the resistor R7 are connected; the source of the NMOS transistor MN11 is connected to the drain of the NMOS transistor MN12, and the source of the NMOS transistor MN14 is connected to the drain of the NMOS transistor MN15; and the drain of the NMOS transistor MN11 outputs the high-order compensation current IBC.

[0010] Compared with the prior art, the present invention has the following characteristics:

[0011] 1. Considering that the temperature characteristic curve of the output voltage of the first-order reference source is usually a downward-opening curve, a curve with an upward opening is needed to be added to it for compensation, the utility model designs a simple-structured, low-power segmented compensation circuit to achieve high-order compensation, so that the temperature drift coefficient of the compensated reference voltage is significantly reduced in a wide temperature range.

[0012] 2. A pre-regulator circuit is used to isolate the power supply voltage from the bandgap reference core circuit, and self-bias technology is used to provide current bias for the operational amplifier while also providing the pre-regulator circuit with a reference voltage that is less affected by temperature, which significantly improves the low-frequency power supply rejection ratio of the bandgap reference circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 The circuit structure diagram of a self-biased low-temperature drift bandgap reference voltage source is shown in FIG.

[0014] Figure 2 Schematic diagram of the temperature characteristics of the first-order reference voltage output by the bandgap reference core circuit;

[0015] Figure 3 A schematic diagram of the temperature characteristics of the segmented compensation current of a self-biased, low-temperature drift bandgap reference voltage source;

[0016] Figure 4 This is a simulation diagram of the output voltage temperature characteristics of a self-biased, low-temperature drift bandgap reference voltage source;

[0017] Figure 5 The figure shows the output voltage power supply rejection ratio of a self-biased, low-temperature drift bandgap reference voltage source. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to specific examples and accompanying drawings.

[0019] A self-biased low-temperature drift bandgap reference voltage source, such as Figure 1As shown, the circuit consists of a pre-regulator circuit, a self-biased operational amplifier, a bandgap reference core circuit, and a segmented compensation circuit. The pre-regulator circuit's inputs are connected to power supply VDD, ground GND, and the self-biased operational amplifier's internal feedback reference voltage VBN. The pre-regulator circuit's output provides a pre-regulator voltage VDDA. The self-biased operational amplifier's inputs are connected to the pre-regulator circuit's pre-regulator voltage VDDA, ground GND, and the bandgap reference core circuit's non-inverting voltage VNP and inverting voltage VNM. The self-biased operational amplifier's output provides the internal feedback reference voltage VBN and a positive temperature coefficient voltage VPTAT. The bandgap reference core circuit's inputs are connected to the pre-regulator circuit's pre-regulator voltage VDDA, ground GND, the self-biased operational amplifier's positive temperature coefficient voltage VPTAT, and the segmented compensation circuit's high-order compensation current IBC. The bandgap reference core circuit's output provides a non-inverting voltage VNP, an inverting voltage VNM, a negative temperature coefficient voltage VCTAT, and the output reference voltage VREF. The input of the segmented compensation circuit is connected to the pre-regulated voltage VDDA of the pre-regulated circuit, the ground GND, the positive temperature coefficient voltage VPTAT of the self-biased operational amplifier and the negative temperature coefficient voltage VCTAT of the bandgap reference core circuit. The output of the segmented compensation circuit sends out a high-order compensation current IBC.

[0020] The pre-regulator circuit consists of a PMOS transistor MP1, resistors R1 and R2, and an error amplifier OPAMP. The source of the PMOS transistor MP1 is connected to the power supply VDD; one end of the resistor R2 is connected to the ground GND; and the inverting input of the error amplifier OPAMP is connected to the internal feedback reference voltage VBN. The non-inverting input of the error amplifier OPAMP, the other end of the resistor R2, and one end of the resistor R1 are connected; the output of the error amplifier OPAMP is connected to the gate of the PMOS transistor MP1. The drain of the PMOS transistor MP1 is connected to the other end of the resistor R1 and then outputs a pre-regulated voltage VDDA. The error amplifier OPAMP of the pre-regulator circuit amplifies the difference between the internal feedback reference voltage VBN and the sampled voltage to output an error voltage, thereby driving the PMOS transistor MP1 to generate the pre-regulated voltage VDDA that powers the subsequent stage, thereby improving the circuit's low-frequency power supply rejection ratio.

[0021] The self-biased operational amplifier is composed of NMOS transistors MN1-MN8, PMOS transistors MP2-MP7, and resistor R3. The sources of PMOS transistors MP2, MP4, and MP6 are connected to a pre-regulated voltage VDDA. The sources of NMOS transistors MN1, MN4, MN6, and MN8 are connected to ground GND. The gate of NMOS transistor MN2 is connected to a positive-phase voltage VNP. The gate of NMOS transistor MN3 is connected to a negative-phase voltage VNM. The source of the PMOS transistor MP3 is connected to the drain of the PMOS transistor MP2; the gates of the PMOS transistors MP2, MP3, MP5, and MP7 are connected to the drains of the PMOS transistor MP3 and the NMOS transistor MN1; the source of the PMOS transistor MP5 is connected to the drains of the PMOS transistor MP4 and the NMOS transistor MN2; the source of the PMOS transistor MP7 is connected to the drain of the PMOS transistor MP6 and the NMOS transistor MN3; the sources of the NMOS transistors MN2 and MN3 are connected to the drain of the NMOS transistor MN4; the source of the NMOS transistor MN5 is connected to the drain of the NMOS transistor MN6; the source of the NMOS transistor MN7 is connected to the drain of the NMOS transistor MN8; the gates of the NMOS transistors MN5 and MN7, the drain of the PMOS transistor MP5, and one end of the resistor R3 are connected. The gates of NMOS transistors MN1, MN4, MN6, and MN8 are connected to the other end of resistor R3 to generate the internal feedback reference voltage VBN. The gates of PMOS transistors MP4 and MP6, and the drains of PMOS transistors MP7 and NMOS transistor MN7, are connected to generate the positive temperature coefficient voltage VPTAT. Self-biased operational amplifiers utilize self-biasing technology to generate a bias current independent of the power supply. By participating in the construction of positive and negative feedback loops, they improve loop gain, reference voltage accuracy, and stability.

[0022] The bandgap reference core circuit comprises PMOS transistors MP8-MP10, NMOS transistors MN9 and MN10, PNP transistors Q1-Q3, and resistors R4-R6. The sources of the PMOS transistors MP8, MP9, and MP10 are connected to a pre-regulated voltage VDDA; the bases and collectors of the PNP transistors Q1, Q2, and Q3 are connected to ground GND; the gates of the PMOS transistors MP8, MP9, and MP10 are connected to a positive temperature coefficient voltage VPTAT; one end of resistor R5 is connected to one end of resistor R6, and a high-order compensation current IBC is connected. The drain of the PMOS transistor MP8 is connected to the drain of the NMOS transistor MN9; the emitter of the PNP transistor Q2 is connected to one end of resistor R4; and the emitter of the PNP transistor Q3 is connected to the other end of resistor R6. The source of NMOS transistor MN10 is connected to the other end of resistor R4 to generate a positive-phase voltage VNP. The source of NMOS transistor MN9 is connected to the emitter of PNP transistor Q1 to generate a negative-phase voltage VNM. The gates of NMOS transistors MN9 and MN10, and the drains of NMOS transistors MN10 and PMOS transistor MP9, are connected to generate a negative temperature coefficient voltage VCTAT. The drain of PMOS transistor MP10 is connected to the other end of resistor R5 to generate an output reference voltage VREF. The bandgap reference core circuit adds the positive and negative temperature coefficient voltages using a specific proportionality factor to output a first-order compensated bandgap reference voltage.

[0023] The segmented compensation circuit consists of NMOS transistors MN11-MN15, a PMOS transistor MP11, and a resistor R7. The source of the PMOS transistor MP11 is connected to a pre-regulated voltage VDDA; the sources of the NMOS transistors MN12 and MN15 are connected to ground GND; the gate of the PMOS transistor MP11 is connected to a positive temperature coefficient voltage VPTAT; and the gate of the NMOS transistor MN13 is connected to a negative temperature coefficient voltage VCTAT. The PMOS transistor MP11 is connected to the drain of the NMOS transistor MN13; the gates of the NMOS transistors MN11 and MN14, the source of the NMOS transistor MN13, and one end of the resistor R7 are connected; the gates of the NMOS transistors MN12 and MN15, the drain of the NMOS transistor MN14, and the other end of the resistor R7 are connected; the source of the NMOS transistor MN11 is connected to the drain of the NMOS transistor MN12, and the source of the NMOS transistor MN14 is connected to the drain of the NMOS transistor MN15. The drain of the NMOS transistor MN11 outputs a high-order compensation current IBC. The segmented compensation circuit improves the temperature drift coefficient of the bandgap reference output voltage by outputting high and low temperature compensation currents of different sizes in the set high and low temperature ranges.

[0024] The working principle of this utility model is:

[0025] The core circuit of the bandgap reference generates a first-order compensated reference voltage that is less affected by temperature by adding a negative temperature coefficient voltage and a positive temperature coefficient voltage at a certain coefficient; the negative temperature coefficient voltage is generated by using the junction voltage V between the emitter and base of the PNP transistors Q1 and Q3. EB The positive temperature coefficient voltage is generated by using PNP transistors Q1 and Q2 with different sizes but the same current flowing through them, so that the junction voltage V between the emitter and the base EB The relationship between the difference and temperature is a positive proportional coefficient characteristic, and the positive temperature coefficient voltage ΔV BE It can be expressed as;

[0026] ΔV BE =V BE1 -V BE2 =V T *lnn

[0027] Where n = 8, V T is the thermal voltage. Assuming I is the current flowing through PNP transistors Q1 and Q2, it can be expressed as:

[0028]

[0029] When designing the circuit, resistors R1 to R7 with the same temperature coefficient and block value are used. The reference voltage for the output first-order compensation can be expressed as:

[0030]

[0031] Here, k is a ratio coefficient of the number of transistors in the PMOS transistor MP9 and the PMOS transistor MP10.

[0032] Figure 2 The figure is a schematic diagram of the temperature characteristics of the first-order reference voltage output by the bandgap reference core circuit. As can be seen from the figure, the temperature characteristic curve of the first-order reference voltage output by the bandgap reference core circuit is a downward-opening curve. A compensation circuit is designed to extract a downward-opening current, generate an upward-opening voltage after passing through a resistor, and add it to the current to achieve high-order compensation.

[0033] Figure 3This is a schematic diagram of the temperature characteristics of the segmented compensation current of a self-biased, low-temperature drift bandgap reference voltage source. As can be seen from the figure, the output current drawn before the set temperature node increases with increasing temperature, and the output current drawn after the set temperature node decreases with increasing temperature. Since the high-order compensation current is the current drawn through the resistor, the inversion results in an upward-opening voltage compensation curve. When the negative temperature coefficient current ICTAT is greater than the positive temperature coefficient current IPTAT, the NMOS tube MN13 operates in the linear region, and the IBC output terminal draws a positive temperature coefficient current; when the positive temperature coefficient current IPTAT is greater than the negative temperature coefficient current ICTAT, the PMOS tube MP11 transitions from the saturation region to the linear region, and the IBC output terminal draws a negative temperature coefficient current. The compensated segmented current can be expressed as:

[0034]

[0035] Wherein T0 is a set temperature node, the proportional coefficient k1 is changed by changing the ratio of the number of transistors of the PMOS transistor MP9 to the PMOS transistor MP11, and the proportional coefficient k2 is changed by changing the ratio of the number of transistors of the NMOS transistor MN10 to the NMOS transistor MN12.

[0036] Figure 4 This is a simulation diagram of the output voltage temperature characteristics of a self-biased, low-temperature drift bandgap reference voltage source. As can be seen from the figure, the output voltage of the reference source after high-order compensation has multiple turning points, fluctuating by 0.582mV between -60℃ and 130℃. Compared with the 2.68mV fluctuation of the first-order reference voltage output by the bandgap reference core circuit between -60℃ and 130℃, it is reduced by 78.28%, making the temperature drift coefficient only 2.43ppm.

[0037] Figure 5 This is a simulation diagram of the output voltage power supply rejection ratio of a self-biased, low-temperature drift bandgap reference voltage source. It can be seen from the figure that the low-frequency power supply rejection ratio of the circuit is 63dB when the pre-regulator circuit is not added. After adding the pre-regulator circuit, the low-frequency power supply rejection ratio of the circuit is 125dB, and the low-frequency power supply rejection is significantly improved.

[0038] The utility model isolates the power supply voltage from the self-biased operational amplifier and the bandgap reference core circuit by introducing a pre-stabilizer circuit, so that the bias current and output voltage of the bandgap reference voltage source do not depend on the change of the power supply voltage, thereby improving the low-frequency power supply rejection ratio of the bandgap reference voltage source; utilizes the self-bias technology to simplify the bias circuit of the operational amplifier, and provides the pre-stabilizer circuit with a reference voltage that is less affected by temperature drift; considering that the temperature drift coefficient of the first-order reference voltage output by the bandgap reference core circuit is large, a simple-structured, low-power segmented compensation circuit is adopted to output high and low-temperature compensation currents of different sizes within the set high and low temperature ranges, thereby realizing high-order compensation of the first-order reference voltage, broadening the temperature range of the reference voltage, significantly reducing the temperature drift coefficient of the reference voltage, and improving the output reference voltage accuracy.

[0039] It should be noted that although the embodiments described above are illustrative, they are not intended to limit the present invention. Therefore, the present invention is not limited to the above-mentioned specific embodiments. Without departing from the principles of the present invention, any other embodiments obtained by those skilled in the art under the guidance of the present invention are deemed to be within the protection of the present invention.

Claims

1. A self-biased low-temperature drift bandgap reference voltage source, characterized in that: It consists of a pre-regulator circuit, a self-biased operational amplifier, a bandgap reference core circuit and a segmented compensation circuit; The input of the pre-regulator circuit is connected to the power supply VDD, the ground GND and the internal feedback reference voltage VBN of the self-biased operational amplifier, and the output of the pre-regulator circuit sends out the pre-regulated voltage VDDA; The input of the self-biased operational amplifier is connected to the pre-regulated voltage VDDA of the pre-regulated circuit, the ground GND, and the in-phase voltage VNP and the inverting voltage VNM of the bandgap reference core circuit; the output of the self-biased operational amplifier sends out the internal feedback reference voltage VBN and the positive temperature coefficient voltage VPTAT; The input of the bandgap reference core circuit is connected to the pre-regulated voltage VDDA of the pre-regulated circuit, the ground GND, the positive temperature coefficient voltage VPTAT of the self-biased operational amplifier, and the high-order compensation current IBC of the segmented compensation circuit. The output of the bandgap reference core circuit sends out the common-phase voltage VNP, the reverse-phase voltage VNM, the negative temperature coefficient voltage VCTAT, and the output reference voltage VREF. The input of the segmented compensation circuit is connected to the pre-regulated voltage VDDA of the pre-regulated circuit, the ground GND, the positive temperature coefficient voltage VPTAT of the self-biased operational amplifier and the negative temperature coefficient voltage VCTAT of the bandgap reference core circuit. The output of the segmented compensation circuit sends out a high-order compensation current IBC.

2. The self-biased low-temperature drift bandgap reference voltage source according to claim 1, wherein: The pre-regulator circuit consists of a PMOS tube MP1, resistors R1, R2 and an error amplifier OPAMP; The source of the PMOS transistor MP1 is connected to the power supply VDD; one end of the resistor R2 is connected to the ground GND; the inverting input of the error amplifier OPAMP is connected to the internal feedback reference voltage VBN; The non-inverting input terminal of the error amplifier OPAMP, the other end of the resistor R2 and one end of the resistor R1 are connected; the output terminal of the error amplifier OPAMP is connected to the gate of the PMOS tube MP1; The drain of the PMOS transistor MP1 is connected to the other end of the resistor R1 to output a pre-regulated voltage VDDA.

3. The self-biased low-temperature drift bandgap reference voltage source according to claim 1, wherein: The self-biased operational amplifier is composed of NMOS transistors MN1 to MN8, PMOS transistors MP2 to MP7 and resistor R3; The sources of the PMOS transistors MP2, MP4, and MP6 are connected and then connected to the pre-regulated voltage VDDA; the sources of the NMOS transistors MN1, MN4, MN6, and MN8 are connected and then connected to the ground GND; the gate of the NMOS transistor MN2 is connected to the in-phase voltage VNP; the gate of the NMOS transistor MN3 is connected to the inverting voltage VNM; The source of the PMOS transistor MP3 is connected to the drain of the PMOS transistor MP2; the gates of the PMOS transistors MP2, MP3, MP5, and MP7 are connected to the drains of the PMOS transistor MP3 and the NMOS transistor MN1; the source of the PMOS transistor MP5 is connected to the drains of the PMOS transistor MP4 and the NMOS transistor MN2; the source of the PMOS transistor MP7 is connected to the drain of the PMOS transistor MP6 and the NMOS transistor MN3; the sources of the NMOS transistors MN2 and MN3 are connected to the drain of the NMOS transistor MN4; the source of the NMOS transistor MN5 is connected to the drain of the NMOS transistor MN6; the source of the NMOS transistor MN7 is connected to the drain of the NMOS transistor MN8; the gates of the NMOS transistors MN5 and MN7, the drain of the PMOS transistor MP5, and one end of the resistor R3 are connected; The gates of the NMOS transistors MN1, MN4, MN6 and MN8 are connected to the other end of the resistor R3 to output an internal feedback reference voltage VBN; the gates of the PMOS transistors MP4 and MP6 and the drains of the PMOS transistors MP7 and NMOS transistor MN7 are connected to output a positive temperature coefficient voltage VPTAT.

4. The self-biased, low-temperature drift bandgap reference voltage source according to claim 1, wherein: The bandgap reference core circuit is composed of PMOS transistors MP8 to MP10, NMOS transistors MN9 and MN10, PNP transistors Q1 to Q3 and resistors R4 to R6; The sources of the PMOS transistors MP8, MP9, and MP10 are connected and then connected to the pre-regulated voltage VDDA; the bases and collectors of the PNP transistors Q1, Q2, and Q3 are connected and then connected to the ground GND; the gates of the PMOS transistors MP8, MP9, and MP10 are connected and then connected to the positive temperature coefficient voltage VPTAT; one end of the resistor R5 and one end of the resistor R6 are connected and then connected to the high-order compensation current IBC; The drain of the PMOS transistor MP8 is connected to the drain of the NMOS transistor MN9; the emitter of the PNP transistor Q2 is connected to one end of the resistor R4; the emitter of the PNP transistor Q3 is connected to the other end of the resistor R6; The source of the NMOS transistor MN10 is connected to the other end of the resistor R4 to output a common-mode voltage VNP. The source of the NMOS transistor MN9 is connected to the emitter of the PNP transistor Q1 to output a negative-mode voltage VNM. The gates of the NMOS transistors MN9 and MN10 and the drains of the NMOS transistors MN10 and PMOS transistor MP9 are connected to output a negative temperature coefficient voltage VCTAT. The drain of the PMOS transistor MP10 is connected to the other end of the resistor R5 to output an output reference voltage VREF.

5. The self-biased low-temperature drift bandgap reference voltage source according to claim 1, wherein: The segmented compensation circuit is composed of NMOS transistors MN11 to MN15, PMOS transistor MP11 and resistor R7; The source of the PMOS transistor MP11 is connected to the pre-regulated voltage VDDA; the sources of the NMOS transistors MN12 and MN15 are connected to the ground GND; the gate of the PMOS transistor MP11 is connected to the positive temperature coefficient voltage VPTAT; the gate of the NMOS transistor MN13 is connected to the negative temperature coefficient voltage VCTAT; The PMOS transistor MP11 is connected to the drain of the NMOS transistor MN13; the gates of the NMOS transistors MN11 and MN14, the source of the NMOS transistor MN13, and one end of the resistor R7 are connected; the gates of the NMOS transistors MN12 and MN15, the drain of the NMOS transistor MN14, and the other end of the resistor R7 are connected; the source of the NMOS transistor MN11 is connected to the drain of the NMOS transistor MN12, and the source of the NMOS transistor MN14 is connected to the drain of the NMOS transistor MN15. The drain of the NMOS transistor MN11 sends out a high-order compensation current IBC.

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