Cell region structure of IGBT chip and IGBT chip

Abstract

The utility model relates to the technology of semiconductor devices, and discloses a cellular region structure of an IGBT chip and the IGBT chip, which comprises a substrate and a P well region arranged at a hollow part on the front surface of the substrate, the two Poly gates longitudinally penetrate through the P well region, and the silicide region is arranged at the hollowed part of the upper surface of the P well region between the two Poly gates; an oxide layer is arranged on the front surface of the substrate, the P well region and the Poly gate, and the Poly gate is isolated from the substrate, the P well region and the silicide region by the oxide layer; a dielectric layer and a front metal layer which longitudinally penetrates through the dielectric layer and is in contact with the silicide region are arranged on the oxide layer and the silicide region; and a buffer layer, a P-type doped layer and a back metal layer are sequentially arranged below the back of the substrate. The utility model aims to enable the IGBT chip to have a natural anti-latch-up characteristic so as to eliminate a corresponding latch-up effect.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, in particular to a cell region structure of an IGBT chip and the IGBT chip. Background Art

[0002] The IGBT (Insulated Gate Bipolar Transistor) is a high-power semiconductor device that combines the high switching frequency and controllability of MOS devices with the high current handling capability of BJTs (bipolar junction transistors). It is widely used in industrial frequency conversion, consumer electronics, rail transportation, new energy, and aerospace. In traditional trench-gate IGBT chips, a high-dose P or As ion implantation is typically used to form an N+ source to supply electrons when the channel is turned on. This, together with the gate, the underlying P-well region, and the N-type drift layer, forms a positive MOSFET structure, controlling the chip's switching state.

[0003] However, in this case, in an area far from the gate, the heavily doped N-type source forms an N+P junction with the underlying P-well region. Vertically within this region, the N-type drift layer and the P-type anode further form an NPNP structure. When the P-well region's potential rises, the N+P junction between the N+ source and the P-well region can be triggered, leading to a latch-up effect. This causes the current to increase dramatically and uncontrollably, potentially damaging the chip.

[0004] The above content is only used to assist in understanding the technical solution of the present invention and does not constitute an admission that the above content is prior art. Utility Model Content

[0005] The utility model provides a cell region structure of an IGBT chip and an IGBT chip, aiming to enable the IGBT chip to have a natural anti-latchup characteristic so as to eliminate the corresponding latchup effect.

[0006] To achieve the above objectives, the present invention proposes a cell region structure of an IGBT chip, comprising:

[0007] A substrate and a P-well region provided in a hollowed-out portion of a front surface of the substrate;

[0008] Two Poly gates vertically passing through the P-well region, and a silicide region provided in the hollowed-out portion of the upper surface of the P-well region between the two Poly gates;

[0009] An oxide layer is provided on the front surface of the substrate, the P-well region, and the Poly gate, and the oxide layer also isolates the Poly gate from the substrate, the P-well region, and the silicide region;

[0010] A dielectric layer is provided on the oxide layer and the silicide region, and a front metal layer vertically penetrates the dielectric layer and contacts the silicide region;

[0011] A buffer layer, a P-type doping layer and a back metal layer are sequentially arranged under the back side of the substrate.

[0012] Optionally, the cellular region structure further includes:

[0013] A passivation layer is provided on the dielectric layer and the front metal layer, and is divided into a left passivation layer and a right passivation layer, with a lateral gap between the left passivation layer and the right passivation layer.

[0014] Optionally, the thickness of the dielectric layer ranges from 9000 to 12000 Å.

[0015] Optionally, the dielectric layer is a double-layer structure of USG+BPSG.

[0016] Optionally, the Poly gate is connected to the metal gate of the IGBT chip based on a Busbar routing.

[0017] Optionally, the thickness of the front metal layer ranges from 8 to 12 μm;

[0018] And / or, the thickness of the back metal layer is in the range of 1 to 2 μm.

[0019] Optionally, the buffer layer is an N-type doped layer.

[0020] The present invention further proposes an IGBT chip, comprising a cellular region structure and a terminal region structure adapted to the cellular region structure; the cellular region structure is the cellular region structure of the IGBT chip as described above.

[0021] The beneficial effect of the technical solution of the present utility model is that: by using the contact between the silicide region and the P-well region to form a Schottky contact, the NPNP structure in the traditional IGBT chip is replaced, so that the meta-cell structure of the IGBT chip has a natural anti-latch characteristic, eliminating the latch-up effect, thereby enhancing the robustness and stability of the IGBT chip working in extreme environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a structural diagram of an embodiment of the cell region structure of an IGBT chip of the present utility model;

[0023] Figure 2 This is a structural diagram of another embodiment of the cell region structure of the IGBT chip of the present invention.

[0024] Description of reference numerals:

[0025] 1. Substrate; 2. P-well region; 3. Poly gate; 4. Silicide region; 5. Oxide layer; 6. Dielectric layer; 7. Front metal layer; 8. Buffer layer; 9. P-type doped layer; 10. Back metal layer; 11. Passivation layer.

[0026] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the schemes in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0028] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0029] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element.

[0030] Furthermore, if terms such as "first" or "second" are used in this utility model, they are used solely for descriptive purposes (e.g., to distinguish identical or similar components) and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include at least one such feature. Furthermore, the technical solutions of various embodiments may be combined, but only if they are achievable by persons of ordinary skill in the art. If a combination of technical solutions contradicts or is unachievable, such combination shall be deemed non-existent and outside the scope of protection claimed by this utility model.

[0031] The utility model proposes a cell area structure of an IGBT chip, referring to Figure 1 , the cell area structure of the IGBT chip includes:

[0032] A substrate 1, and a P-well region 2 provided in a hollowed-out portion of the front surface of the substrate 1;

[0033] Two Poly gates 3 vertically passing through the P-well region 2, and a silicide region 4 provided in a hollowed-out portion of the upper surface of the P-well region 2 between the two Poly gates 3;

[0034] An oxide layer 5 is provided on the front surface of the substrate 1, the P-well region 2, and the Poly gate 3, and the oxide layer 5 also isolates the Poly gate 3 from the substrate 1, the P-well region 2, and the silicide region 4;

[0035] A dielectric layer 6 is provided on the oxide layer 5 and the silicide region 4, and a front metal layer 7 vertically penetrating the dielectric layer 6 and contacting the silicide region 4;

[0036] A buffer layer 8 , a P-type doping layer 9 and a back metal layer 10 are sequentially provided below the back surface of the substrate 1 .

[0037] In this embodiment, the substrate 1 is the basis of the entire IGBT chip and may be a single crystal silicon substrate.

[0038] A hollow portion is formed on the front side of the substrate 1 , and a P-well region 2 (ie, P-well) is provided in the hollow portion. Two Poly gates 3 are provided in the substrate 1 and the P-well region 2 , vertically passing through the P-well region 2 .

[0039] A hollowed area is formed on the upper surface of the P-well region 2 between the two Poly gates 3, and a silicide region 4 is provided in the hollowed area. The silicide region 4 may be a silicide (mainly SiTi) alloy region.

[0040] An oxide layer 5 is provided on the front surface of the substrate 1 , the P-well region 2 , and the Poly gate 3 , and the oxide layer 5 also isolates the Poly gate 3 from the substrate 1 , the P-well region 2 , and the silicide region 4 .

[0041] A dielectric layer 6 is provided above the oxide layer 5 and the silicide region 4, as well as a front metal layer 7 that vertically penetrates the dielectric layer 6 and contacts the silicide region 4. The front metal layer 7 also partially covers the dielectric layer 6. The dielectric layer 6 may be an ILD (InterLayer Dielectric) dielectric layer.

[0042] On the back side of the substrate 1 , a buffer layer 8 , a P-type doping layer 9 and a back side metal layer 10 are sequentially provided from top to bottom.

[0043] The front metal layer 7 serves as the front cathode metal, and the back metal layer 10 serves as the back anode metal.

[0044] Because the silicide region 4 contacts (forms an electrical connection) with the front metal layer 7, and the P-type doped layer 9 acts as a back anode and contacts (forms an electrical connection) with the back metal layer 10, when the channel is conducting, the silicide region 4 provides electrons, performing the same function as the N+ source in a conventional IGBT chip. Simultaneously, the contact with the underlying P-well region 2 is a Schottky contact, thus replacing the N-type doped source in conventional IGBT chips. Because there is no complete NPNP structure along the longitudinal direction of the IGBT chip, this IGBT chip's metacell structure has inherent latch-up resistance, preventing latch-up failure under any circumstances. This enhances the chip's robustness and stability in extreme operating environments. Furthermore, because the front cathode metal (i.e., the front metal layer 7) directly contacts the P-well region 2 through the silicide region 4, the dry etching and B+ ion implantation steps following N+ ion doping in conventional IGBT chips are eliminated, thereby shortening the IGBT chip's manufacturing cycle and production costs.

[0045] In one embodiment, a Schottky contact is formed by using the contact between the silicide region 4 and the P-well region 2 to replace the NPNP structure in the traditional IGBT chip, so that the metacell structure of the IGBT chip has a natural anti-latch characteristic, eliminating the latch-up effect, thereby enhancing the robustness and stability of the IGBT chip working in extreme environments.

[0046] In addition, since the front cathode metal (i.e., the front metal layer 7) is in direct contact with the P-well region 2 through the silicide region 4, the process steps of CT etching and B+ injection after N+ doping in traditional IGBT chips are omitted, which can shorten the manufacturing cycle and production cost of the IGBT chip.

[0047] In one embodiment, based on the above embodiment, referring to Figure 2 , the cellular region structure further includes:

[0048] A passivation layer 11 is provided on the dielectric layer 6 and the front metal layer 7 , and is divided into a left passivation layer and a right passivation layer, with a lateral gap between the left passivation layer and the right passivation layer.

[0049] In this embodiment, the passivation layer 11 serves as an electrical insulation layer to protect the front metal layer 7 and the dielectric layer 6, thereby preventing unnecessary current leakage and ensuring stable electrical performance within the device.

[0050] At the same time, the passivation layer 11 can provide environmental protection, prevent oxygen, moisture and other harmful substances from damaging the device, and increase the durability and service life of the device.

[0051] Furthermore, the addition of left and right passivation layers can help improve the distribution of the electric field, reduce local electric field strength, and help reduce the risk of electrical breakdown and failure. The lateral spacing between the left and right passivation layers promotes efficient heat dissipation, helping to avoid localized excessive heating. The spacing between the passivation layers 11 effectively reduces parasitic capacitance, minimizing the impact on device performance and improving switching speed.

[0052] In one embodiment, based on the above embodiment, the thickness of the dielectric layer 6 is in the range of 9000-12000 Å.

[0053] Optionally, the dielectric layer 6 is a double-layer structure of USG+BPSG.

[0054] The USG layer provides good insulation performance, and the BPSG layer enhances the mechanical strength and structural stability of the dielectric layer 6 , thereby jointly ensuring electrical isolation performance.

[0055] In one embodiment, based on the above embodiment, the Poly gate 3 is connected to the metal gate of the IGBT chip based on a Busbar trace.

[0056] In this embodiment, the Poly gate 3 is generally made of polycrystalline silicon material, which is more adaptable to high temperature and high electric field environments than single crystal silicon and has good electrical characteristics.

[0057] Busbar routing is used to efficiently transmit electrical energy within a circuit. By connecting multiple components (such as multiple IGBT chips) together, an efficient current distribution system is formed. This routing design helps reduce line resistance, thereby reducing power consumption and heat generation.

[0058] The busbar routing design of Poly Gate 3 forms electrical contact with the metal gate, ensuring stable and reliable signal transmission. This connection improves gate voltage and switching control performance.

[0059] In one embodiment, based on the above embodiment, the thickness of the front metal layer 7 is in the range of 8 to 12 μm;

[0060] And / or, the thickness of the back metal layer 10 is in the range of 1 to 2 μm.

[0061] In one embodiment, based on the above embodiment, the buffer layer 8 is an N-type doped layer.

[0062] In this embodiment, the buffer layer 8 is generally designed to provide electrical isolation between different materials of the IGBT, prevent current leakage between different regions, and ensure the stability of device performance.

[0063] The N-type doped layer can help optimize the distribution of carriers, enhance device performance, improve conductivity and reduce switching losses.

[0064] The present utility model further proposes an IGBT chip, which includes a cell region structure and a terminal region structure. The specific structure of the cell region structure of the IGBT chip refers to the above-mentioned embodiment. Since the present IGBT chip adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the technical effects brought about by the technical solutions of the above-mentioned embodiments, which will not be described one by one here.

[0065] Among them, the terminal region structure is adapted to the cellular region structure.

[0066] In this embodiment, the cell region structure is the core component of the IGBT chip, responsible for the primary power conversion and control functions. Its design directly affects key IGBT indicators such as switching efficiency, conduction loss, and thermal performance. By optimizing the structure and materials, the cell region design can improve electrical characteristics such as switching speed and withstand voltage, while also reducing parasitic capacitance and inductance to adapt to high-frequency applications.

[0067] The termination region structure is often used to provide additional electrical protection, ensuring the safety and stability of devices in high voltage and high current applications. It can prevent damage to the cell region under extreme operating conditions.

[0068] The optimized connection between the terminal region and the cell region can ensure uniform current distribution, reduce hot spots and stress concentration, and enhance the stability of contact resistance.

[0069] In IGBT chip design, by creating a terminal region structure that matches the cell region structure, not only can the overall performance and reliability of the device be improved, but it can also ensure its safety and stability under various application conditions. This concept of mutually adaptive design provides strong support for the development of modern power devices.

[0070] The above description is only part or preferred embodiments of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural transformations made by using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.

Claims

1. A cell region structure of an IGBT chip, characterized in that: include: A substrate and a P-well region provided in a hollowed-out portion of a front surface of the substrate; Two Poly gates vertically passing through the P-well region, and a silicide region provided in the hollowed-out portion of the upper surface of the P-well region between the two Poly gates; An oxide layer is provided on the front surface of the substrate, the P-well region, and the Poly gate, and the oxide layer also isolates the Poly gate from the substrate, the P-well region, and the silicide region; A dielectric layer is provided on the oxide layer and the silicide region, and a front metal layer vertically penetrates the dielectric layer and contacts the silicide region; A buffer layer, a P-type doping layer and a back metal layer are sequentially arranged under the back side of the substrate.

2. The cell region structure of the IGBT chip according to claim 1, wherein: The cellular region structure further includes: A passivation layer is provided on the dielectric layer and the front metal layer, and is divided into a left passivation layer and a right passivation layer, with a lateral gap between the left passivation layer and the right passivation layer.

3. The cell region structure of the IGBT chip according to claim 1, wherein: The thickness of the dielectric layer ranges from 9000 to 12000 Å.

4. The cell region structure of the IGBT chip according to any one of claims 1 to 3, characterized in that: The dielectric layer is a double-layer structure of USG+BPSG.

5. The cell region structure of the IGBT chip according to claim 1, wherein: The Poly gate is based on a Busbar trace and is connected to the metal gate of the IGBT chip.

6. The cell region structure of the IGBT chip according to claim 1, wherein: The thickness of the front metal layer ranges from 8 to 12 μm; And / or, the thickness of the back metal layer is in the range of 1 to 2 μm.

7. The cell region structure of the IGBT chip according to claim 1, wherein: The buffer layer is an N-type doped layer.

8. An IGBT chip, characterized in that: It comprises a cellular region structure and a terminal region structure adapted to the cellular region structure; the cellular region structure is the cellular region structure of the IGBT chip according to any one of claims 1 to 7.

Images