Device for interconnection and packaging circuit

Abstract

The embodiment of the utility model discloses a device for interconnection and a packaging circuit. The interconnect device includes a first signal trace and a second signal trace. The first signal trace includes a first portion at a first layer of the substrate and a plurality of disk-shaped portions at a second layer of the substrate, the first portion being connected to the plurality of disk-shaped portions through conductive vias. The second signal trace includes a first portion at the third layer of the substrate and a plurality of disk-shaped portions at the second layer of the substrate, the first portion being connected to the plurality of disk-shaped portions through conductive vias. In some embodiments, there is crosstalk between the first signal trace and the second signal trace, and a mutual capacitance between the plurality of disk-shaped portions of the first signal trace and the plurality of disk-shaped portions of the second signal trace may increase a mutual capacitance between the first signal trace and the second signal trace, which will counteract the mutual inductance, reducing crosstalk between the first signal trace and the second signal trace.

Description

Technical Field

[0001] The present invention generally relates to the field of integrated circuits, and more particularly, to a device for interconnection and a packaged circuit. Background Art

[0002] In 2.5D and 3D packaging technologies, multiple integrated circuit dies are located in the same package. The integrated circuit dies are interconnected using a die-to-die (D2D) approach. D2D interconnection requires low latency, low power consumption, and high reliability. When signal lines transmit signals, they generate electric and magnetic fields. Crosstalk refers to the energy coupling from one signal line to an adjacent signal line due to the interaction of the electric and magnetic fields generated by the signal lines. As communication frequencies increase and the physical distance between signal lines decreases, crosstalk can negatively impact signal transmission. As interconnect bandwidth requirements and chip performance increase, D2D I / O frequency and signal line density also increase, limiting the performance of D2D interconnects. Utility Model Content

[0003] In view of this, embodiments of the present invention provide a device for interconnecting integrated circuit dies and a packaging circuit to reduce crosstalk between signal traces.

[0004] According to a first aspect of an embodiment of the present invention, a device for interconnection is provided. The device includes: a first signal trace and a second signal trace. The first signal trace includes a first portion located on a first layer of a substrate and multiple disc-shaped portions located on a second layer of the substrate, the first portion being connected to the multiple disc-shaped portions via a conductive via. The second signal trace includes a first portion located on a third layer of the substrate and multiple disc-shaped portions located on the second layer of the substrate, the first portion being connected to the multiple disc-shaped portions via a conductive via.

[0005] Optionally, the first portion of the first signal trace and the first portion of the second signal trace extend along a first direction, and the plurality of disk-shaped portions of the first signal trace and the plurality of disk-shaped portions of the second signal trace are alternately arranged in the first direction.

[0006] Optionally, the first portion of the first signal trace and the first portion of the second signal trace are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals.

[0007] Optionally, the plurality of disk-shaped portions of the first signal trace and the plurality of disk-shaped portions of the second signal trace increase mutual capacitance to offset the mutual inductance.

[0008] Optionally, the device comprises a plurality of first signal traces, the first portion of the first signal trace comprising a toothed portion; and / or the device comprises a plurality of second signal traces, the first portion of the second signal trace comprising a toothed portion.

[0009] Optionally, adjacent first signal traces are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals, and the toothed portions of adjacent first signal traces increase the mutual capacitance to offset the mutual inductance; and / or, adjacent second signal traces are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals, and the toothed portions of adjacent second signal traces increase the mutual capacitance to offset the mutual inductance.

[0010] Optionally, the first signal trace and the second signal trace comprise signal traces for a high-speed memory package.

[0011] According to a second aspect of an embodiment of the present utility model, a packaged circuit is provided, comprising: a substrate; a first integrated circuit die and a second integrated circuit die located on the substrate; and a first signal trace and a second signal trace connecting the first integrated circuit die and the second integrated circuit die. The first signal trace comprises a first portion located on a first layer of the substrate and a plurality of disc-shaped portions located on a second layer of the substrate, the first portion being connected to the plurality of disc-shaped portions via a conductive via. The second signal trace comprises a first portion located on a third layer of the substrate and a plurality of disc-shaped portions located on a second layer of the substrate, the first portion being connected to the plurality of disc-shaped portions via a conductive via.

[0012] Optionally, the first portion of the first signal trace and the first portion of the second signal trace extend along a first direction, and the plurality of disk-shaped portions of the first signal trace and the plurality of disk-shaped portions of the second signal trace are alternately arranged in the first direction.

[0013] Optionally, the first portion of the first signal trace and the first portion of the second signal trace are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals.

[0014] Optionally, the plurality of disk-shaped portions of the first signal trace and the plurality of disk-shaped portions of the first signal trace increase mutual capacitance to offset the mutual inductance.

[0015] Optionally, the packaged circuit includes a plurality of first signal traces, a first portion of the first signal traces including a toothed portion; and / or the packaged circuit includes a plurality of second signal traces, a first portion of the second signal traces including a toothed portion.

[0016] Optionally, adjacent first signal traces are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals, and the toothed portions of adjacent first signal traces increase the mutual capacitance to offset the mutual inductance; and / or, adjacent second signal traces are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals, and the toothed portions of adjacent second signal traces increase the mutual capacitance to offset the mutual inductance.

[0017] Optionally, the first integrated circuit die is a high-speed memory.

[0018] According to the interconnection device and packaged circuit of the embodiments of the present invention, the mutual capacitance between the multiple disk-shaped portions of the first signal trace and the multiple disk-shaped portions of the second signal trace can increase the mutual capacitance between the first signal trace and the second signal trace, which will offset the mutual inductance between the first signal trace and the second signal trace and reduce the crosstalk between the first signal trace and the second signal trace. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0020] Figure 1 1 is a top view of a packaged circuit according to an embodiment of the present invention;

[0021] Figure 2 is a cross-sectional view of a packaged circuit according to an embodiment of the present invention along a first direction;

[0022] Figure 3A is a partial cross-sectional view of an interconnection device of the related art along a first direction;

[0023] Figure 3B is a partial cross-sectional view of an interconnection device of the related art along the second direction;

[0024] Figure 4 is a partial cross-sectional view of the interconnection device according to an embodiment of the present utility model along a first direction;

[0025] Figure 5A is a partial cross-sectional view of an interconnection device according to an embodiment of the present invention along a second direction;

[0026] Figure 5B yes Figure 5A a top view of a second layer of a substrate of an interconnect device;

[0027] Figure 6A is a partial cross-sectional view of an interconnection device along a second direction according to another embodiment of the present invention;

[0028] Figure 6B yes Figure 6Aa top view of a second layer of a substrate of an interconnect device;

[0029] Figure 7 is a top view of a first portion of a plurality of first signal traces in one embodiment of the present invention;

[0030] Figure 8 is a top view of a first portion of a plurality of first signal traces in another embodiment of the present invention;

[0031] Figures 9A-9E are cross-sectional views of the interconnection device of the present invention at various stages of the manufacturing method;

[0032] Figure 10 The far-end crosstalk simulation method of the interconnection device of the present utility model is shown;

[0033] Figure 11 The far-end crosstalk simulation results of the interconnection device of the present utility model are shown;

[0034] Figure 12 It is a schematic diagram of a testing method of the interconnection device of the present utility model;

[0035] Figure 13 Shown Figure 12 Test results for the test method shown. DETAILED DESCRIPTION

[0036] The present application is described below based on the following embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without the description of these details. To avoid obscuring the essence of the present application, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0037] Furthermore, persons of ordinary skill in the art will appreciate that the figures provided herein are for illustration purposes only and are not necessarily drawn to scale.

[0038] Unless the context clearly requires otherwise, words like “include”, “comprising” and the like throughout this application should be interpreted as including rather than exclusive or exhaustive; that is, as meaning “including but not limited to”.

[0039] In the description of this application, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood to indicate or imply relative importance. In addition, in the description of this application, unless otherwise specified, "plurality" means two or more.

[0040] Figure 11 is a top view block diagram of an exemplary packaged circuit of the present invention. Figure 2 is a cross-sectional view of the packaged circuit along the first direction. The first direction is Figure 1 The AA direction in the second direction is Figure 1 The BB direction in FIG is perpendicular to the first direction and the second direction. It should be understood that the sizes of the components are not necessarily to scale. For the purpose of illustrating the features described, some components may be exaggerated or emphasized in size or position. Figure 1 and Figure 2 As shown, the packaged circuit includes: a first integrated circuit die 101 and a second integrated circuit die 103, a device for interconnection 105, a package substrate 107, and a circuit board 109. The packaged circuit also includes a protection frame (not shown), and the first integrated circuit die 101, the second integrated circuit die 103 and the interconnection device 105 are accommodated in a space defined by the protection frame.

[0041] The packaged circuit includes at least two integrated circuit dies, thereby achieving computing power stacking or heterogeneous integration. The first integrated circuit die 101 and the second integrated circuit die 103 are bare dies. The first integrated circuit die 101 and the second integrated circuit die 103 are, for example, logic chips, high-speed memories, etc. Logic chips are, for example, CPUs, GPUs, and TPUs. High-speed memories are, for example, high-bandwidth memories (HBM).

[0042] The first integrated circuit die 101 and the second integrated circuit die 103 are disposed on an interconnection device 105. The first integrated circuit die 101 and the second integrated circuit die 103 communicate with each other through the interconnection device 105 and are also connected to a package substrate 107 and a circuit board 109 through the interconnection device 105. The first integrated circuit die 101 and the second integrated circuit die 103 include D2D interface circuits and communicate according to one or more of the XSR protocol, the BoW protocol, the OpenHBI protocol, and the UCIe protocol.

[0043] The interconnection device 105 includes a substrate 106, solder balls 113 located on a first surface of the substrate 106, solder balls 117 located on a second surface of the substrate 106, and signal traces 111. The first surface and the second surface are opposite to each other. Solder balls 113 and 117 are, for example, C4 solder balls (C4 bumps) or C2 micro bumps (C2 micro bumps), but are not limited to these two types. The first integrated circuit die 101 and the second integrated circuit die 103 are connected to the interconnection device 105 through the corresponding solder balls 113. The signal traces 111 connect the solder balls 113 corresponding to the D2D interface circuit of the first integrated circuit die 101 with the solder balls 113 corresponding to the D2D interface circuit of the second integrated circuit die 103, thereby realizing the interconnection between the first integrated circuit die 101 and the second integrated circuit die 103.

[0044] Interconnect device 105 also includes signal traces 115. Signal traces 115 are used to connect solder balls 113 on the first surface of substrate 106 to solder balls 117 on the second surface of substrate 106. Signal traces 115 are, for example, plated through-holes. Substrate 106 and package substrate 107 are connected via solder balls 117. Package substrate 107 and circuit board 109 are connected via solder balls 120. Solder balls 120 are, for example, BGA solder balls. Solder balls 117 and 120 are connected via signal traces 119 in package substrate 107. This enables communication between first integrated circuit die 101 and second integrated circuit die 103 and other external circuits.

[0045] In some embodiments, the interconnection device 105 is formed by forming signal traces and solder balls on a silicon substrate, and the interconnection device 105 is also called a silicon interposer. The interconnection device 105 of the present invention is not limited to a silicon interposer, and can also be a silicon bridge.

[0046] The signal traces 111 are arranged on multiple layers of the substrate 106. The following description will be made by taking the arrangement of the signal traces 111 on two layers of the substrate 106 as an example. Figure 2 As shown, the signal trace 111 includes a first signal trace 1111 and a second signal trace 1112. The first signal trace 1111 includes a first portion located on the first layer of the substrate 106, and the first portion is connected to the corresponding solder ball 113 through a conductive via. The second signal trace 1112 includes a first portion located on the third layer of the substrate 106, and the first portion is connected to the corresponding solder ball 113 through a conductive via. The first portion of the first signal trace 1111 and the first portion of the second signal trace 1112 are connected along a first direction (i.e., Figure 1 The first portion of the first signal trace 1111 and the first portion of the second signal trace 1112 are located below the gap between the first integrated circuit die 101 and the second integrated circuit die 103.

[0047] As the interconnection bandwidth requirements and chip performance of integrated circuit dies increase, the number of signal traces 111 increases, the physical distance between the first signal trace 1111 and the second signal trace 1112 decreases, and the crosstalk between the first signal trace 1111 and the second signal trace 1112 becomes more serious.

[0048] Figure 3A is a partial cross-sectional view of an interconnection device in the related art along a first direction. Figure 3B1 is a partial cross-sectional view of an interconnection device of the related art along the second direction. One method of reducing crosstalk in the related art is to set a ground layer 151 between the first signal trace 1111 and the second signal trace 1112, and the first signal trace 1111 and the second signal trace 1112 are shielded by the ground layer 151. Figure 3A and 3B As shown, a dielectric material layer 152 is provided between the first layer where the first signal trace 1111 is located and the ground layer 151. A dielectric material layer 153 is provided between the third layer where the second signal trace 1112 is located and the ground layer 151. Ground layer 151 is a metal layer and is connected to the ground node VSS. Isolation and shielding using ground layer 151 not only increases the parasitic capacitance of the signal traces, causing increased signal loss and deteriorating electrical performance, but also, due to process and space limitations, insufficient VSS connections at different locations, resulting in poor crosstalk isolation and worsening crosstalk.

[0049] This utility model proposes a crosstalk solution that does not require a ground plane. Crosstalk refers to energy from one signal crossing into the electric or magnetic field (or both) of an adjacent signal line, thereby affecting the signal energy of the adjacent signal line. Crosstalk can have an electric component caused by the electric field, resulting in a capacitive crosstalk component. Crosstalk can also have a magnetic component caused by the magnetic field, resulting in an inductive crosstalk component. Far-end crosstalk (FEXT) can be expressed as the difference between capacitive crosstalk and inductive crosstalk and can be calculated using the following formula.

[0050]

[0051] Where a is the coupling coefficient, which is specific to a specific circuit. Cm is the mutual capacitance, Cs is the self-capacitance, Lm is the mutual inductance, and Ls is the self-inductance. In current 2.5D packaging, far-end crosstalk (FEXT) between signals is dominated by inductive coupling, meaning Lm / Ls > Cm / Cs. To reduce FEXT, the mutual capacitance Cm needs to be increased so that Cm / Cs ≈ Lm / Ls.

[0052] Figure 4 It is a partial cross-sectional view of the interconnection device of an embodiment of the present utility model along the first direction. Figure 4 It is a view looking into the interior of the interconnection device along the second direction. Figure 4 FIG. 1 shows a local area where the first signal trace 1111 and the second signal trace 1112 are located. Figure 4As shown, a first signal trace 1111 includes a first portion located on the first layer L1 of the substrate 106 and multiple disc-shaped portions 122 located on the second layer L2 of the substrate 106. The first portion is connected to the disc-shaped portions 122 via a conductive via 123. A second signal trace 1112 includes a first portion located on the third layer L3 of the substrate 106 and multiple disc-shaped portions 124 located on the second layer L2 of the substrate 106. The first portion is connected to the disc-shaped portions 124 via a conductive via 125. The second layer L2 is located between the first layer L1 and the third layer L3. A dielectric material layer 121 is provided between the first layer L1 and the second layer L2, and between the second layer L2 and the third layer L3. The shapes of the disc-shaped portions 122 and 124 are not limited and may be, for example, triangular, rectangular, diamond, circular, etc. The shapes of the disc-shaped portions 122 and 124 may be the same or different.

[0053] According to an embodiment of the present invention, first signal trace 1111 and second signal trace 1112 are used to implement D2D interconnection between first integrated circuit die 101 and second integrated circuit die 103. Signals are transmitted through first signal trace 1111 and first portion of second signal trace 1112. The first portion of the first signal trace and the first portion of the second signal trace are physically close, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals. The multiple disc-shaped portions 122 of the first signal trace 1111 and the multiple disc-shaped portions 124 of the second signal trace 1112 also have mutual capacitance, which increases the mutual capacitance of the first signal trace 1111 and the second signal trace 1112 to offset the mutual inductance. In other words, the disc-shaped portions 122 and 124 increase the capacitive coupling between the first signal trace 1111 and the second signal trace 1112, reducing far-end crosstalk.

[0054] It should be understood that the physical proximity described in the embodiments of the present invention means that the physical distance is less than or equal to a predetermined value, wherein the size of the predetermined value is determined according to actual needs and processes, and the embodiments of the present invention do not limit this.

[0055] The first portion of the first signal trace 1111 and the first portion of the second signal trace 1112 are made of metal. The disc-shaped portions 122 and 124 are also made of metal. The material of the disc-shaped portions 122 and 124 can be the same as or different from the material of the first portion.

[0056] Figure 5A It is a partial cross-sectional view of an interconnection device according to an embodiment of the present invention along the second direction. Figure 5A It is a view looking into the interior of the interconnection device along the first direction. Figure 5B yes Figure 5A In some embodiments, as shown in FIG. Figure 5Aand 5B As shown, the plurality of disc-shaped portions 122 of the first signal trace 1111 and the plurality of disc-shaped portions 124 of the second signal trace 1112 are aligned and alternately arranged in a first direction. The first direction is the signal transmission direction of the first signal trace 1111 and the second signal trace 1112, and is also the extending direction of the first portion.

[0057] Figure 6A It is a partial cross-sectional view of an interconnection device according to another embodiment of the present invention along the second direction. Figure 6A It is a view looking into the interior of the interconnection device along the first direction. Figure 6B yes Figure 6A In some embodiments, as shown in FIG. Figure 6A and 6B As shown, the plurality of disc-shaped portions 122 of the first signal trace 1111 and the plurality of disc-shaped portions 124 of the second signal trace 1112 are staggered in a first direction and are alternately arranged in the first direction. The staggered distance between the disc-shaped portions 122 of the first signal trace 1111 and the disc-shaped portions 124 of the second signal trace 1112 is S. The staggered disc-shaped portions 122 of the first signal trace 1111 and the disc-shaped portions 124 of the second signal trace 1112 means that the first portion of the first signal trace 1111 and the first portion of the second signal trace 1112 are staggered (as viewed from above).

[0058] Figure 7 FIG. 1 is a top view of a first portion of a plurality of first signal traces in one embodiment of the present invention. Figure 7 As shown, the first portions of the plurality of first signal traces are in the shape of bars and are parallel to each other.

[0059] As the interconnect bandwidth requirements and chip performance of integrated circuit dies increase, the physical spacing between first signal traces 1111 gradually decreases, and the crosstalk between first signal traces 1111 gradually increases. The present invention also provides a method for reducing crosstalk between first signal traces 1111. Figure 8 FIG. 1 is a top view of a first portion of a plurality of first signal traces in another embodiment of the present invention. Figure 8As shown, the first portion of the first signal trace 1111 includes a toothed portion 127. The toothed portion 127 is also located in the first layer L1, has the same material as the other positions of the first portion and is formed simultaneously in the process. Adjacent first signal traces 1111A and 1111B (or 1111B and 1111C) are physically close, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals. The toothed portions 127 of adjacent first signal traces 1111 increase the relative area between adjacent first signal traces 1111, thereby increasing the mutual capacitance between adjacent first signal traces 1111, thereby offsetting the mutual inductance and reducing far-end crosstalk. The shape of the toothed portion 127 is not limited and can be rectangular, triangular, semicircular, etc.

[0060] It is understood that the second signal trace 1112 may also be provided with a toothed portion according to the above solution. The toothed portion of the second signal trace 1112 is provided on the third layer L3.

[0061] In some embodiments, one of the first signal trace 1111 and the second signal trace 1112 is provided with a serration, while the other does not have a serration. For example, if the crosstalk between the first and second signal traces 1112 is not significant, the serration may not be provided.

[0062] Figures 9A-9E 1 is a cross-sectional view of the interconnection device 105 of the present invention at various stages of the manufacturing method. The interconnection device 105 can be formed by the following steps.

[0063] The first step, such as Figure 9A As shown, a first portion of a second signal trace 1112 is formed on a substrate 131, and a dielectric material layer 133 covers the first portion of the second signal trace 1112. It is understood that other functional layers may be present between the substrate 131 and the first portion of the second signal trace 1112. Dielectric material layer 133 may be, for example, a silicon oxide layer and / or a silicon nitride layer, and substrate 131 may be, for example, a silicon substrate. The first portion of the second signal trace 1112 may be formed by depositing metal and then patterning it.

[0064] The second step is Figure 9B As shown, conductive via 125 is formed in dielectric material layer 133, and disk-shaped portions 122 and 124 are formed on dielectric material layer 133. Disk-shaped portions 122 and 124 can be formed by depositing metal and then patterning. Conductive via 125 penetrates dielectric material layer 133 to electrically connect the first portion of second signal trace 1112 and disk-shaped portion 124.

[0065] The third step, such as Figure 9CAs shown, a dielectric material layer 135 is covered on the dielectric material layer 133 and the disc-shaped portions 122 and 124, and a conductive via 123 is formed in the dielectric material layer 135. The conductive via 123 penetrates the dielectric material layer 135 above the disc-shaped portion 122. The dielectric material layers 133 and 135 constitute Figure 4 , Figure 5A and Figure 6A The dielectric material layer 121 in the embodiment of the present invention is shown in FIG.

[0066] The fourth step is as follows Figure 9D As shown, the first portion of the first signal trace 1111 is formed on the dielectric material layer 121. The first portion of the first signal trace 1111 can be formed by depositing metal and then patterning. The patterning process can also simultaneously form Figure 8 Toothed portion 127 is shown.

[0067] Step 5: Figure 9E As shown, a dielectric material layer 137 is formed over the first portion of first signal trace 1111, a conductive via 141 is formed through dielectric material layer 137, and a conductive via 143 is formed through dielectric material layer 137 and dielectric material layer 121. Corresponding solder balls 113 are disposed above conductive vias 141 and 143. Conductive via 141 connects to the first portion of first signal trace 1111, and conductive via 143 connects to the first portion of second signal trace 1112. Conductive via 143 can be formed by the following steps: forming a portion that passes through dielectric material layer 121, then depositing dielectric material layer 137, and then forming a portion that passes through dielectric material layer 137.

[0068] In summary, the manufacturing method of the interconnection device according to the embodiment of the present invention is simple and can be realized under current process conditions without requiring additional process improvement solutions.

[0069] Figure 10 The far-end crosstalk simulation method of the interconnection device of the present invention is shown. Figure 11 Figure 2 shows the far-end crosstalk simulation results of the interconnection device of the present invention. Figure 10 As shown, when the signal sig1 is input at the left end of the first signal trace 1111, the signal transmission on the first signal trace 1111 affects the second signal trace 1112, wherein the impact on the left end of the second signal trace 1112 is called near-end crosstalk, and the impact on the right end of the second signal trace 1112 is called far-end crosstalk. In the simulation, when the signal sig1 is input at the left end of the first signal trace 1111, the detection signal sig2 at the right end of the second signal trace 1112 is simulated, and the far-end crosstalk generated by the first signal trace 1111 on the second signal trace 1112 is simulated. Figure 11 In the figure, the black line is the Figure 3A and 3BThe simulation results of the crosstalk reduction scheme are shown in red. Figure 4 The simulation results of the crosstalk reduction scheme are shown in Figure 2. Figure 11 In the figure, the horizontal axis represents the frequency of the input signal, and the vertical axis represents the far-end crosstalk (in dB). Far-end crosstalk Y = b*lg(sig2 / sig1). For example, if the input signal sig1 is 1V, the detection signal is 0.01V, b = 20, and the far-end crosstalk is -40dB. Figure 11 As shown, the solution of the present invention reduces far-end crosstalk.

[0070] Figure 12 It is a schematic diagram of a testing method of the interconnection device of the present utility model. Figure 13 Shown Figure 12 The test results of the test method shown are as follows. Figure 12 As shown, a signal IN1 is input at one end of the first signal trace 1111, a signal IN2 is input at one end of the second signal trace 1112, a signal OUT1 is detected at the other end of the first signal trace 1111, and a signal OUT2 is detected at the other end of the second signal trace 1112. That is, Figure 12 It is an eye diagram test. Eye diagram analysis is widely used in high-speed transmission interfaces. By superimposing signals on each other in a fixed period, the effects of noise and inter-symbol crosstalk can be analyzed. Eye diagrams are an important tool for signal integrity analysis in high-speed interconnect systems. The larger the eye opening, the smaller the inter-symbol interference. Conversely, the smaller the eye opening, the greater the inter-symbol crosstalk. Figure 13 In Figure A, Figure 3A and 3B The eye diagram of the crosstalk reduction solution is shown in Figure B. Figure 4 The eye diagram of the crosstalk reduction solution. Figure 13 As shown, the eye opening degree and line width of Figure B are better than those of Figure A, indicating that the solution of the present invention reduces far-end crosstalk.

[0071] The foregoing is merely a preferred embodiment of the present application and is not intended to limit the present application. Persons skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application are intended to be within the scope of protection of the present application.

Claims

1. An apparatus for interconnection, comprising: a first signal trace, the first signal trace comprising a first portion located on a first layer of a substrate and a plurality of disk-shaped portions located on a second layer of the substrate, the first portion being connected to the plurality of disk-shaped portions via a conductive via; as well as The second signal trace includes a first portion located on the third layer of the substrate and a plurality of disk-shaped portions located on the second layer of the substrate, wherein the first portion is connected to the plurality of disk-shaped portions through a conductive via.

2. The device according to claim 1, wherein The first portion of the first signal trace and the first portion of the second signal trace extend along a first direction, and the plurality of plate-shaped portions of the first signal trace and the plurality of plate-shaped portions of the second signal trace are alternately arranged in the first direction.

3. The device according to claim 1, wherein The first portion of the first signal trace and the first portion of the second signal trace are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals.

4. The device according to claim 3, wherein The plurality of plate-shaped portions of the first signal trace and the plurality of plate-shaped portions of the second signal trace increase mutual capacitance to cancel the mutual inductance.

5. The device according to claim 1, wherein The device includes a plurality of said first signal traces, a first portion of said first signal traces including a toothed portion, And / or, the device comprises a plurality of the second signal traces, the first portion of the second signal traces comprising a toothed portion.

6. The device according to claim 5, wherein Adjacent first signal traces are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals, and the toothed portions of the adjacent first signal traces increase mutual capacitance to offset the mutual inductance. and / or, Adjacent second signal traces are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals. The toothed portions of the adjacent second signal traces increase mutual capacitance to offset the mutual inductance.

7. The device according to any one of claims 1 to 6, wherein: The first signal trace and the second signal trace comprise signal traces for a high-speed memory package.

8. A packaged circuit comprising: substrate; a first integrated circuit die and a second integrated circuit die located on the substrate; as well as a first signal trace and a second signal trace connecting the first integrated circuit die and the second integrated circuit die, The first signal trace includes a first portion located on a first layer of the substrate and a plurality of disk-shaped portions located on a second layer of the substrate, the first portion being connected to the plurality of disk-shaped portions via a conductive through-hole. The second signal trace includes a first portion located on the third layer of the substrate and a plurality of pad-shaped portions located on the second layer of the substrate, wherein the first portion is connected to the plurality of pad-shaped portions through a conductive via.

9. The packaged circuit according to claim 8, wherein: The first portion of the first signal trace and the first portion of the second signal trace extend along a first direction, and the plurality of plate-shaped portions of the first signal trace and the plurality of plate-shaped portions of the second signal trace are alternately arranged in the first direction.

10. The packaged circuit according to claim 8, wherein: The first portion of the first signal trace and the first portion of the second signal trace are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals.

11. The packaged circuit according to claim 10, wherein: The plurality of plate-shaped portions of the first signal trace and the plurality of plate-shaped portions of the first signal trace increase mutual capacitance to cancel the mutual inductance.

12. The packaged circuit according to claim 8, wherein: The packaged circuit includes a plurality of the first signal traces, the first portion of the first signal traces including a tooth portion, And / or, the packaged circuit includes a plurality of the second signal traces, and the first portion of the second signal traces includes a tooth-shaped portion.

13. The packaged circuit according to claim 12, wherein: Adjacent first signal traces are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals, and the toothed portions of the adjacent first signal traces increase mutual capacitance to offset the mutual inductance. and / or, Adjacent second signal traces are physically close to each other, thereby inducing magnetic coupling and causing mutual inductance when transmitting signals. The toothed portions of the adjacent second signal traces increase mutual capacitance to offset the mutual inductance.

14. The packaged circuit according to any one of claims 8 to 13, wherein: The first integrated circuit die is a high-speed memory.

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