Substrate for packaging laser chip
By designing the laser chip packaging substrate with substrate layer, formation metal layer, dielectric isolation layer and transmission line structure, the problems of through-hole resistance changes and process complexity in the packaging substrate process are solved, and the stable transmission of high-frequency signals and cost reduction are achieved.
Patent Information
- Application Number
- CN202421799340.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-26
- Publication Date
- 2025-09-02
- Estimated Expiration
- 2034-07-26
AI Technical Summary
In the existing laser chip packaging technology, there are contradictions in the process of the packaging substrate, especially the changes in through-hole resistance and process complexity problems during high-frequency signal transmission, which affect the signal source characteristics and cost.
The design of substrate layer, formation metal layer, dielectric isolation layer and transmission line structure is adopted. The area of the dielectric isolation layer is smaller than that of the formation metal layer. The transmission line ground port is set on the exposed formation metal layer to avoid through holes, simplify the process and improve transmission performance.
It realizes stable transmission of high-frequency signals, avoids changes in through-hole resistance, simplifies the process flow, reduces costs and improves the performance stability of the packaging substrate.
Smart Images
Figure CN223297204U_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of optoelectronic devices, and specifically relates to a substrate for laser chip packaging. Background Art
[0002] In fiber-optic communication technology, semiconductor lasers are primarily used as signal sources. With the continuous improvement of laser chip fabrication technology, not only has the cost of laser chips been significantly reduced, but the modulation frequency of a single laser chip has also reached tens of GHz or even dozens of GHz. Currently, the key factor restricting signal source performance and cost lies primarily in packaging technology. During the packaging process, the packaging substrate must provide high-frequency signals to the laser. To ensure high-frequency transmission and signal coupling, multilayer ceramics or multilayer high-resistance silicon are generally used to form microstrip lines or coplanar microwave waveguide structures. If multilayer ceramics are used, the sintering temperature must reach above 1000°C, which limits slurry deformation and limits sintering to small dimensions, resulting in relatively low production capacity. If single-layer laser drilling is used, copper plating is required to fill the holes, along with copper grinding and polishing, making the process more complex. High-resistance silicon bonding can achieve high-frequency transmission similar to ceramics, but it requires TSV (Through Silicon Via) fabrication, electroplating, and bonding processes. However, these processes conflict with the processes of integrating components such as capacitors and resistors with silicon. If the capacitors are integrated first, they can be easily damaged during the TSV and electroplating processes.
[0003] Therefore, it is urgent to propose a substrate for laser chip packaging that can avoid conflicts between processes. Utility Model Content
[0004] In view of the above-mentioned shortcomings or deficiencies of the prior art, the technical problem to be solved by the present application is to provide a substrate for laser chip packaging.
[0005] To solve the above technical problems, this application is implemented through the following technical solutions:
[0006] The present application proposes a substrate for laser chip packaging, which at least includes: a substrate layer structure, a ground metal layer structure, a dielectric isolation layer structure and a transmission line structure, wherein the ground metal layer structure covers part of the substrate layer structure, the dielectric isolation layer structure is arranged on the ground metal layer structure, and the projection area of the dielectric isolation layer structure is smaller than the projection area of the ground metal layer structure, the transmission line structure is arranged on the dielectric isolation layer structure, and the projection area of the transmission line structure is smaller than the projection area of the dielectric isolation layer structure, and the ground port of the transmission line structure is arranged on the ground metal layer structure.
[0007] Optionally, the above-mentioned substrate for laser chip packaging further includes: a gold-tin pad, which is connected to the ground metal layer structure.
[0008] Optionally, in the above-mentioned substrate for laser chip packaging, the substrate layer structure includes: a ceramic substrate or a silicon substrate.
[0009] Optionally, in the above-mentioned substrate for laser chip packaging, the material of the ground metal layer structure includes at least one of titanium, gold, aluminum, copper, silver, and platinum.
[0010] Optionally, in the above-mentioned substrate for laser chip packaging, the dielectric constant of the dielectric isolation layer structure is less than 7.
[0011] Optionally, the above-mentioned substrate for laser chip packaging further includes: a capacitor layer structure, wherein the capacitor layer structure is arranged between the substrate layer structure and the ground metal layer structure.
[0012] Optionally, in the above-mentioned substrate for laser chip packaging, the ground metal layer structure, the capacitor layer structure and the metal layer structure are connected through a first through hole.
[0013] Optionally, in the above-mentioned substrate for laser chip packaging, the metal layer of the capacitor layer structure is connected to the surface metal through a second through hole.
[0014] Optionally, in the above-mentioned substrate for laser chip packaging, the thickness of the substrate layer structure is 100 to 500 μm; and / or the thickness of the stratum metal layer structure is 0.1 to 2 μm; and / or the thickness of the dielectric isolation layer structure is 5 to 50 μm; and / or the thickness of the transmission line structure is 0.1 to 2 μm.
[0015] Compared with the existing technology, this application has the following technical effects:
[0016] The present application avoids the situation in the prior art where the transmission performance of conventional microstrip lines deteriorates dramatically when the resistance of the through-hole at a certain ground port changes or becomes non-conductive. The ground metal layer structure of the present application shields the substrate layer structure. By setting the projected area of the dielectric isolation layer structure to be smaller than the projected area of the ground metal layer structure, the ground metal layer structure is exposed, and the ground port of the transmission line structure can be set on the exposed ground metal layer structure, thereby avoiding the need for setting a through-hole and avoiding special requirements for the material of the substrate layer structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings:
[0018] Figure 1 : The main view of Example 1 and Example 2 of the present application;
[0019] Figure 2 :like Figure 1 A-A' cross-sectional view of the structure shown;
[0020] Figure 3 : S21 curves of different thicknesses of silicon dioxide in the substrate layer structure in Example 1 of the present application;
[0021] Figure 4 : S11 curves of different thicknesses of silicon dioxide in the substrate layer structure in Example 1 of the present application;
[0022] Figure 5 : A front view of Example 3 of the present application;
[0023] Figure 6 :like Figure 5 A-A' cross-sectional view of the structure shown;
[0024] In the figure: substrate layer structure 1, ground metal layer structure 2, dielectric isolation layer structure 3, transmission line structure 4, gold-tin pad 5, capacitor layer structure 6, first layer structure 6a, second layer structure 6b, third layer structure 6c, first through hole 7, second through hole 8, and ground port 9. DETAILED DESCRIPTION
[0025] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0026] The present application proposes a substrate for laser chip packaging, which is suitable for a microstrip transmission line structure of high-speed laser packaging and can support signal transmission above 70GHz. The substrate comprises at least: a substrate layer structure 1, a ground metal layer structure 2, a dielectric isolation layer structure 3 and a transmission line structure 4. The ground metal layer structure 2 covers part of the substrate layer structure 1, the dielectric isolation layer structure 3 is arranged on the ground metal layer structure 2, and the projection area of the dielectric isolation layer structure 3 is smaller than the projection area of the ground metal layer structure 2, the transmission line structure 4 is arranged on the dielectric isolation layer structure 3, and the projection area of the transmission line structure 4 is smaller than the projection area of the dielectric isolation layer structure 3, and the ground port 9 of the transmission line structure 4 is arranged on the ground metal layer structure 2.
[0027] The ground metal layer structure 2 is a ground layer in the microstrip transmission line.
[0028] In conventional microstrip lines in the prior art, if the resistance of the through-hole at a ground port changes or becomes non-conductive, the transmission performance deteriorates dramatically. The structure proposed in this application avoids this problem. The ground metal layer structure 2 actually shields the substrate layer structure 1, which eliminates any special requirements for the material of the substrate layer structure 1. Compared with the prior art, this application avoids the through-hole electroplating process when the substrate layer structure 1 uses a silicon substrate or a ceramic substrate, and further avoids the high-temperature sintering process of ceramics. Moreover, after eliminating the through-hole, the structure is simple, the impedance is stable, and the performance stability is better than that of through-hole products.
[0029] Optionally, the substrate for laser chip packaging further comprises: a gold-tin pad 5, which is connected to the ground metal layer structure 2. The above arrangement facilitates mounting of the gold-tin pad 5 and the laser.
[0030] Optionally, the substrate layer structure 1 includes: a ceramic substrate or a silicon substrate. When there is a need for integrated capacitance, a silicon substrate is preferred.
[0031] Optionally, the thickness of the substrate layer structure 1 is 100-500 μm to meet the mechanical strength requirements of the device and the optical path requirements of the laser.
[0032] Optionally, the material of the formation metal layer structure 2 includes at least one of titanium, gold, aluminum, copper, silver, and platinum to ensure the performance of the formation metal layer structure 2.
[0033] Optionally, the thickness of the ground metal layer structure 2 is 0.1-2 μm to adapt to the skin effect and economic effect of high-frequency signals.
[0034] Optionally, the dielectric constant of the dielectric isolation layer structure 3 is less than 7. Specifically, considering the influence of parasitic capacitance on transmission characteristics, the material with a dielectric constant less than 7 is preferably used to reduce parasitic capacitance, such as silicon dioxide, silicon nitride, polyimide, epoxy resin, etc.
[0035] Optionally, the thickness of the dielectric isolation layer structure 3 is 5 to 50 μm, which is specifically optimized according to classical electromagnetic transmission line theory and actual transmission line index requirements.
[0036] Specifically, the dielectric isolation layer structure 3 is graphically distributed according to the layout requirements of the transmission line structure 4 .
[0037] Optionally, the material of the transmission line structure 4 includes at least one of titanium, gold, aluminum, copper, silver, and platinum to ensure the performance of the transmission line structure 4 .
[0038] Optionally, the transmission line structure 4 has a thickness of 0.1-2 μm to accommodate direct current resistance and skin effect.
[0039] Example 1
[0040] like Figure 1 and Figure 2 As shown in one embodiment of the present application, the substrate layer structure 1 is constructed from a silicon wafer. First, 2000 angstroms of silicon dioxide are grown. A 1-micron-thick aluminum layer is then deposited as the base metal layer structure 2. This aluminum layer serves as the microstrip line base and is patterned using photolithography. A 20-micron-thick silicon dioxide layer is deposited on the aluminum layer using chemical vapor deposition to form the dielectric isolation layer structure 3. Photolithography is then used to etch away the structure, leaving only the portion covered by the transmission line structure 4. The projected width of the dielectric isolation layer structure 3 is 10 microns wider than the projected width of the transmission line structure 4.
[0041] Then, a gold layer with a thickness of 1 μm is deposited on top of the dielectric isolation layer structure 3 using photolithography and lift-off processes to form the transmission line structure 4. To improve device reliability, the exposed ground metal layer structure 2 is covered with the transmission line structure 4 during the deposition of the transmission line structure 4.
[0042] When dielectric isolation layer structure 3 is corroded, it often forms a 5-10 degree inclination. During the deposition of transmission line structure 4, the inclination is also covered with a gold layer. Furthermore, the gold layer on the inclination is integrally connected to the metal portion of ground metal layer structure 2, forming an electrical interconnection.
[0043] The subsequent step is to deposit a gold-tin pad 5 and manufacture a thin film resistor as required, and the gold-tin pad 5 is connected to the ground metal layer structure 2 .
[0044] This embodiment uses the classical electromagnetic transmission line theory to calculate the results. Figure 3 and Figure 4 When the transmission line structure 4 is 1.5 mm long and 50 μm wide, and the dielectric isolation layer structure 3 is 15 to 35 μm thick, the transmission characteristics all meet a -3 dB bandwidth greater than 70 GHz. However, considering the S11 characteristic, which is generally required to be less than -10 dB, a silicon dioxide thickness of 20 μm is selected in this embodiment.
[0045] Example 2
[0046] like Figure 1 and Figure 2As shown, aluminum nitride ceramic is used as the substrate layer structure 1 with a thickness of 450μm. A 3μm ground metal layer structure 2 is made on the ceramic surface. The ground metal layer structure 2 uses an aluminum layer, which is the ground layer of the microstrip line. The pattern is formed by photolithography. A 30μm dielectric isolation layer structure 3 is deposited on the ground metal layer structure 2 by chemical vapor deposition. The dielectric isolation layer structure 3 uses silicon dioxide. Only part of the transmission line structure 4 is retained by photolithography. The width of the dielectric isolation layer structure 3 is 10μm wider than the transmission line. Conventional aluminum nitride cannot directly grow silicon dioxide due to stress problems. The present application can grow silicon dioxide because it has a 3μm ground metal layer structure 2 as a stress buffer.
[0047] Then, using photolithography and lift-off processes, a gold layer is deposited on top of the dielectric isolation layer structure 3 to form a transmission line structure 4 with a thickness of 1 μm. To improve device reliability, the exposed ground metal layer structure 2 is partially covered with the transmission line structure 4 during the deposition of the transmission line structure 4.
[0048] When dielectric isolation layer structure 3 is corroded, it often forms a 5-10 degree inclination. During the deposition of transmission line structure 4, the inclination is also covered with a gold layer. Furthermore, the gold layer on the inclination is integrally connected to the metal portion of ground metal layer structure 2, forming an electrical interconnection.
[0049] The subsequent step is to deposit a gold-tin pad 5 and manufacture a thin film resistor as required, and the gold-tin pad 5 is connected to the ground metal layer structure 2 .
[0050] Because the ground metal layer structure 2 is a ground layer for high-frequency signals, it shields the substrate layer structure 1. Under the structure of this embodiment, the calculation method and results of optimizing the microstrip line are consistent with those of the first embodiment.
[0051] Example 3
[0052] This embodiment is for explaining how to set up the capacitor layer structure 6 in the present application.
[0053] like Figure 5 and Figure 6 As shown, compared with embodiment 1, a capacitor layer structure 6 is further provided between the substrate layer structure 1 and the ground metal layer structure 2 in this embodiment to meet user needs and realize different functions by setting capacitors.
[0054] The capacitor layer structure 6 includes a three-layer structure, wherein the first layer structure 6 a is connected to the substrate layer structure 1 , and the third layer structure 6 c is connected to the ground metal layer structure 2 .
[0055] The ground metal layer structure 2 , the capacitor layer structure 6 and the metal layer structure are connected via a first through hole 7 .
[0056] The metal layer of the capacitor layer structure 6 is connected to the surface metal electrode through the second through hole 8 .
[0057] In this embodiment, the first layer structure 6a is formed by a silicon nitride layer, the second layer structure 6b is formed by a capacitor P-pole metal layer, and the third layer structure 6c is formed by an isolation silicon dioxide layer. The silicon nitride layer is connected to the substrate layer structure 1, and the isolation silicon dioxide layer is connected to the ground metal layer structure 2.
[0058] A low-resistance silicon wafer with a resistance of 0.01Ω.cm and a thickness of 250μm is used as the substrate layer structure 1. A 500-angstrom silicon nitride layer is deposited on the wafer surface. A 1μm-thick capacitor P-pole metal layer is formed on the silicon nitride layer. The capacitor P-pole metal layer is made of aluminum. The low-resistance silicon wafer serves as the N-electrode of the entire device, and the capacitor P-pole metal layer serves as the capacitor's P-pole. A 2000-angstrom silicon dioxide insulating layer is grown on the capacitor P-pole metal layer to serve as an isolation silicon dioxide layer. The silicon nitride layer, the capacitor P-pole metal layer, and the isolation silicon dioxide layer are all patterned using photolithography, so that the capacitor's N-pole and P-pole are electrically connected to the surface metal electrodes through through-holes. A 1μm-thick aluminum layer is deposited on the isolation silicon dioxide layer. This aluminum layer serves as the ground metal layer structure 2, the bottom metal of the microstrip line. This metal layer contacts the silicon substrate through a first through-hole 7, serving as the capacitor's N-pole.
[0059] Because deep hole etching and electroplating processes are avoided, this embodiment first integrates the capacitors and then completes the transmission line structure 4. Specifically, the configuration of the transmission line structure 4 is consistent with that of Example 1. Specifically for silicon substrates, this embodiment enables high-frequency transmission, such as signal transmission above 70 GHz, on the silicon substrate, resulting in a single-layer high-speed silicon substrate with integrated capacitors.
[0060] In the description of this application, unless otherwise expressly specified or limited, the terms "connected," "connect," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and can refer to internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.
[0061] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.
[0062] In the description of this embodiment, the terms "upper," "lower," "left," "right," and other orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely for ease of description and simplified operation. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used solely for descriptive purposes and have no special meanings.
[0063] The above embodiments are intended only to illustrate the technical solutions of the present application and are not intended to limit the present application. The present application is described in detail with reference to the preferred embodiments. It should be understood by those skilled in the art that the technical solutions of the present application may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application and should be included within the scope of the claims of the present application.
Claims
1. A substrate for laser chip packaging, characterized in that: At least: A substrate layer structure, a ground metal layer structure, a dielectric isolation layer structure and a transmission line structure, wherein the ground metal layer structure covers part of the substrate layer structure, the dielectric isolation layer structure is arranged on the ground metal layer structure, and the projection area of the dielectric isolation layer structure is smaller than the projection area of the ground metal layer structure, the transmission line structure is arranged on the dielectric isolation layer structure, and the projection area of the transmission line structure is smaller than the projection area of the dielectric isolation layer structure, and the ground port of the transmission line structure is arranged on the ground metal layer structure.
2. The substrate for laser chip packaging according to claim 1, characterized in that: Also includes: A gold-tin pad is connected to the ground metal layer structure.
3. The substrate for laser chip packaging according to claim 1 or 2, characterized in that: The substrate layer structure includes: a ceramic substrate or a silicon substrate.
4. The substrate for laser chip packaging according to claim 1 or 2, characterized in that: The dielectric constant of the dielectric isolation layer structure is less than 7.
5. The substrate for laser chip packaging according to claim 1 or 2, characterized in that: Also includes: A capacitor layer structure is provided between the substrate layer structure and the ground metal layer structure.
6. The substrate for laser chip packaging according to claim 5, characterized in that: The ground metal layer structure, the capacitor layer structure and the metal layer structure are connected through a first through hole.
7. The substrate for laser chip packaging according to claim 5, characterized in that: The metal layer of the capacitor layer structure is connected to the surface metal through the second through hole.
8. The substrate for laser chip packaging according to claim 1 or 2, characterized in that: The thickness of the substrate layer structure is 100 to 500 μm; and / or the thickness of the stratum metal layer structure is 0.1 to 2 μm; and / or the thickness of the dielectric isolation layer structure is 5 to 50 μm; and / or the thickness of the transmission line structure is 0.1 to 2 μm.