SiC device capable of improving protection performance

Abstract

The utility model discloses a SiC device for improving protection performance, and relates to the technical field of semiconductors. A first groove and a second groove are designed in the device, a P-shield region which is deeper in junction depth and narrower than the first groove in width is formed on the bottom surface of the second groove through injection, and the design aims that a depletion layer generated by the narrower P-shield region and a SiC Drift layer does not expand excessively, so that the conduction performance of the device is not influenced, and the conduction performance of the device is improved. And the P-shield region with deeper junction depth can also ensure that the generated depletion layer can wrap the corner at the bottom of the trench, thereby realizing protection of the trench gate oxide layer. And meanwhile, ohmic contact is prepared on the top surface of the P-shield region to connect a source electrode, so that grounding processing of the P-shield region is realized, and the protection capability of the P-shield region is further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to SiC devices with improved protection performance. Background Art

[0002] Si-based devices have long been the dominant form of voltage-controlled switching devices. In the low- and medium-voltage segments, Si MOSFETs are popular due to their excellent switching performance. However, in the medium- and high-voltage segments, Si IGBTs (Insulated Gate Bipolar Transistor) devices are more advantageous, as Si MOSFETs struggle to achieve a compromise between high voltage and low conduction losses. However, their significant drawback is their poor switching performance, with switching frequencies typically below 60kHz. However, with the continuous development of society, new energy vehicles, clean energy, and industrial power supplies are all moving towards high voltage and high power, placing increasing demands on system efficiency. However, due to the physical performance limitations of their materials, Si MOSFETs and Si IGBTs have struggled to achieve higher efficiencies. Consequently, third-generation wide-bandgap semiconductor power devices, such as SiC MOSFETs, have gained popularity. They offer superior physical properties and combine the conduction and switching characteristics of Si MOSFETs and Si IGBTs.

[0003] Trench-gate SiC MOSFETs, due to their smaller source cell structure, can achieve smaller chip sizes at the same power level, achieving advantages in switching performance and product cost. Many chip manufacturers are also considering trench gate structures as the future development direction of SiC MOSFET products. However, due to the electric field concentration problem at the bottom corner of the trench and the quality issues of the gate oxide layer grown by direct thermal oxidation, trench-gate SiC MOSFETs are prone to breakdown failure at the gate oxide layer at the bottom corner of the trench during long-term use. This is unacceptable for increasingly stringent operating conditions. Therefore, how to better protect the trench gate oxide layer during the long-term use of trench-gate SiC MOSFETs is essential for their safe and stable operation. Utility Model Content

[0004] In response to the above problems, the present invention provides a trench gate oxide layer for protecting the device, thereby improving the stability of the device and extending the service life of the SiC device with enhanced protection performance.

[0005] The practical technical solution is:

[0006] A SiC device with enhanced protection performance includes a SiC sublayer, a SiC drift layer, a P-body region, an NP region, an ohmic contact alloy layer, and a front electrode metal layer arranged sequentially from bottom to top;

[0007] A pair of first trenches extending downward from the top surface of the NP region are provided in the SiC Drift layer; a second trench extending downward is provided on the bottom surface of the first trench;

[0008] A P-shield region extending downward is provided at the bottom of the second trench;

[0009] A gate oxide layer is provided in the first trench, extending downward along the sidewall of the first trench, passing through the sidewall of the second trench and connected to the P-shield region;

[0010] A Poly layer is provided on the sidewall of the gate oxide layer in the first trench;

[0011] A horizontally extending isolation dielectric layer is provided on the top surface of the NP region. The isolation dielectric layer extends downward in the first trench after passing through a gate oxide layer and a Poly layer, and is connected to the P-shield region.

[0012] The ohmic contact alloy layer is located on the side of the isolation dielectric layer and is formed on the top surface of the NP region and the top surface of the P-shield region respectively.

[0013] Specifically, the bottom surface of the front electrode metal layer is connected to the ohmic contact alloy layer and the isolation dielectric layer respectively.

[0014] The depth between the bottom surface of the P-body region and the top surface of the SiC Drift layer is 0.6um-2um.

[0015] Specifically, the depth between the bottom surface of the NP region and the top surface of the SiC Drift layer is 0.3 μm-1.5 μm.

[0016] Specifically, the depth between the bottom surface of the first trench and the top surface of the SiC Drift layer is 1 um-3 um.

[0017] Specifically, the depth between the bottom surface of the second groove and the bottom surface of the first groove is 0.4um-0.8um.

[0018] This utility model addresses the issue of safe and stable use of the trench gate oxide layer of trench gate SiC MOSFETs. A first and second trench design is adopted in the device. By implanting a P-shield region with a deeper junction depth and a narrower width than the first trench, it is formed at the bottom surface of the second trench. This design aims to prevent the depletion layer generated by the narrower P-shield region and the SiC Drift layer from expanding too much, thereby affecting the device's conduction performance. The deeper junction depth of the P-shield region ensures that the generated depletion layer can wrap around the bottom corner of the trench, thereby protecting the trench gate oxide layer. At the same time, this utility model also prepares an ohmic contact on the top surface of the P-shield region to connect to the source electrode, achieving grounding of the P-shield region and further improving its protection capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the practical trench gate SiC MOSFET;

[0020] Figure 2 It is a structural diagram of step S100 of this practical application;

[0021] Figure 3 It is a structural diagram of step S200 of this practical application;

[0022] Figure 4 It is a structural diagram of step S300 of this practical application;

[0023] Figure 5 It is a structural diagram of step S400 of this practical application;

[0024] Figure 6 It is a structural diagram of step S500 of this practical application;

[0025] Figure 7 It is a structural diagram of step S600 of this practical application;

[0026] Figure 8 It is a structural diagram of step S700 of this practical application;

[0027] Figure 9 It is a structural diagram of step S800 of this practical application;

[0028] Figure 10 It is a structural diagram of step S900 of this practical application;

[0029] Figure 11 It is a structural diagram of step S1000 of this practical application;

[0030] Figure 12 It is a structural diagram of step S1100 of this practical application;

[0031] In the figure, 1 is the SiC Sub layer, 2 is the SiC Drift layer, 3 is the P-body region, 4 is the NP region, 5 is the first trench, 6 is the second trench, 7 is the P-shield region, 8 is the gate oxide layer, 9 is the Poly layer, 10 is the isolation dielectric layer, 11 is the ohmic contact alloy layer, and 12 is the front electrode metal layer. DETAILED DESCRIPTION

[0032] The present invention is described in detail below with reference to specific practical cases. Examples of the embodiments are shown in the accompanying drawings. The schematic implementation of the present invention and its description are only used to explain the present invention and are not intended to limit the present invention.

[0033] In the description of this utility, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely for the convenience of describing this utility and to simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting this utility. In the description of this utility, unless otherwise specified, "plurality" means two or more.

[0034] In the description of this utility, it should be noted that, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this utility based on the specific circumstances.

[0035] Improving the protection performance of SiC devices includes the following steps:

[0036] S100, forming a SiC Drift layer 2 on the top surface of the SiC Sub layer 1 by epitaxial deposition;

[0037] The doping concentration of the SiC Sub layer 1 in step S100 is 1E19-3E19cm -2 , the doping concentration of SiC Drift layer 2 is 1E15-5E16cm -2 .

[0038] S200 , forming a P-body region 3 on the top surface of the SiC Drift layer 2 by Al ion implantation;

[0039] The depth of the bottom surface of the P-body region 3 from the top surface of the SiC Drift layer (2) in step S200 is 0.6um-2um, and the doping concentration is 1E17-3E18cm -2 .

[0040] S300 , forming an NP region 4 on the top surface of the P-body region 3 by N ion implantation;

[0041] The depth of the bottom surface of the NP region 4 from the top surface of the SiC Drift layer (2) in step S300 is 0.3um-1.5um, and the doping concentration is 1E18-1E19cm -2 .

[0042] S400 , etching downwards to form a first trench 5 on the top surface of the NP region 4 ;

[0043] In step S400 , the depth between the bottom surface of the first trench 5 and the top surface of the SiC Drift layer ( 2 ) is 1 μm to 3 μm.

[0044] S500, forming a second trench 6 on the bottom surface of the first trench 5 by etching downwards;

[0045] In step S500, the depth of the bottom surface of the second groove 6 from the bottom surface of the first groove (5) is 0.4um-0.8um, and the left and right ends are 0.2um-0.5um away from the two sides of the first groove 5.

[0046] S600 , forming a P-shield region 7 on the bottom surface of the second trench 6 by Al ion implantation, and then performing high-temperature ion annealing to activate the implanted regions of the P-body region 3 , the NP region 4 and the P-shield region 7 ;

[0047] In step S600, the depth of the bottom surface of the P-shield region 7 from the bottom surface of the second trench 6 is 0.3um-0.8um, and the doping concentration is 5E18-1E19cm -2 .

[0048] S700 , forming a gate oxide layer 8 on the sidewalls of the first trench 5 and the second trench 6 by high-temperature dry oxygen oxidation;

[0049] The thickness of the gate oxide layer 8 in step S700 is 30 nm to 100 nm.

[0050] S800, forming a Poly layer 9 on the surface of the gate oxide layer 8 by polysilicon deposition;

[0051] S900 , forming an isolation dielectric layer 10 on top surfaces of the NP region 4 , the gate oxide layer 8 , the Poly layer 9 , and the P-shield region 7 by oxide deposition;

[0052] S1000, forming an ohmic contact alloy layer 11 on the top surfaces of the NP region 4 and the P-shield region 7 by Ni metal sputtering or deposition followed by thermal annealing;

[0053] The thickness of the Ni metal in step S1000 is 0.3um-1um.

[0054] S1100 , forming a front electrode metal layer 12 on the top of the device by sputtering Ti and AlCu metals.

[0055] In step S1100 , the thickness of the Ti metal is 0.1 um to 0.6 um, and the thickness of the AlCu metal is 2 um to 5 um.

[0056] A SiC device with improved protection performance includes a SiC sub-layer 1, a SiC drift layer 2, a P-body region 3, an NP region 4, an ohmic contact alloy layer 11, and a front electrode metal layer 12, which are arranged in sequence from bottom to top;

[0057] A pair of first trenches 5 extending downward from the top surface of the NP region 4 is provided in the SiC Drift layer 2; a second trench 6 extending downward is provided on the bottom surface of the first trench 5, and the second trench 6 is located in the SiC Drift layer 2;

[0058] A P-shield region 7 extending downward is provided at the bottom of the second trench 6; the lateral width of the P-shield region 7 (ranging from 0.3 μm to 1 μm) is greater than the lateral width of the second trench 6 and smaller than the lateral width of the first trench 5;

[0059] A gate oxide layer 8 is provided in the first trench 5 and extends downward along the sidewall of the first trench 5 through the sidewall of the second trench 6 and is connected to the P-shield region 7;

[0060] A Poly layer 9 is provided on the sidewall of the gate oxide layer 8 in the first trench 5;

[0061] A horizontally extending isolation dielectric layer 10 is provided on the top surface of the NP region 4. The isolation dielectric layer 10 extends downward in the first trench 5 after passing through the gate oxide layer 8 and the Poly layer 9, and is connected to the P-shield region 7.

[0062] The ohmic contact alloy layer 11 is located on the side of the isolation dielectric layer 10 and is formed on the top surface of the NP region 4 and the top surface of the P-shield region 7 respectively;

[0063] The bottom surface of the front electrode metal layer 12 is connected to the ohmic contact alloy layer 11 and the isolation dielectric layer 10 respectively.

[0064] The present invention adopts a first trench 5 and a second trench 6 structural design in a trench-gate SiC MOSFET. The first trench is used to prepare a gate oxide layer and a Poly layer 9 to form a gate electrode, and the second trench is used to form a P-shield region 7. By implanting a P-shield region 7 with a deeper junction depth and a narrower width than the first trench 5 at the bottom surface of the second trench 6, the depletion layer represented by the dotted line generated by the narrower P-shield region 7 and the SiC Drift layer 2 will not expand too much, thereby affecting the conduction performance of the device. The deeper junction depth of the P-shield region 7 can ensure that the depletion layer generated can wrap around the bottom corner of the trench, thereby protecting the trench gate oxide layer. At the same time, the present invention also prepares an ohmic contact on the top surface of the P-shield region 7 to connect to the source electrode, realizing the grounding treatment of the P-shield region 7 and further improving its protection capability.

Claims

1. A SiC device with improved protection performance, characterized in that: The invention comprises a SiC sub layer (1), a SiCDrift layer (2), a P-body region (3), an NP region (4), an ohmic contact alloy layer (11) and a front electrode metal layer (12) which are sequentially arranged from bottom to top; A pair of first grooves (5) extending downward from the top surface of the NP region (4) are provided in the SiC Drift layer (2); a second groove (6) extending downward is provided on the bottom surface of the first groove (5); A P-shield region (7) extending downward is provided at the bottom of the second groove (6); A gate oxide layer (8) is provided in the first trench (5), extending downward along the side wall of the first trench (5) through the side wall of the second trench (6) and connected to the P-shield region (7); A Poly layer (9) is provided on the sidewall of the gate oxide layer (8) in the first trench (5); A horizontally extending isolation dielectric layer (10) is provided on the top surface of the NP region (4); the isolation dielectric layer (10) extends downward in the first trench (5) after passing through the gate oxide layer (8) and the Poly layer (9), and is connected to the P-shield region (7); The ohmic contact alloy layer (11) is located on the side of the isolation dielectric layer (10) and is formed on the top surface of the NP region (4) and the top surface of the P-shield region (7), respectively.

2. The SiC device with improved protection performance according to claim 1, characterized in that: The bottom surface of the front electrode metal layer (12) is respectively connected to the ohmic contact alloy layer (11) and the isolation dielectric layer (10).

3. The SiC device with improved protection performance according to claim 1, characterized in that: The depth between the bottom surface of the P-body region (3) and the top surface of the SiC Drift layer (2) is 0.6um-2um.

4. The SiC device with improved protection performance according to claim 1, characterized in that: The depth between the bottom surface of the NP region (4) and the top surface of the SiC Drift layer (2) is 0.3um-1.5um.

5. The SiC device with improved protection performance according to claim 1, characterized in that: The depth between the bottom surface of the first groove (5) and the top surface of the SiC Drift layer (2) is 1 μm-3 μm.

6. The SiC device with improved protection performance according to claim 1, characterized in that: The depth between the bottom surface of the second groove (6) and the bottom surface of the first groove (5) is 0.4um-0.8um.

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