SiC field effect transistor for improving protection capability of P-shield region

Abstract

The utility model discloses a SiC field effect transistor for improving the protection capability of a P-shield region, and relates to the technical field of semiconductors. A P-shield region of a deep buried junction is formed, and the P-shield region is arranged at the bottom deeper than a groove region, so that in the use process of the device, a depletion layer formed by the P-shield region of the deep buried junction, a SiC Drift layer and an Epi layer is expanded to a corner at the bottom of the groove, a gate oxide layer at the corner at the bottom of the groove is protected, and the long-term stable use reliability of the device is improved. Meanwhile, a trench opening is etched above the P-shield region, and ohmic contact is prepared, so that grounding processing of the P-shield region is realized, and the protection capability of the P-shield region is further improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC field effect transistor with improved P-shield protection capability. Background Art

[0002] Currently, in the field of power electronics, third-generation wide-bandgap semiconductor materials, represented by SiC, have emerged as a significant force in order to achieve higher power and better efficiency to adapt to a rapidly developing society. Compared to traditional Si materials, SiC materials possess numerous physical performance advantages, such as a wide bandgap, high critical breakdown electric field, low intrinsic carrier concentration, fast saturation drift velocity, high melting point, and high thermal conductivity. These factors give SiC power devices significant advantages in applications involving high voltage, high temperature, high frequency, and high radiation. Among SiC power devices, SiC MOSFETs are a core product, combining the excellent conduction and switching characteristics of both Si MOSFETs and Si IGBTs. They have gained market favor and are now being adopted on a large scale.

[0003] SiC MOSFETs are mainly divided into two types: planar gate structure and trench gate structure. Most chip manufacturers mainly use planar structure due to its simple processing technology and high structural stability. However, in terms of chip area and cost, the trench structure still has more advantages. The trench structure has also been identified by major manufacturers as the future technology development direction. However, currently, only ROHM and Infineon's trench gate SiC MOSFETs are used in large quantities on the market. The reason is that due to the electric field concentration phenomenon at the bottom corner of the trench inside the trench structure and the interface state problem of the gate oxide layer in the SiC, the gate oxide layer at the bottom corner of the trench of the trench gate SiC MOSFET is extremely prone to premature breakdown failure, affecting long-term stable use. Utility Model Content

[0004] In response to the above problems, the utility model provides a SiC field effect transistor that protects the gate oxide layer at the corner of the trench bottom and further improves the protection capability of the P-shield region by grounding the P-shield region.

[0005] The technical solution of the utility model is:

[0006] A SiC field-effect transistor with improved P-shield protection capability includes a SiC sublayer, a SiC drift layer, a SiC epilayer, a P-body region, an NP region, an ohmic contact alloy layer, and a front electrode metal layer, which are sequentially arranged from bottom to top;

[0007] The top surface of the SiC Drift layer is provided with a plurality of P-shield regions extending downward at intervals;

[0008] The top surface of the NP region is provided with a plurality of first trench regions etched downward to the top surface of the P-shield region and a plurality of second trench regions etched downward to the SiC Epi layer;

[0009] A gate oxide layer is provided in the second trench region; a Poly layer is provided on the gate oxide layer;

[0010] The top surface of the NP region and the sidewalls of the first trench region are respectively provided with an isolation dielectric layer; the bottom surface of the isolation dielectric layer on the NP region is respectively connected to the NP region, the second trench region and the Poly layer;

[0011] The bottom of the ohmic contact alloy layer extends into the first trench region and is connected to the P-shield region, and the top is located on the side of the isolation dielectric layer.

[0012] Specifically, the bottom of the front electrode metal layer is connected to the ohmic contact alloy layer and the isolation dielectric layer respectively.

[0013] Specifically, the bottom of the front electrode metal layer (13) is connected to the ohmic contact alloy layer (12) and the isolation dielectric layer (11) respectively.

[0014] Specifically, the SiC Drift layer has a thickness of 3 μm to 10 μm.

[0015] Specifically, the depth between the bottom surface of the P-shield region and the top surface of the SiC Drift layer is 0.3 μm-1 μm.

[0016] Specifically, the SiC Epi layer has a thickness of 5 μm to 15 μm.

[0017] Specifically, the depth between the bottom surface of the P-body region and the top surface of the SiC Epi layer is 0.4 μm-1 μm.

[0018] The present invention forms a deep-buried P-shield region in a trench-gate SiC MOSFET device, positioning the P-shield region deeper than the trench region. Thus, during device operation, the depletion layer formed by the deep-buried P-shield region, the SiC Drift layer, and the Epi layer extends to the bottom corners of the trench, protecting the gate oxide layer at the bottom corners of the trench and improving the long-term stability and reliability of the device. Furthermore, by etching a trench opening above the P-shield region and preparing an ohmic contact, the P-shield region is grounded, further enhancing the protection capability of the P-shield region. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic structural diagram of the trench gate SiC MOSFET of the utility model;

[0020] Figure 2 It is a structural diagram of step S100 of the present utility model;

[0021] Figure 3 It is a structural diagram of step S200 of the present utility model;

[0022] Figure 4 It is a structural diagram of step S300 of the present utility model;

[0023] Figure 5 It is a structural diagram of step S400 of the present utility model;

[0024] Figure 6 It is a structural diagram of step S500 of the present utility model;

[0025] Figure 7 It is a structural diagram of step S700 of the present utility model;

[0026] Figure 8 It is a structural diagram of step S800 of the present utility model;

[0027] Figure 9 It is a structural diagram of step S900 of the present utility model;

[0028] Figure 10 It is a structural diagram of step S1000 of the present utility model;

[0029] Figure 11 It is a structural diagram of step S1100 of the present utility model;

[0030] Figure 12 It is a structural diagram of step S1200 of the present utility model;

[0031] Figure 13 It is a structural diagram of step S1300 of the present utility model;

[0032] In the figure, 1 is the SiC Sub layer, 2 is the SiCDrift layer, 3 is the P-shield region, 4 is the SiC Epi layer, 5 is the P-body region, 6 is the NP region, 7 is the first trench region, 8 is the second trench region, 9 is the gate oxide layer, 10 is the Poly layer, 11 is the isolation dielectric layer, 12 is the ohmic contact alloy layer, and 13 is the front electrode metal layer. DETAILED DESCRIPTION

[0033] The present invention will be described in detail below with reference to specific practical cases. Examples of the embodiments are shown in the accompanying drawings. The schematic implementations of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0034] In the description of this utility model, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of this utility model. They do not indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting this utility model. In the description of this utility model, unless otherwise specified, "plurality" means two or more.

[0035] In the description of this utility model, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections; direct connections, indirect connections through an intermediate medium, and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this utility model based on the specific circumstances.

[0036] A method for preparing a SiC field effect transistor with improved P-shield protection capability comprises the following steps:

[0037] S100, forming a SiC Drift layer 2 on the top surface of the SiC Sub layer 1 by epitaxial deposition;

[0038] The thickness of the SiC Sub layer 1 in step S100 is 100um-400um, and the doping concentration is 5E18-3E19cm -2 , SiCDrift layer 2 thickness is 3um-10um, and the doping concentration is 1E15-5E16cm -2 .

[0039] S200 , forming spaced-apart P-shield regions 3 on the top surface of the SiC Drift layer 2 by Al ion implantation;

[0040] In step S200, the depth of the bottom surface of the P-shield region 3 from the top surface of the SiC Drift layer 2 is 0.3um-1um, and the doping concentration is 1E18-1E19cm -2 .

[0041] S300, forming a SiC Epi layer 4 on the top surface of the SiC Drift layer 2 again by epitaxial deposition;

[0042] The thickness of the SiC Epi layer 4 in step S300 is 5um-15um, and the doping concentration is 1E15-1E17cm -2 .

[0043] S400 , forming a P-body region 5 on the top surface of the SiC Epi layer 4 by Al ion implantation;

[0044] The depth of the bottom surface of the P-body region 5 from the top surface of the SiC Epi layer 4 in step S400 is 0.4um-1um, and the doping concentration is 1E17-3E18cm -2 .

[0045] S500 , forming a NP region 6 on the top surface of the P-body region 5 by N ion implantation;

[0046] The depth of the bottom surface of the NP region 6 from the top surface of the SiC Epi layer 4 in step S500 is 0.2um-0.7um, and the doping concentration is 1E18-1E19cm -2 .

[0047] S600, the P-shield region 3, the P-body region 5 and the NP region 6 are activated and formed by high temperature ion annealing;

[0048] The high temperature ion annealing temperature in step S600 is 1600° C.-1900° C.

[0049] S700 , etching downwards on the top surface of the NP region 6 to form a plurality of first trench regions 7 etched to the top surface of the P-shield region 3 ;

[0050] S800 , etching downwards on the top surface of the NP region 6 to form a plurality of second trench regions 8 etched into the SiC Epi layer 4 ;

[0051] In step S800 , the depth between the bottom surface of the second trench region 8 and the top surface of the SiC Epi layer 4 is 0.6 μm-1.5 μm.

[0052] S900, oxygen is introduced into the second trench region 8 to form a gate oxide layer 9 by dry oxygen oxidation;

[0053] The thickness of the gate oxide layer 9 in step S900 is 30 nm to 100 nm.

[0054] S1000 , forming a Poly layer 10 in the second trench region 8 by polysilicon deposition;

[0055] S1100 , forming an isolation dielectric layer 11 on the top surface of the NP region 6 and the Poly layer 10 and the top surface of the P-shield region 3 by oxide deposition;

[0056] In step S1100 , the isolation dielectric layer 11 on the top surface of the P-shield region 3 completely covers the sidewalls of the first trench region 7 .

[0057] S1200, forming an ohmic contact alloy layer 12 on the top surfaces of the NP region 6 and the P-shield region 3 by Ni metal deposition followed by thermal annealing;

[0058] The thickness of the Ni metal in step S1200 is 0.3um-1um.

[0059] S1300, the top of the device by Ti and AlCu metal sputtering to form a front electrode metal layer 13;

[0060] In step S1300 , the thickness of the Ti metal is 0.1 um to 0.6 um, and the thickness of the AlCu metal is 2 um to 5 um.

[0061] A SiC field-effect transistor with improved P-shield protection capability includes, arranged from bottom to top, a SiC sublayer 1, a SiC drift layer 2, a SiC epilayer 4, a P-body region 5, an NP region 6, an ohmic contact alloy layer 12, and a front electrode metal layer 13;

[0062] The top surface of the SiC Drift layer 2 is provided with a plurality of P-shield regions 3 extending downward at intervals;

[0063] The top surface of the NP region 6 is provided with a plurality of first trench regions 7 etched downward to the top surface of the P-shield region 3 and a plurality of second trench regions 8 etched downward to the interior of the SiC Epi layer 4;

[0064] There is a gap between the bottom surface of the second trench region 8 and the bottom surface of the SiC Epi layer 4; the first trench region 7 is located between adjacent second trench regions 8;

[0065] A gate oxide layer 9 is provided in the second trench region 8, and the cross section of the gate oxide layer 9 is a U-shaped structure; a Poly layer 10 is provided on the gate oxide layer 9; and the top surface of the Poly layer 10 is in the same plane as the top surface of the NP region 6;

[0066] An isolation dielectric layer 11 is provided on the top surface of the NP region 6 and the sidewalls of the first trench region 7. The bottom surface of the isolation dielectric layer 11 on the NP region 6 is connected to the NP region 6, the second trench region 8, and the Poly layer 10. The bottom of the isolation dielectric layer 11 in the first trench region 7 is connected to the P-shield region 3, and the sides are connected to the NP region 6, the P-body region 5, and the SiC Epi layer 4.

[0067] The bottom of the ohmic contact alloy layer 12 extends into the first trench region 7 and is connected to the P-shield region 3 , and the top is located on the side of the isolation dielectric layer 11 .

[0068] The bottom of the front electrode metal layer 13 is connected to the ohmic contact alloy layer 12 and the isolation dielectric layer 11 respectively.

[0069] In the existing trench gate SiC MOSFET, the bottom corner of the trench is very likely to cause electric field concentration, and the gate oxide layer formed by SiC thermal oxidation growth has poor quality due to the high interface state density. These factors make the gate oxide layer at the bottom corner of the trench of the trench gate SiC MOSFET prone to premature breakdown failure during use, affecting long-term stable use. The utility model addresses this problem. Figure 1 As shown, in a trench-gate SiC MOSFET, a deep-buried P-shield region 3 is formed and positioned at a depth deeper than the trench region. Thus, during device operation, the depletion layer formed by the deep-buried P-shield region 3, the SiC Drift layer 2, and the Epi layer 4 extends to the bottom corners of the trench, protecting the gate oxide layer at the bottom corners of the trench and improving the long-term stability and reliability of the device. Furthermore, by etching a trench opening above the P-shield region 3 and preparing an ohmic contact, the P-shield region 3 is grounded, further enhancing the protection capability of the P-shield region 3.

Claims

1. A SiC field effect transistor with improved P-shield protection capability, characterized in that: The invention comprises a SiC sub layer (1), a SiC drift layer (2), a SiC epi layer (4), a P-body region (5), an NP region (6), an ohmic contact alloy layer (12) and a front electrode metal layer (13) arranged in sequence from bottom to top; The top surface of the SiC Drift layer (2) is provided with a plurality of P-shield regions (3) extending downward at intervals; The top surface of the NP region (6) is provided with a plurality of first trench regions (7) etched downward to the top surface of the P-shield region (3) and a plurality of second trench regions (8) etched downward to the interior of the SiC Epi layer (4); A gate oxide layer (9) is provided in the second trench region (8); a Poly layer (10) is provided on the gate oxide layer (9); The top surface of the NP region (6) and the sidewalls of the first trench region (7) are respectively provided with an isolation dielectric layer (11); the bottom surface of the isolation dielectric layer (11) on the NP region (6) is respectively connected to the NP region (6), the second trench region (8) and the Poly layer (10); The bottom of the ohmic contact alloy layer (12) extends into the first groove area (7) and is connected to the P-shield area (3), and the top is located on the side of the isolation dielectric layer (11).

2. The SiC field effect transistor with improved P-shield protection capability according to claim 1, characterized in that: The bottom of the front electrode metal layer (13) is respectively connected to the ohmic contact alloy layer (12) and the isolation dielectric layer (11).

3. The SiC field effect transistor with improved P-shield protection capability according to claim 1, characterized in that: The SiC Drift layer (2) has a thickness of 3um-10um.

4. The SiC field effect transistor with improved P-shield protection capability according to claim 1, characterized in that: The depth between the bottom surface of the P-shield region (3) and the top surface of the SiC Drift layer (2) is 0.3 μm-1 μm.

5. The SiC field effect transistor with improved P-shield protection capability according to claim 1, characterized in that: The SiC Epi layer (4) has a thickness of 5 μm to 15 μm.

6. The SiC field effect transistor with improved P-shield protection capability according to claim 1, characterized in that: The depth between the bottom surface of the P-body region (5) and the top surface of the SiC Epi layer (4) is 0.4 μm-1 μm.

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