On-chip storage and calculation system and server

Abstract

The utility model provides an on-chip storage and calculation system and a server, comprising a wafer-level substrate, the front side of the wafer-level substrate is provided with a first wiring layer, the back side of the wafer-level substrate is provided with a second wiring layer, and the first wiring layer and the second wiring layer are connected through a vertical conductive column; the lower surface of the second wiring layer is connected with a solder ball; a plurality of subsystems are integrated on the front surface of the wafer-level substrate, each subsystem comprises multiple types of functional modules, and each functional module is connected with the first wiring layer; each subsystem comprises a plurality of types of interfaces, so that the plurality of subsystems are in communication interconnection; the metal heat dissipation cover is bonded on the upper surface of the subsystem; and the liquid cooling heat dissipation structure is bonded above the metal heat dissipation cover, and the liquid cooling heat dissipation structure is provided with a flow guide groove for circulating cooling liquid.

Description

Technical Field

[0001] The utility model relates to the field of data storage and computing, and in particular to an on-chip storage and computing system. Background Art

[0002] With the rapid development of artificial intelligence and big data, the requirements for data computing and storage are becoming increasingly stringent. However, the current storage and computing systems in the industry utilize a step-by-step engineering approach: "chip-module-casing-rack-subsystem-system." The chip, in particular, integrates various cores, such as storage, interconnect, and I / O, onto a traditional substrate to create a small integrated storage and computing chip (this type of chip is small, with dimensions ≤50mm). This results in low storage capacity, slow processing speeds, and high power consumption, which limits the performance of the entire system. Furthermore, servers built using this approach are bulky and costly, requiring even more expensive heat dissipation solutions.

[0003] Therefore, how to improve the performance of storage and computing systems has become a focus of those skilled in the art. Utility Model Content

[0004] The purpose of this utility model is to provide an on-chip storage and computing system that can improve the performance of the storage and computing system.

[0005] In order to achieve the above objectives, the present invention provides an on-chip storage and computing system, comprising:

[0006] A wafer-level substrate, wherein a first wiring layer is formed on the front surface of the wafer-level substrate, and a second wiring layer is formed on the back surface of the wafer-level substrate, wherein the first wiring layer and the second wiring layer are connected via vertical conductive pillars; and solder balls are connected to the lower surface of the second wiring layer;

[0007] A plurality of subsystems are integrated on the front side of the wafer-level substrate, each of the subsystems includes multiple types of functional modules, and each of the functional modules is connected to the first wiring layer;

[0008] Each of the subsystems includes multiple types of interfaces to enable communication and interconnection between the multiple subsystems;

[0009] a metal heat dissipation cover bonded to the upper surface of the subsystem;

[0010] The liquid cooling heat dissipation structure is bonded on the top of the metal heat dissipation cover, and the liquid cooling heat dissipation structure has a guide groove for circulating the cooling liquid.

[0011] In an optional solution, each of the subsystems is bonded to the lower surface of the metal heat dissipation cover by TIM glue.

[0012] In an optional solution, the liquid cooling heat dissipation structure is bonded to the upper surface of the metal heat dissipation cover by TIM glue.

[0013] In an optional solution, the specification of the wafer-level substrate is 8 inches or 12 inches.

[0014] In an optional solution, the path of the guide groove is a rectangular waveform.

[0015] In an optional solution, the types of interfaces of the subsystem include: PCIE interface, JTAG interface, SATA interface, optical port, and power interface.

[0016] In the optional solution, the functional modules include: GPU bare core, CPU bare core, FPGA bare core, GPGPU bare core, DDR bare core, Flash bare core, power bare core, PHY bare core, and NVMe controller.

[0017] In an optional solution, the wafer-level substrate is a 12-inch wafer-level glass core ABF organic substrate.

[0018] The present invention also provides a server, which is assembled from a plurality of the above-mentioned on-chip storage and computing systems.

[0019] The beneficial effects of the present invention are:

[0020] The utility model abandons the traditional packaging substrate and assembles various core particles such as computing, storage, interconnection, I / O, etc. on the wafer to realize a complete system, providing a wider range of resource configurability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which the same reference numerals generally represent the same components.

[0022] Figure 1 This is a structural diagram of the on-chip storage and computing system in one embodiment of the present utility model.

[0023] Figure 2 This is a schematic diagram of the structure of a subsystem in one embodiment of the present invention.

[0024] Figure 3 Schematic diagram of a liquid cooling heat dissipation structure in one embodiment of the present invention.

[0025] Figure 4 Schematic diagram of the structure of a wafer-level substrate in one embodiment of the present invention.

[0026] Description of reference numerals:

[0027] 1-Power supply die; 2-GPGPU die; 3-DDR die; 4-FPGA die; 5-NVMe die; 6-CUP die; 7-GUP die; 81-First TIM glue; 9-Solder ball; 10-Metal heat sink; 11-Liquid cooling structure; 12-Flash die; 13-Second TIM glue; 14-HBM; 15-PHY die; 16-JTAG interface; 17-PCIE interface; 18-SATA interface; 19-Entrance; 20-Exit; 21-First wiring layer; 22-Second wiring layer; 23-Conductive column; 24-Wafer-level substrate; 25-Guide groove; 26-Subsystem. DETAILED DESCRIPTION

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and drawings. However, it should be noted that the technical solutions of the present invention can be implemented in a variety of different forms and are not limited to the specific embodiments described herein. The drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0029] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0030] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0031] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0032] Example 1

[0033] Reference Figures 1 to 4 This embodiment provides an on-chip storage and computing system, including:

[0034] A wafer-level substrate 24, wherein a first wiring layer 21 is formed on the front surface of the wafer-level substrate 24, and a second wiring layer 22 is formed on the back surface thereof, wherein the first wiring layer 21 and the second wiring layer 22 are connected via conductive pillars 23; and solder balls 9 are connected to the lower surface of the second wiring layer 22;

[0035] The front surface of the wafer-level substrate 24 is integrated with a plurality of subsystems 26 , each of which includes multiple types of functional modules, and each of the functional modules is connected to the first wiring layer 21 ;

[0036] Each of the subsystems includes multiple types of interfaces to enable communication and interconnection between the multiple subsystems;

[0037] A metal heat dissipation cover 10 is bonded to the upper surface of the subsystem 26;

[0038] The liquid cooling heat dissipation structure 13 is bonded on the top of the metal heat dissipation cover 10 , and the liquid cooling heat dissipation structure 13 has a guide groove 25 for circulating the cooling liquid.

[0039] Specifically, the functional modules of each subsystem of this embodiment include: GPU bare core 7, CPU bare core 6, FPGA bare core 4, GPGPU bare core 2, DDR bare core 3, Flash bare core 12, power bare core 1, PHY bare core 15, NVMe bare core 5, etc. Among them, in this embodiment, multiple DDR bare cores 3 are stacked vertically together using silicon through-hole via technology and micro-bump technology to form HBM14. HBM is the abbreviation of High Bandwidth Memory, which can significantly improve data processing speed and reduce size while improving performance. The types of interfaces of the subsystem 26 include: PCIE interface 17, JTAG interface 16, SATA interface 18, optical port, and power interface. Communication and interconnection between the multiple subsystems are achieved through these interfaces. SATA interface is a computer bus whose main function is to transmit data between the motherboard and a large number of storage devices (such as hard disks and optical drives). It is named because it uses serial data transmission and has the advantages of simple structure and hot plug support. PCIE is a high-speed serial computer expansion bus standard, which belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission. The JTAG interface is a crucial interface for chip design, verification, debugging, and testing. It enables the exchange of debugging information between the host and the chip, and can load, read, or write the contents of the chip's internal controllers, memory, and registers. An optical port (fiber optic port) is an interface used to connect to fiber optic transmission media. It enables high-speed data transmission between optical fibers and fiber optic networks. Compared to traditional electrical ports (cable ports), it offers higher transmission speeds and longer transmission distances. PHY, or port physical layer, is a common abbreviation for the physical layer of the OSI model. Ethernet is a device that operates at the physical layer of the OSI model. An Ethernet PHY is a chip that can send and receive Ethernet data frames. The NVMe controller and NVMe protocol are non-volatile memory standards tailored for flash storage and PCIe interfaces. It not only offers cross-platform compatibility (currently supported by mainstream platforms such as Windows, Linux, and VMware), but also offers lower latency, higher IOPS, and lower power consumption compared to the AHCI protocol.

[0040] The on-chip storage and computing system of this embodiment can achieve high bandwidth, high computing power, and large capacity.

[0041] High bandwidth: Four 100G optical ports are introduced through the FPGA high-speed interface, and the CPU's PCIE X16 external 100G optical port simultaneously expands data input and output bandwidth, and is supplemented by HBM (stacked DDR for high-bandwidth cache) to achieve high-bandwidth performance.

[0042] High computing power: The CPU is equipped with two GPGPUs and a GPU for data processing, and is also connected to an FPGA. PCIe X16 communication is used between the CPU and GPU, and between the CPU and FPGA to meet data bandwidth requirements. During calculations, the GPU and FPGA simultaneously accelerate the CPU's computing power, thus achieving high computing power.

[0043] 3. Large Capacity: Connecting the CPU to the FPGA, the FPGA's high-speed PCIe interface expands into multi-channel NVMe storage. This storage space is equipped with multiple high-capacity FLASH chips and multiple DDR memory chips. Multiple NVMe storage groups can be expanded based on the number of FPGA interfaces, enabling a single subsystem to store up to 256TB of data.

[0044] In this embodiment, each subsystem is bonded to the lower surface of the metal heat dissipation cover 10 via a first TIM adhesive 8. The liquid cooling heat dissipation structure 13 is bonded to the upper surface of the metal heat dissipation cover 10 via a second TIM adhesive 13. The path of the guide groove 25 of the liquid cooling heat dissipation structure 13 is a rectangular waveform.

[0045] At the hardware level, this embodiment integrates multiple subsystems (multiple storage and computing units) on a wafer-level substrate. These subsystems are combined through RAID (Redundant Array of Independent Disks) to form multiple storage and computing arrays to improve overall performance and redundancy. A liquid cooling structure is also designed to achieve a high-bandwidth, high-computing power, large-capacity, and high-heat dissipation on-wafer storage and computing system. The system also integrates multiple interfaces such as PCIE, JTAG, SATA, optical ports, and power interfaces to meet the application requirements of different interfaces.

[0046] In this embodiment, the wafer-level substrate is a 12-inch wafer-level glass core ABF organic substrate. The advantages of the glass ABF substrate are: higher interconnection density: the via and wiring capabilities of the glass substrate are better than those of the traditional resin substrate, and the integration level can be increased by 50% at the same size; faster transmission rate: the extremely low dielectric constant (Dk) and dissipation factor (Df) of the glass substrate enable the signal transmission speed of the glass substrate to reach 448GHz, while the maximum speed of ordinary substrates is only 100GHz; better reliability: the glass substrate has a lower CTE and better thermal performance, and can withstand high temperatures of 1000°C, while ordinary substrates usually operate at temperatures of -55°C to +125°C.

[0047] The liquid cooling structure is made of nickel-plated copper, designed with a "snake-shaped" guide groove, and adopts liquid cooling to effectively increase the heat dissipation capacity per unit area.

[0048] At the software level, the entire system is software-defined through the three-level definition of the storage protocol layer, storage service layer, and storage core layer. Software-defined methods are well known to those skilled in the art and will not be detailed here.

[0049] The manufacturing process of the on-chip storage and computing system of this embodiment is as follows:

[0050] Using 12-inch wafer-level glass core ABF organic substrate, through TGV (through glass via technology) + wiring + embedded capacitance and resistance process, the wafer-level substrate is produced. The specific process flow is as follows:

[0051] (1) Etching the glass substrate through the TGV process to etch a through-glass hole with a certain aspect ratio (10:1 or 5:1);

[0052] (2) Electroplating copper in through-holes;

[0053] (3) Grind away the excess copper layer on the surface to expose the TGV hole. At this step, the hole is filled with copper to form a conductive column.

[0054] (4) Perform RDL wiring on the glass wafer (the number of wiring layers is determined by the number of pins on the chip);

[0055] (5) On the inner layer of RDL (the second top layer), according to the position of resistors and capacitors, cavities are etched, capacitors and resistors are buried using solder and reflow, and covered with ABF above the RDL and resistors and capacitors;

[0056] (6) Produce a PAD layer on the top layer of RDL;

[0057] (7) PAD surface plating of nickel, gold and other metals (for functional chip flip-chip);

[0058] (8) Apply UV film to the front of the finished glass substrate for protection;

[0059] (9) Grind the back of the substrate to expose the bottom of the TGV (which is now filled with copper);

[0060] (10) Follow steps 1-4 to perform RDL wiring on the back side and make PAD on the back side of the substrate;

[0061] (11) The PAD surface is plated with nickel, gold and other metals to facilitate subsequent ball planting;

[0062] At this point, the production of the entire wafer-level substrate is completed.

[0063] The GPU, CPU, FPGA, GPGPU, DDR bare core, Flash bare core, power bare core, 100GB PHY bare core and other functional chips required by the subsystem (storage and computing unit) are formed with micro bumps on the bare core PAD through the bumping or C2 process;

[0064] It should be noted that during the tape-out process, the TSV+uBUMP on the back of the DDR and Flash die are simultaneously completed for functional interconnection of 3D vertical stacking.

[0065] (2) Through FC+reflow+bottom underfill, the bare die is soldered to the wafer-level glass substrate to form multiple storage and computing unit arrays;

[0066] (3) On the back of the bare die, a metal heat sink cover is bonded using TIM glue (Thermal Interface Material). It should be noted that the metal heat sink cover is made of copper and needs to be nickel-plated on the copper surface to prevent oxidation.

[0067] (4) wafer-level substrate backside ball implantation;

[0068] (5) Above the metal heat dissipation cover of the on-chip storage and computing system, a liquid cooling structure is connected through TIM glue to promptly dissipate the heat generated by the chip operation.

[0069] Among them, (1) the liquid cooling heat dissipation structure has a "snake-shaped" guide groove of a certain depth, and the guide groove is distributed as densely as possible; (2) a metal sealing cover is designed on the guide groove and welded to the guide groove on all sides; (3) a coolant inlet 19 and an outlet 20 are designed at both ends of the guide groove, respectively, and sealed with a sealing plug to prevent leakage.

[0070] This on-wafer storage and computing system eschews traditional packaging substrates and innovatively integrates various cores, including compute, storage, interconnect, and I / O, on the wafer to create a complete system. This provides a wider range of resource configurability and software-defined control over the connections between modules and even the functions of each module. Using advanced packaging and manufacturing processes, this on-wafer storage and computing system tightly integrates numerous compute units, storage units, power management units, and cooling systems onto a single glass wafer (300mm x 300mm). Its core advantage lies in its powerful storage and computing capabilities, enabling rapid processing of complex computing tasks such as large-scale data analysis and deep learning model training. Furthermore, its large storage capacity easily addresses the storage needs of massive amounts of data, effectively addressing the bottlenecks of traditional network transmission, compute, and storage separation. It utilizes a 12-inch wafer-level glass core ABF organic substrate, fabricated using TGV, routing, and embedded capacitor and resistor processes. The packaging utilizes 2.5D, 3DuBUMP, and C2W assembly technology, achieving a minimum chip pitch of 70μm. The volume is about 10 times smaller than that of a traditional single server, the transmission rate is increased by 20%, and energy consumption is saved by 30%.

[0071] Multiple wafer-level storage and computing systems are assembled and integrated together in a "prefabricated-assembly-integrated" and "lossless" manner to form a powerful small server, which greatly reduces the size of the server, saves space, and is more conducive to heat dissipation.

[0072] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. An on-chip storage and computing system, characterized in that: include: A wafer-level substrate, wherein a first wiring layer is formed on the front surface of the wafer-level substrate, and a second wiring layer is formed on the back surface of the wafer-level substrate, wherein the first wiring layer and the second wiring layer are connected via vertical conductive pillars; and solder balls are connected to the lower surface of the second wiring layer; A plurality of subsystems are integrated on the front side of the wafer-level substrate, each of the subsystems includes multiple types of functional modules, and each of the functional modules is connected to the first wiring layer; Each of the subsystems includes multiple types of interfaces to enable communication and interconnection between the multiple subsystems; a metal heat dissipation cover bonded to the upper surface of the subsystem; The liquid cooling heat dissipation structure is bonded on the top of the metal heat dissipation cover, and the liquid cooling heat dissipation structure has a guide groove for circulating the cooling liquid.

2. The on-chip storage and computing system according to claim 1, wherein: Each of the subsystems is bonded to the lower surface of the metal heat dissipation cover by TIM glue.

3. The on-chip storage and computing system according to claim 1, wherein: The liquid cooling heat dissipation structure is bonded to the upper surface of the metal heat dissipation cover by TIM glue.

4. The on-chip storage and computing system according to claim 1, wherein: The wafer-level substrate has a size of 8 inches or 12 inches.

5. The on-chip storage and computing system according to claim 1, wherein: The path of the guide groove is a rectangular waveform.

6. The on-chip storage and computing system according to claim 1, wherein: The types of interfaces of the subsystem include: PCIE interface, JTAG interface, SATA interface, optical port, and power interface.

7. The on-chip storage and computing system according to claim 1, wherein: The functional modules include: GPU bare core, CPU bare core, FPGA bare core, GPGPU bare core, DDR bare core, Flash bare core, power bare core, PHY bare core, and NVMe controller.

8. The on-chip storage and computing system according to claim 1, wherein: The wafer-level substrate is a 12-inch wafer-level glass core ABF organic substrate.

9. A server, characterized in that: It is composed of multiple on-chip storage and computing systems as described in any one of claims 1-8.

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