Chip positioning test device

Abstract

The utility model provides a chip positioning test device. The chip positioning test device comprises a probe support and a test probe arranged on the probe support. Wherein the metal bump of the to-be-detected chip comprises a support column arranged on a chip protection layer and a solder cap positioned at the end part of the support column; the test probe is provided with an open end comprising a memory metal piece, and the open end of the test probe is in contact conduction with the support column when meeting a preset condition; a first positioning piece is arranged on the probe support, a second positioning piece is arranged on the to-be-detected chip, and the test probe and the to-be-detected chip are positioned through the first positioning piece and the second positioning piece. According to the utility model, the related test of the chip can be completed under the condition that the solder cap is not damaged.

Description

Technical Field

[0001] The utility model relates to the technical field of chip detection, and more specifically, to a chip positioning test device. Background Art

[0002] In the field of semiconductor chip stacking technology, performance testing is required before chips are formed or shipped, enabling quality inspection, grading, and defective product screening. Currently, various chip stacking methods exist, such as HBM, Wide-IO, and HMC. Testing these chips requires external probes to contact the metal bumps on the chip to transmit test signals and test results.

[0003] However, since the metal bumps on the chip are small and fragile, if existing probes are used to directly perform contact tests on the metal bumps, the solder ends of the metal bumps will be damaged. In addition, the positioning error between the chip and the probe will also cause the probe and the solder end to collide, thereby affecting the subsequent bonding process and chip performance, and affecting the product yield.

[0004] Therefore, there is an urgent need for a chip testing solution that can achieve precise positioning between the chip and the test signal while ensuring conduction between the two, thereby preventing the solder ends of the metal bumps from being damaged and affecting chip performance. Utility Model Content

[0005] In view of the above problems, the purpose of the present invention is to provide a chip positioning test device to solve the problem that the solder end of the chip is damaged due to contact testing and positioning reasons in the existing chip testing scheme, thereby affecting the chip performance.

[0006] The chip positioning test device provided by the utility model comprises: a probe holder and a test probe arranged on the probe holder; wherein the metal bump of the chip to be tested comprises a support column arranged on the chip protection layer and a solder cap located at the end of the support column; the test probe has an open end, comprising a memory metal part, and the open end of the test probe is in contact with and connected to the support column when a preset condition is met; a first positioning part is provided on the probe holder, and a second positioning part is provided on the chip to be tested, and the test probe and the chip to be tested are positioned by the first positioning part and the second positioning part.

[0007] In addition, an optional technical solution is that the first positioning member includes at least one alignment hole, and the second positioning member includes a marking corresponding to the position of the alignment hole; the marking is a color or mark that is different from the chip to be detected.

[0008] In addition, an optional technical solution is that the first positioning member includes at least one positioning block / groove, and the second positioning member includes a groove / positioning block corresponding to the position of the positioning block / groove; when the test probe contacts and conducts with the support column, the positioning block is limited in the groove at the corresponding position.

[0009] In addition, an optional technical solution is that the probe holder is a PCB, and the test probe is connected to an external test system through the PCB; and the alignment hole is a through hole passing through the PCB.

[0010] In addition, an optional technical solution is that the alignment holes are set on both sides of the PCB, and the marking objects are set in the area of ​​the chip to be tested where the metal bumps are not set; or, the alignment holes are set inside each test probe, and the marking objects are the solder caps.

[0011] In addition, an optional technical solution is to provide a camera module on the side of the alignment hole away from the marking object; wherein, the camera module is used to capture the position image between the chip to be detected and the test probe, so as to adjust the relative position of the chip to be detected and the test probe according to the position image.

[0012] In addition, an optional technical solution is that it also includes a driving device for driving the movement of the chip to be tested and a suction nozzle head arranged on the driving device; wherein, the suction nozzle head is adsorbed and fixed on the chip to be tested; the driving device is used to adjust the relative position between the chip to be tested and the test probe according to the position image.

[0013] In addition, an optional technical solution is that the test probe has a deformable internal cavity structure; the cross-section of the cavity structure is a circular structure; and the difference between the cross-sectional dimensions of the cavity structure and the solder cap ranges from 0 to 50 um.

[0014] In addition, an optional technical solution is that the preset condition is that the temperature is greater than 70°C; when the preset condition is not met, the open end of the test clamp is in an open state, and the size of the open end is larger than the size of the solder cap.

[0015] Utilizing the above-mentioned chip positioning test device, the test probe is set to a cavity structure with an open end, and a shape-changeable memory metal material is used, so that the open end of the test probe is in contact with the support column and is conductive when the preset conditions are met. At the same time, the structure of the first positioning member and the second positioning member is coordinated to ensure the positional accuracy of each test probe and the metal bump at the corresponding position, and the conduction between the test probe and the metal bump is achieved through the support column, thereby avoiding direct contact between the test probe and the solder cap, ensuring the integrity of the solder cap's appearance, and avoiding the subsequent process and performance being affected by damage to the solder cap.

[0016] To achieve the above and related purposes, one or more aspects of the present invention include features described in detail below. The following description and accompanying drawings detail certain exemplary aspects of the present invention. However, these aspects are merely indicative of some of the various ways in which the principles of the present invention may be employed. Furthermore, the present invention is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more clear and easy to understand. In the accompanying drawings:

[0018] Figure 1 This is a structural diagram of the chip positioning test device according to an embodiment of the present invention in a first state;

[0019] Figure 2 This is a structural diagram of the chip positioning test device according to an embodiment of the present invention in the second state;

[0020] Figure 3 This is a schematic diagram of the structure of the chip positioning test device before positioning according to an embodiment of the present utility model;

[0021] Figure 4 This is a schematic diagram of the chip positioning test device after positioning according to an embodiment of the present utility model;

[0022] Figure 5 This is a schematic diagram of the structure of a chip positioning test device before positioning according to another embodiment of the present invention;

[0023] Figure 6 2 is a schematic diagram of the chip positioning test device after positioning according to another embodiment of the present invention.

[0024] The reference numerals include: test probe 1, base 11, inclined side arm 12, open end 13, solder cap 21, support column 22, alignment hole 31, nozzle head 5, chip to be tested 6, marking object 61, camera module 7, AC-DA chip 8.

[0025] The same reference numerals throughout the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0026] In the following description, for illustrative purposes, numerous specific details are set forth to provide a comprehensive understanding of one or more embodiments. However, it will be apparent that the embodiments may be practiced without these specific details. In other examples, well-known structures and devices are shown in block diagram form to facilitate description of one or more embodiments.

[0027] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation to the present invention.

[0028] Those skilled in the art will understand that, unless otherwise stated, the singular forms "a," "an," "said," and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present utility model refers to the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that the term "and / or" used herein includes any and all combinations of one or more associated listed items.

[0029] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art in the field to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with those in the context of the prior art, and will not be interpreted in an idealized or overly formal sense unless defined as such herein.

[0030] In order to describe the chip positioning test device in the present invention in detail, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0031] Figures 1 to 6 The overall or partial schematic structures of the chip positioning test device according to the embodiment of the present utility model are shown from different angles.

[0032] like Figures 1 to 6As shown together, the chip positioning test device of the embodiment of the present invention includes a probe holder and a test probe 1 arranged on the probe holder, wherein the metal bump of the chip 6 to be tested includes a support column 22 arranged on the chip protection layer and a solder cap 21 located at the end of the support column 22. Generally, the material of the support column 22 is slightly harder than the solder cap 21. For example, the support column 22 can be made of copper, which is less susceptible to damage than the solder cap 21. In order to avoid direct contact between the traditional test probe 1 and the solder cap 21, the test probe 1 in the embodiment of the present invention has an open end 13 and may also include a deformable internal cavity structure, which may specifically be a memory metal part, or a memory metal and its alloy part, wherein, The ratio of the alloy and the memory metal can be flexibly set according to the deformation requirements of the test probe. It can be seen that according to the characteristics of the memory metal, the open end 13 of the test probe 1 can be in contact and connected with the support column 22 when the preset conditions are met, so that the metal bump to be tested and the test probe 1 can realize signal transmission through the support column 22, that is, the test signal is partially transmitted through the support column 22 to ensure the integrity of the solder cap 21 at its end. In order to ensure the position accuracy between the test probe 1 and the chip to be tested 6, a first positioning member is provided on the probe bracket, and a second positioning member is provided on the chip to be tested 6. The test probe 1 and the chip to be tested 6 are precisely positioned by the first positioning member and the second positioning member.

[0033] The first positioning member can be at least one alignment hole 31 provided on the probe holder, and the second positioning member in this case is a marker 61 corresponding to the position of the alignment hole 31. When relative displacement occurs between the probes and the chip 6 to be tested, the marker 61 can be observed through the alignment hole 31. In a direction perpendicular to the probe holder, if the alignment hole 31 can be accurately aligned with the standard marker, it indicates that the positions of the two are corresponding. At this time, the positions of the two can be further adjusted along this direction, and finally a contact test is achieved. The marker 61 can be a special color or logo for the chip 6 to be tested.

[0034] It can be seen that the first positioning member and the second positioning member can also be set as compatible structural members such as positioning blocks and grooves. For example, the first positioning member includes at least one positioning block / groove, and the second positioning member at this time is a groove / positioning block that is compatible with the positioning block / groove in position and shape. When the test probe 1 moves to the support column to contact and conduct, the positioning block can be limited in the groove corresponding to the position, that is, through the cooperation of the positioning block and the groove, the position of the chip to be tested and the test probe 1 can be accurately located.

[0035] In a specific embodiment of the present invention, the probe holder can be a DSA chip, and the test probe 1 can be connected to an external test system through the DSA chip. At this time, the through hole is a through hole that passes through the DSA chip, and is aligned with the corresponding marking object 61 through the through hole to achieve a one-to-one position correspondence between each test probe 1 and each metal bump on the chip 6 to be tested.

[0036] It should be noted that the alignment holes 31 can be set on both sides of the DSA chip, and the corresponding marking objects 61 are set in the area where the metal bumps are not set on the chip to be tested 6, that is, the alignment between the entire test chip and the test probe 1 is achieved through at least two alignment holes 31 at the edge of the chip, such as Figure 3 and Figure 4 Alternatively, the alignment hole 31 can also be provided inside each test probe 1, that is, a through hole penetrating the internal cavity is provided at the base of the test probe 1 as the alignment hole 31, and the marking 61 at this time corresponds to the solder cap under the test probe 1, thereby achieving a one-to-one alignment effect, as shown Figure 5 and Figure 6 As shown, if there is a position deviation, the position of the test probe 1 at the corresponding position can be adjusted to ensure the accuracy of each detection position.

[0037] Furthermore, a corresponding camera module 7 can be set on the side of the alignment hole 31 away from the marking object 61; wherein, the camera module 7 can capture a real-time position image between the chip to be detected 6 and the test probe 1, so that the test system controls the driving device to adjust the relative position of the chip to be detected 6 and the test probe 1 according to the position image.

[0038] Specifically, the chip positioning test device of an embodiment of the present invention also includes a driving device for driving the chip to be tested 6 or the test probe 1 to move, and a suction nozzle head 5 arranged on the driving device; for example, the suction nozzle head 5 can be adsorbed and fixed on the chip to be tested 6; the relative position between the chip to be tested 6 and the test probe 1 is adjusted according to the position image by the driving device.

[0039] In addition, a pressure sensor can be set above the test probe 1. When the test probe contacts the chip protective layer, the pressure sensor can detect a sudden change signal. At this time, it can be confirmed that the test probe has moved to the corresponding position, thereby preventing the test probe from being damaged or broken due to excessive extrusion. That is, double insurance is achieved through the positioning piece and the pressure sensor to improve the test accuracy.

[0040] As a specific example, the above-mentioned preset conditions can be set as temperature conditions, so that the memory metal is in different shapes at different temperatures, thereby completing the connection or disconnection between the test probe 1 and the metal bump; wherein, within the first preset temperature range, the open end 13 of the test probe 1 is opened, and at this time, the test probe 1 can be driven by the driving device to move to the outside of the support column 22, so that the entire metal bump is located in the internal cavity of the test probe 1; the external ambient temperature is changed so that within the second preset temperature range, the open end 13 of the test probe 1 retracts and clamps the support column 22, and the solder cap 21 at this time avoids in the internal cavity of the test probe 1, thereby effectively protecting the solder cap 21 structure when the metal bump is in contact and conductive with the test probe 1.

[0041] The temperature range and shape types of memory metals can be diversified through material design and processing technology. The types of memory metal materials may include:

[0042] 1. Low-temperature range materials: able to operate in a temperature range as low as -100°C. For example, copper-based alloys (such as Cu-Zn-Al) can exhibit good shape memory effects in low-temperature environments;

[0043] 2. Materials in the normal temperature range: For example, nickel-titanium alloy (Nitinol) usually exhibits the best shape memory effect between -50°C and 100°C;

[0044] 3. High temperature range: NiTi alloys with the addition of hafnium (Hf) or aluminum (Al) can increase the phase transition temperature to 200°C or even higher. For example, the phase transition temperature of Ni-Ti-Hf alloy can reach 200°C to 400°C;

[0045] 4. Ultra-high temperature range: Iron-based alloys (such as Fe-Mn-Si) also exhibit shape memory effect in the temperature range of 200°C to 400°C. Such materials can be used in extremely high temperature environments.

[0046] In a specific embodiment of the present invention, the memory metal adopts a metal material within the normal temperature range (for example, nickel-titanium alloy). At this time, the first preset temperature can be set to normal temperature, ranging from 0 to 70°C; the range of the second preset temperature is greater than 70°C, and the first preset temperature can also be preferably set to normal temperature, for example, 0 to 40°C, which can ensure that the open end 13 of the test probe 1 is in an open state under normal temperature, and the size of the open end 13 after opening is larger than the maximum size of the metal bump, so that the metal bump can penetrate into the internal cavity of the test probe 1. During the test process, the test probe 1 is temperature-controlled and heated or its ambient temperature is changed so that the ambient temperature reaches the second preset temperature range required for the deformation of the test probe 1. At this time, the open end 13 of the test probe 1 shrinks inward and deforms until it fits with the support column 22.

[0047] Since the solder cap 21 on the chip is usually a spherical structure, the support column 22 below it is a cylindrical structure, which is adapted to the outer shape of the metal bump. In order to achieve that the test probe 1 can effectively contact the support column 22 when deformed, the cross-section of the internal cavity of the test probe 1 (parallel to the direction of the chip protective layer) can be set to a circular structure, and ensure that the space of the internal cavity has sufficient margin to accommodate the solder cap 21. For example, the difference between the cross-sectional dimensions of the internal cavity and the solder cap 21 ranges from 0 to 50um, and can preferably be set to 0 to 27um. At this time, the solder cap 21 can be effectively avoided from colliding with the test probe 1, ensuring that the open end 13 of the test probe 1 can be safely avoided in the internal cavity before and after the inward deformation, thereby ensuring the integrity of the solder cap 21.

[0048] In the chip positioning test device of an embodiment of the present invention, the test probe 1 is a hollow structure having an open end 13, an internal cavity connected to the open end 13, and a base 11 connected to the probe bracket. Furthermore, the open end 13 and the base 11 are connected by an inclined side arm 12, so that when the open end 13 is connected to the support column 22, the solder cap 21 is avoided; within the first preset temperature range, the size of the open end 13 is larger than the size D of the solder cap 21, or further smaller than the size E of the internal cavity. At this time, when the test probe 1 is deformed due to the influence of temperature, since the base 11 is a solid structure, its deformation has little effect on the size. At the same time, under the action of the inclined side arm 12, the deformation of the open end 13 is the largest, thereby achieving the deformation effect of opening outward or contracting inward.

[0049] It should be noted that to prevent the test probe 1 from shrinking or expanding as a whole, which could cause the internal cavity to collide with the solder cap 21, the open end 13 and / or the inclined side arm 12 of the test probe 1 can be made of a memory metal material, while the base 11 and other parts can be made of conventional probe materials to ensure effective opening or clamping of the open end 13. The base 11 can have a rectangular or square cross-section to facilitate its fixation on the probe holder and reduce interference with test probes 1 in other locations.

[0050] In addition, since there will be certain temperature changes during the process of testing the chip through the test probe 1, in order to avoid mutual interference between adjacent test probes 1 or between the test probe 1 and the test chip, an insulating protective layer can be set around the test probe 1 on the outside of the base 11 of the test probe 1. The material and thickness of the insulating protective layer can be set according to the specific probe size, which can play both insulating and protective roles. In addition, the test probe 1 can be connected to an external test system through a PCB, and the chip to be tested 6 can be tested through the test system. In other words, the test probe 1 can be fixed on the PCB through a probe holder or the PCB can be directly used as a probe holder. During the test process, the external test system is connected to the test probe 1 through the PCB and the AC-DA chip 8 set on the PCB to achieve the transmission of the test signal.

[0051] The chip to be tested is tested using the above-mentioned chip positioning test device, including: first, moving the test probe to the top of the chip to be tested, and then aligning the test probe and the chip to be tested by using a first positioning member and a second positioning member; then, controlling the test probe to descend or the chip to be tested to rise until the end of the test probe is located on the outside of the support column; finally, controlling the test probe to contact and conduct with the support column when preset conditions are met, and sending a test signal to the chip to be tested through the test probe to complete the test of the chip to be tested.

[0052] Specifically, when using the chip positioning test device to test the chip to be tested, the probe holder and the test probe thereon are first moved by the driving device to directly above the metal bump on the chip to be tested; then, when the open end of the test probe is in an open state, the test probe is controlled to move downward until the first positioning member and the second positioning member are aligned with each other, and the open end is located outside the support column of the metal bump; then, the test probe is controlled to be within a second preset temperature range. Due to the characteristics of the memory metal, the open end of the test probe will shrink inward at this time and contact and conduct with the support column. Finally, the external test system completes the relevant performance testing of the chip through the test probe.

[0053] According to the chip positioning test device of the utility model described above, the test probe is set to a cavity structure with an open end, and at the same time, it is combined with a shape-changeable memory metal material, so that the open end of the test probe can undergo corresponding deformation when the preset conditions are met, so that its open end can be in contact and conduct with the support column in a clamping manner. At the same time, the structure of the first positioning member and the second positioning member is combined to ensure the positional accuracy of each test probe and the metal bump at the corresponding position, and to avoid direct contact between the test probe and the solder cap, thereby achieving conduction between the test probe and the metal bump through the support column, ensuring the integrity of the solder cap, and avoiding the chip performance and service life being affected by damage to the solder cap.

[0054] The chip positioning test device according to the present invention has been described above by way of example with reference to the accompanying drawings. However, those skilled in the art will appreciate that various improvements may be made to the chip positioning test device proposed above without departing from the scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the contents of the appended claims.

Claims

1. A chip positioning test device, characterized in that: include: A probe holder and a test probe arranged on the probe holder; wherein, The metal bumps of the chip to be tested include support pillars arranged on the chip protection layer and solder caps located at the ends of the support pillars; The test probe has an open end and includes a memory metal piece, and the open end of the test probe contacts and conducts with the support column when a preset condition is met; A first positioning member is provided on the probe holder, and a second positioning member is provided on the chip to be tested. The test probe and the chip to be tested are positioned by the first positioning member and the second positioning member.

2. The chip positioning test device according to claim 1, characterized in that: The first positioning member includes at least one alignment hole, and the second positioning member includes a marking corresponding to the position of the alignment hole; The marker is a color or logo that is different from the chip to be detected.

3. The chip positioning test device according to claim 1, characterized in that: The first positioning member includes at least one positioning block / groove, and the second positioning member includes a groove / positioning block corresponding to the position of the positioning block / groove; When the test probe is in contact with the support column, the positioning block is limited in the groove at the corresponding position.

4. The chip positioning test device according to claim 2, characterized in that: The probe holder is a PCB, and the test probe is connected to an external test system via the PCB; The alignment hole is a through hole passing through the PCB.

5. The chip positioning test device according to claim 4, characterized in that: The alignment holes are provided on both sides of the PCB, and the marking objects are provided in the area of ​​the chip to be tested where the metal bumps are not provided; or, The alignment hole is arranged inside each test probe, and the marking object is the solder cap.

6. The chip positioning test device according to claim 2, characterized in that: A camera module is provided on the side of the alignment hole away from the marking object; wherein, The camera module is used to capture a position image between the chip to be detected and the test probe, so as to adjust the relative position of the chip to be detected and the test probe according to the position image.

7. The chip positioning test device according to claim 6, characterized in that: It also includes a driving device for driving the chip to be detected to move and a nozzle head arranged on the driving device; wherein, The nozzle head is adsorbed and fixed on the chip to be detected; The driving device is used to adjust the relative position between the chip to be detected and the test probe according to the position image.

8. The chip positioning test device according to claim 1, characterized in that: The test probe has a deformable internal cavity structure; The cross section of the cavity structure is a circular structure; and The difference between the cross-sectional dimensions of the cavity structure and the solder cap ranges from 0 to 50 μm.

9. The chip positioning test device according to claim 1, characterized in that: The preset condition is that the temperature is greater than 70°C; When the preset condition is not met, the open end of the test clamp is in an open state, and the size of the open end is larger than the size of the solder cap.

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