Chip packaging structure and chip packaging module
By integrally forming a wire module on the substrate as a resistance sensor, the problems of low accuracy and complex operation of stress detection between the substrate and the PCB are solved, achieving more accurate and convenient stress detection.
Patent Information
- Application Number
- CN202422796110.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-15
- Publication Date
- 2025-10-10
- Estimated Expiration
- 2034-11-15
AI Technical Summary
In the prior art, the mismatch in thermal expansion coefficients between the substrate and the PCB leads to stress problems, resulting in failures such as cracked solder joints and circuits. Traditional stress detection methods also have low accuracy and are complex to operate.
Multiple wire modules are integrally formed on the substrate as resistance sensors. Stress is detected by the resistance change of the wire modules. The wire modules are arranged around the stress site and distributed at specific angles to avoid pasting operations. They are integrated into the substrate in combination with the etching process.
The accuracy of stress detection is improved, the operation process is simplified, the influence of adhesives on the test results is reduced, and the convenience and accuracy of detection are enhanced.
Smart Images
Figure CN223427503U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a chip packaging structure and a chip packaging module. Background Art
[0002] The substrate is the bridge connecting the chip (bare die) and the PCB, providing interconnection, protection, support and other functions for the chip. During the packaging process, stress will be generated between the substrate and the PCB due to the mismatch of the thermal expansion coefficients of their respective materials. Stress can lead to failure problems such as cracking of solder joints and circuits, so stress testing is required for areas where stress is prone to occur.
[0003] Currently, stress is detected by pasting detection sensors on areas where stress is likely to occur. In this method, the strength and thermal stability of the adhesive used when gluing can have a significant impact on the detection results. In addition, the accuracy of stress detection results is low when the detection sensors are pasted on the surface of the substrate.
[0004] In addition, when pasting the detection sensor, if the pasting space is small, not only is the operation difficult, but the substrate may also need to be destroyed, which brings great inconvenience to the detection. Utility Model Content
[0005] The purpose of the embodiments of the present application is to provide a chip packaging structure that can improve the accuracy of stress detection and make detection more convenient. In addition, the present application provides a chip packaging module having this chip packaging structure.
[0006] In order to achieve the above objectives, this application provides the following technical solutions:
[0007] A chip packaging structure, comprising:
[0008] Substrate, used to connect the die and PCB;
[0009] The resistance sensor includes a plurality of integrally formed wire modules disposed inside or on the surface of the substrate for detecting stress of the substrate, wherein the resistance values of the plurality of wire modules are equal.
[0010] By integrally forming the wire module on the substrate, the wire module can at least be set inside the substrate during the substrate manufacturing process, so that the resistance sensor can detect the stress condition inside the substrate, thereby improving the accuracy of substrate stress detection.
[0011] Optionally, in the above chip packaging structure, the plurality of wire modules are arranged around the stress location of the substrate, and the angle between the adjacent wire modules arranged in the surrounding direction is 40° to 50°.
[0012] Multiple conductor modules are arranged around the stress site and spaced at preset angles, so that different conductor modules can be arranged in different directions, thereby enabling targeted and more accurate detection of stress in multiple directions inside the substrate.
[0013] Optionally, in the above chip packaging structure, the wire modules include at least three, and the central angle corresponding to the distribution of all the wire modules in the surrounding direction is at least 90°.
[0014] By further optimizing the number of wire module settings and the distribution angle, stress can be detected in more directions and a larger range while meeting the basic stress detection requirements.
[0015] Optionally, in the above chip packaging structure, the substrate includes a top layer on which the bare die is disposed, a bottom layer connected to a PCB, and a plurality of intermediate layers located between the top layer and the bottom layer, and:
[0016] Each of the wire modules is arranged in one of the intermediate layers, and all of the wire modules are arranged in a plurality of consecutively adjacent intermediate layers;
[0017] Alternatively, all the wire modules are arranged in the same middle layer.
[0018] The conductor modules are arranged in adjacent middle layers or the same middle layer, which expands the arrangement of the conductor modules inside the substrate and can also perform more accurate detection for different stress generation situations.
[0019] Optionally, in the above chip packaging structure, the substrate includes a top layer for arranging the bare chip and a bottom layer for connecting to the PCB, and all the wire modules are arranged on the top layer or the bottom layer.
[0020] The wire module can be set not only inside the substrate, but also on the outer layer of the substrate to detect the stress generated on the outer layer of the substrate, providing more setting methods for the wire module and further meeting diverse detection needs.
[0021] Optionally, in the above chip packaging structure, the wire module is etched on the top layer, the bottom layer or the middle layer to be integrally formed with the substrate.
[0022] The wire module is integrally formed inside or on the surface of the substrate by etching. This allows the wire module to be arranged while also being formed using the same process steps as in the substrate manufacturing process, thus facilitating the arrangement of the wire module.
[0023] Optionally, in the above chip packaging structure, each of the wire modules has two pins, one of the pins of all the wire modules is interconnected and fanned out to form a common output end, and the other pins of all the wire modules are fanned out separately to form multiple independent output ends.
[0024] The pins of the wire modules are interconnected to form a common output terminal, so that the pins of multiple wire modules can be connected to a solder ball through a common output terminal when fanning out, reducing the number of solder balls occupied. At the same time, setting an independent output terminal can enable each wire module to be detected independently.
[0025] Optionally, in the above chip packaging structure, the wire module is formed by bending and extending the wire.
[0026] The conductor module of this structure has the advantages of being simple in structure and easy to be arranged on a substrate, and is easy to be formed on the substrate, in addition to realizing normal stress detection.
[0027] Optionally, in the above chip packaging structure, the line width of the conductive line is 15um to 30um, the line length is at least 20,000um, and the spacing formed by the bending of adjacent line segments is 15um to 30um.
[0028] This value range can ensure that the wire module has good detection performance, higher detection accuracy, and improved sensitivity of the resistance sensor.
[0029] A chip packaging module comprises the above-mentioned chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.
[0031] Figure 1 A schematic diagram of the chip packaging structure provided in an embodiment of the present application;
[0032] Figure 2 This is a schematic diagram of the structure in which multiple conductor modules are distributed around the stress location.
[0033] exist Figure 1 and Figure 2 middle:
[0034] 1-substrate, 2-bare die, 3-PCB, 4-wire module, 5-solder ball;
[0035] 101-top floor, 102-bottom floor, 103-middle floor;
[0036] 401-straight line segment, 402-pin. DETAILED DESCRIPTION
[0037] The following will describe the technical solutions in the embodiments of this application in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0038] At present, when stress detection is required for chip packaging structures, strain gauges and other detection sensors need to be set on the tested part of the substrate by pasting. However, the pasting detection method has many limitations: first, the adhesive used for pasting may have unstable factors such as firmness and thermal stability, which will have a great impact on the detection results; second, since the substrate has been formed, the detection sensor can only be pasted on the surface of the substrate, but there will also be stress problems inside the substrate. Simply pasting the detection sensor on the surface cannot accurately characterize the internal stress of the substrate, and the accuracy of the stress detection result is low; third, when pasting the detection sensor, if the pasting space is small due to the setting of electronic components, it will be very difficult for personnel to perform the pasting operation, and in some cases it may be necessary to destroy the substrate, which brings great inconvenience to the setting of the detection sensor.
[0039] In view of the above situation, if Figure 1 and Figure 2As shown, the embodiment of the present application provides a chip packaging structure that can be applied to the packaging of products such as CPU / GPU, which includes a substrate 1 connecting a bare die 2 (DIE) and a PCB 3. The substrate 1 is used for fanning out the DIE signal and then interconnecting with the PCB 3 to realize the system electrical design, and includes a resistance sensor arranged on the substrate 1. This resistance sensor includes a plurality of wire modules 4 with equal resistance values. When these wire modules 4 are arranged on the substrate 1, they are integrally formed with the substrate 1, that is, the wire modules 4 are arranged on the substrate 1 during the manufacturing process of the substrate 1, so that the substrate 1 and the wire modules 4 become an integrated structure, so that there is no need to perform a pasting operation. At the same time, by molding in this way, the wire module 4 can be located at any position of the substrate 1, such as on the surface of the substrate 1, or inside the substrate 1. When the wire module 4 is located on the surface of the substrate 1, for example, when it is located on the surface where the bare chip 2 is set, and the wire module 4 is set in the area close to the bare chip 2, the stress of the local area where the bare chip 2 is located can be detected. For example, when it is located on the surface of the connected PCB 3, and the wire module 4 is set in the area close to the solder point (solder ball 5), the stress of the local area where the solder point is located can be detected. When the wire module 4 is located inside the substrate 1, the internal stress state of the substrate 1 can be detected.
[0040] The above-mentioned chip packaging structure, on the basis of meeting the requirements related to signal integrity and power integrity, on the one hand, because the wire module 4 of the resistance sensor can be set on the surface or inside the substrate 1, it can detect the stress state on the surface or inside the substrate 1, thereby more accurately characterizing the stress condition of the substrate 1; on the other hand, the wire module 4 of the resistance sensor no longer needs to be pasted with adhesive, which not only avoids the influence of factors such as the adhesive's firmness and thermal stability on the test results, but also improves the convenience of detection. Stress detection can be achieved by simply using the resistance sensor in conjunction with EDA software. This chip packaging structure can be applied to two major links: packaging process and packaging reliability. It is used to test various thermal stresses and thermomechanical stresses, and assist in completing product process risk assessment and reliability evaluation.
[0041] like Figure 2As shown, when setting the wire modules 4, multiple wire modules 4 are set around the stress part of the substrate 1 (this stress part refers to the part that needs to detect stress in the process requirements, or the part that is prone to stress), that is, each wire module 4 is set along a different direction, and the angle α between the wire modules 4 arranged adjacent to each other in the surrounding direction is 40° to 50°. Among them, the structure of all wire modules 4 is the same (for example, the overall outline shape is rectangular), and each wire module 4 has two straight segments 401 respectively close to its two ends. The two straight segments 401 of the same wire module 4 are parallel to each other. The angle α between two adjacent wire modules 4 is the angle between the straight segments 401 of the two adjacent wire modules 4. The reason for setting the angle range of 40° to 50° is that such setting of the wire modules 4 can enable different wire modules 4 to detect stress in different directions more accurately and comprehensively, thereby improving the detection performance of the resistance sensor. Preferably, the angle α between two adjacent wire modules 4 is 45°.
[0042] Furthermore, the plurality of conductor modules 4 includes at least three conductor modules, and the central angle β corresponding to the distribution of all conductor modules 4 in the surrounding direction is at least 90°, as shown in FIG. Figure 2 As shown. The reason why there are at least three wire modules 4 and the distribution angle β is not less than 90° is because the substrate 1 is subjected to stress in three directions: the X direction, the Y direction perpendicular to the X direction, and the direction of the resultant force between the X and Y directions. In order to fully detect stress in each direction, it is necessary to set a wire module 4 in each direction. Therefore, at least three wire modules 4 are required. In order to simplify the structure and reduce the probability of interference with other circuits on the substrate 1 due to the installation of the wire modules 4, it is preferably to set three wire modules 4. In addition, for the silicon wafer-level chip packaging structure, more wire modules 4 can be set according to the different crystal orientations of the silicon, and all wire modules 4 can be distributed at equal angles in the circumferential direction.
[0043] Specifically, such as Figure 2 As shown, the conductor modules 4 are formed by bending and stretching conductors. When the conductors of all conductor modules 4 are made of the same material, the resistance of each conductor module 4 can be made uniform by ensuring that the conductor length and width of each conductor module 4 are the same. When the conductors of different conductor modules 4 are made of different materials, the length of each conductor module 4 is determined based on the resistivity of each material. When stress is applied to the substrate 1, the conductors will undergo slight deformation along with the substrate 1, resulting in slight changes in the conductor's cross-sectional area and length, which in turn changes the resistance of the conductor modules 4. This resistance change can be used to detect stress.
[0044] In this application, the preferred wire width L1 is 15um to 30um, the wire length L2 is at least 20,000um, and the spacing L3 between adjacent curved wire segments is 15um to 30um. This numerical range not only enables the wire module 4 to more accurately perform stress detection, but also ensures that the area occupied by the wire module 4 on the substrate 1 is not too large, thereby minimizing the possibility of interference between the wire module 4 and other circuits on the substrate 1.
[0045] In addition, other requirements need to be met when setting the wire module 4 on the substrate 1: on the one hand, the winding size and spacing of the wire module 4 must meet the minimum process requirements of the wiring of the substrate 1. On this basis, a reasonable occupied area can be designed in combination with actual product requirements and test requirements; on the substrate layer (the substrate 1 generally includes multiple layers, and this substrate layer refers to one layer of the substrate 1), the outer periphery of the trace is usually copper foil. When determining the setting position of the wire module 4, it is necessary to make the wire module 4 and the copper foil have a certain safety distance (that is, electrical spacing, usually electrical characteristics, specifically in this application refers to a stress characteristic, that is, there can be no stress coupling between the copper foil and the trace) to prevent other factors from interfering with the test results. The value range of this safety distance is 50um~90um.
[0046] The substrate 1 is usually a multi-layer structure, which is used for interconnection routing and via fan-out. The top layer 101 of the substrate 1 is usually soldered to the bare chip 2 through bumps, and the bottom layer 102 of the substrate 1 is connected to the PCB 3 through solder balls 5. Figure 1 As shown, the substrate 1 includes a top layer 101 on which the bare die 2 is disposed, a bottom layer 102 connected to the PCB 3, and a plurality of intermediate layers 103 located between the top layer 101 and the bottom layer 102. Based on this, the conductor modules 4 can be arranged in a variety of different ways. In a first arrangement, each conductor module 4 is arranged in an intermediate layer 103, and all conductor modules 4 are arranged in a plurality of consecutive adjacent intermediate layers 103. For example, when the intermediate layers 103 include a first layer, a second layer, a third layer, a fourth layer, and a fifth layer, and the conductor module 4 includes three conductor modules 4, the three conductor modules 4 can be arranged in the first layer, the second layer, and the third layer, or in the second layer, the third layer, and the fourth layer, or in the third layer, the fourth layer, and the fifth layer, respectively. In this way, the stress inside the substrate 1 can be detected more accurately. In addition, when the conductor module 4 is arranged in the next layer, it is necessary to rotate the conductor module 4 45° around the stress location relative to the conductor module 4 arranged in the previous layer, and ensure that the conductor modules 4 on three consecutive adjacent layers have the same rotation direction. The three conductor modules 4 are connected by vias.
[0047] In the second setting method, all the wire modules 4 can be set on the same middle layer 103 and distributed at equal angles around the stress position on the same middle layer 103, with an angle of 45°. In this way, a more targeted and accurate detection can be performed on a certain layer in the substrate 1.
[0048] In the third setting method, all the wire modules 4 are set on the top layer 101 or the bottom layer 102. When all the wire modules 4 are set on the top layer 101 and distributed around the area where the bare chip 2 is located, the stress of the local area where the bare chip 2 is located can be detected; when all the wire modules 4 are set on the bottom layer 102 and distributed around the area where the solder ball 5 is located, the stress of the local area where the solder ball 5 is located can be detected.
[0049] Specifically, during the integrated molding process, the wire module 4 is etched into the top layer 101, bottom layer 102, or middle layer 103 of the substrate 1 through an etching process to achieve an integrated molding with the substrate 1. This allows the resistance sensor to be manufactured simultaneously with the substrate 1, eliminating the need for gluing during testing. The etching process is a process that is more compatible with the manufacturing process of the substrate 1, so it is preferably used to integrate the wire module 4 on the substrate 1. Alternatively, the wire module 4 can be integrally molded onto the substrate 1 using other methods, such as sintering.
[0050] like Figure 1 As shown, each wire module 4 has two pins 402 , one pin 402 of all wire modules 4 is interconnected and fanned out to form a common output end, and the other pins 402 of all wire modules 4 are fanned out separately to form multiple independent output ends. Each wire module 4 is formed by bending a wire, and the two ends of this wire are two pins 402. When set on the substrate 1, the pins 402 of all wire modules 4 need to be fanned out. Since the substrate 1 is connected to the PCB 3 through the solder balls 5, the fanning out of the wire module 4 is to punch holes in the substrate 1 so that the pins 402 are connected to the solder balls 5. When there are three wire modules 4, if each pin 402 of all wire modules 4 is fanned out separately, it needs to be connected to six solder balls 5. The circuit is complex and occupies a large number of solder balls 5. Therefore, the present application first interconnects one pin 402 of each wire module 4 to form a common output end, and then makes the other pin 402 of each wire module 4 form an independent output end and fan out (the reason for setting the independent output end is because the resistance value of each wire module 4 needs to be detected separately). In this way, only four solder balls 5 need to be occupied (one for the common output end and one for each of the three independent output ends), which simplifies the circuit and reduces the number of occupied solder balls 5.
[0051] In summary, the design and use process of the resistance sensor is as follows:
[0052] 1. Determine the object to be tested:
[0053] The chip packaging structure will generate stress due to the mismatch of material parameters, resulting in a decrease in process yield. When designing a resistance sensor, it is necessary to determine the position of the object to be measured, such as the position of the solder ball 5 of the substrate 1 and the position of the trace. After the object to be measured is determined, the design can be carried out on the corresponding substrate layer.
[0054] 2. Wire module design:
[0055] Three wire modules 4 with equal resistance are set to form a resistance sensor. There is no overlapping area between the wire modules 4. The angle between adjacent wire modules 4 is 45°. Each wire module 4 itself is a metal wire with a certain resistance. When designing the wire module 4, it is necessary to design the line width, line spacing, and line length. In this application, the line width is selected to be 20um, the line spacing is 20um, the angle between adjacent wire modules 4 is 45°, and the total line length is greater than 20000um.
[0056] 3. Interconnect Fan-out
[0057] After completing the design of the three wire modules 4, they need to be fanned out to the solder ball 5 position of the substrate 1. Each wire module 4 has two pins 402. One pin 402 of each wire module 4 is interconnected to form a common output end, and the other pin 402 of each wire module 4 is fanned out separately to form three independent output ends, where the common output end fans out to one solder ball 5, and the three independent output ends fan out to three solder balls 5 respectively.
[0058] 4. Measurement:
[0059] Measurements can be divided into package-level and system-level measurements according to measurement requirements. For package-level measurements, four low-resistance wires are soldered to the four output terminals of the resistance sensor, and the soldering points are heat-protected to prevent melting at 260°C. The soldered components are then connected to the test equipment for testing. For system-level measurements, a single package (this single package refers to the packaged chip package structure) needs to be soldered to PCB3, and then the leads from PCB3 are connected to the test equipment.
[0060] The above chip packaging structure is applicable to the traditional packaging substrate level and the silicon wafer level; it can also be applied to the advanced packaging level, and resistance sensors can be set at different interconnected objects.
[0061] Based on the above-mentioned chip packaging structure, the present application also provides a chip packaging module, which has the above-mentioned chip packaging structure. The beneficial effects of the chip packaging structure brought about by this chip packaging module can be found in the above content and will not be repeated here.
[0062] The above describes the basic principles of the present application in combination with specific embodiments, but it should be noted that the advantages, benefits, effects and the like mentioned in the present application are only examples and are not limiting, and these advantages, benefits, effects and the like cannot be considered as necessary for each embodiment of the present application. In addition, the above specific details disclosed are only for the purpose of illustration and understanding, and are not limiting, and the above details do not limit the present application to be necessarily implemented with the above specific details.
[0063] The block diagrams of the devices, apparatuses, equipment, systems involved in the present application are only illustrative examples and are not intended to require or imply the connection, arrangement, configuration shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, systems can be connected, arranged, configured in any manner. Words such as "include", "contain", "have" and the like are open-ended words, mean "including but not limited to", and can be used interchangeably. The words "or" and "and" used herein mean the word "and / or", and can be used interchangeably unless the context clearly indicates otherwise. The word "such as" used herein means the phrase "such as but not limited to", and can be used interchangeably.
[0064] It should also be noted that in the devices, equipment and methods of the present application, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions of the present application.
[0065] The above description of the disclosed aspects is provided so that any person skilled in the art can make or use the present application. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but is intended to be accorded the widest scope consistent with the principles and novel features disclosed herein.
[0066] It should be understood that the adjectives "first", "second", "third", "fourth", "fifth" and "sixth" used in the embodiments of the present application are only used for clearer description of the technical solutions, and cannot be used to limit the protection scope of the present application.
[0067] The above description has been given for the purpose of illustration and description. Furthermore, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.
Claims
1. A chip packaging structure, characterized in that: include: Substrate, used to connect the die and PCB; The resistance sensor includes a plurality of integrally formed wire modules disposed inside or on the surface of the substrate for detecting stress of the substrate, wherein the resistance values of the plurality of wire modules are equal.
2. The chip packaging structure according to claim 1, wherein: The plurality of conductor modules are arranged around the stress portion of the substrate, and the angle between the adjacent conductor modules in the surrounding direction is 40° to 50°.
3. The chip packaging structure according to claim 2, wherein: The conductor modules include at least three, and the central angle corresponding to the distribution of all the conductor modules in the surrounding direction is at least 90°.
4. The chip packaging structure according to claim 1, wherein: The substrate includes a top layer on which a bare chip is disposed, a bottom layer connected to a PCB, and a plurality of intermediate layers located between the top layer and the bottom layer, and: Each of the wire modules is arranged in one of the intermediate layers, and all of the wire modules are arranged in a plurality of consecutively adjacent intermediate layers; Alternatively, all the wire modules are arranged in the same middle layer.
5. The chip packaging structure according to claim 1, wherein: The substrate comprises a top layer for arranging the bare chip and a bottom layer for connecting to the PCB, and all the wire modules are arranged on the top layer or the bottom layer.
6. The chip packaging structure according to claim 4 or 5, characterized in that: The wire module is etched on the top layer, the bottom layer or the middle layer to be integrally formed with the substrate.
7. The chip packaging structure according to claim 1, wherein: Each of the wire modules has two pins. One of the pins of all the wire modules is interconnected and fanned out to form a common output end, and the other pins of all the wire modules are fanned out separately to form multiple independent output ends.
8. The chip packaging structure according to claim 1, wherein: The wire module is formed by bending and extending the wire.
9. The chip packaging structure according to claim 8, wherein: The wire has a line width of 15um to 30um, a line length of at least 20,000um, and a spacing between adjacent bending line segments of 15um to 30um.
10. A chip packaging module, characterized in that: A chip packaging structure comprising the chip packaging structure according to any one of claims 1 to 9.