ECG system and ESD protection structure thereof
By designing a multi-layer circuit board and a two-stage TVS protection circuit in the ECG system, the problem of static electricity escaping to other chips during the ECG system's electrostatic discharge test was solved, achieving stable static discharge and chip protection.
Patent Information
- Application Number
- CN202422644320.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2034-10-30
AI Technical Summary
In the electrostatic discharge test of existing ECG systems, it is difficult for the input end to stably pass the ESD standard. Static electricity can easily run to the pins of other chips, causing chip damage.
An ESD protection structure is constructed in the ECG system, including a multi-layer circuit board design, multiple metal vias and TVS tubes, forming a two-stage TVS protection circuit. Static electricity is released to the negative pole of the power supply through the shortest path, protecting the analog front-end chip and other chips.
It effectively reduces the movement of static electricity on other chip pins, protects the chip, and achieves stable static discharge of the ECG system to meet ESD standards.
Smart Images
Figure CN223452147U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the field of ECG, especially to an ECG system and an ESD protection structure thereof. BACKGROUND
[0002] Since the detection foot (PAD) of an ECG (Electrocardiogram) product for collecting and inputting an electrocardiogram signal is exposed, contact discharge needs to be performed. When static electricity testing is performed, the probe for releasing static electricity directly contacts the PAD, and then releases static electricity. Since a medical ECG product needs to pass through ESD of ±6kV, it is difficult to ensure that the ESD standard is stably passed through by simply increasing the TVS tube at the input end (i.e., the PAD).
[0003] The above information disclosed in the background section is only included to enhance the understanding of the background of the present disclosure, and thus can include information that does not form the prior art known to those of ordinary skill in the art at the time of the present disclosure. SUMMARY
[0004] The utility model solves the technical problem in that, in view of the above ESD discharge requirement of the prior art, an ECG system and an ESD protection structure thereof are provided.
[0005] The utility model solves the technical problem by adopting the following technical scheme:
[0006] On the one hand, an ESD protection structure of an ECG system is constructed, which comprises a circuit board, the circuit board comprises a multilayer structure stacked from top to bottom, the multilayer structure comprises a component circuit layer located at the topmost part and a system ground layer and an analog front-end ground layer below the component circuit layer, the component circuit layer is provided with an analog front-end circuit comprising a detection electrode and a power supply negative electrode;
[0007] The component circuit layer is provided with a plurality of first metal vias penetrating to the analog front-end ground layer and a plurality of second metal vias penetrating to the system ground layer in the thickness direction of the circuit board;
[0008] The plurality of first metal vias are arranged around the detection electrode, and the plurality of second metal vias are arranged around the power supply negative electrode, so that the static electricity of the detection electrode is released to the power supply negative electrode in the optimal path, thereby reducing the static electricity running to the pins of other chips.
[0009] Further, in the ESD protection structure of the ECG system, the component circuit layer comprises an analog front-end ground partition and a system ground partition, the analog front-end ground partition is communicated with the analog front-end ground layer through a third metal via, and the system ground partition is communicated with the system ground layer through a fourth metal via.
[0010] The analog front-end ground partition is connected with the system ground partition through a plurality of first TVS tubes which are distributed in different positions.
[0011] Further, in the ESD protection structure of the ECG system, the analog front-end circuit is arranged inside the analog front-end ground partition, and the system ground partition is arranged around the outer ring of the analog front-end ground partition.
[0012] Further, in the ESD protection structure of the ECG system, the first TVS tube is also connected in parallel with a first resistor with a resistance value of zero.
[0013] Further, in the ESD protection structure of the ECG system, the analog front-end ground partition surrounds the detection electrode, and the first metal via is formed on the analog front-end ground partition, and the system ground partition surrounds the negative electrode of the power supply, and the second metal via is formed on the system ground partition.
[0014] Further, in the ESD protection structure of the ECG system, the analog front-end circuit further comprises an analog front-end detection chip, the detection electrode and the analog front-end detection chip are connected through a two-stage TVS protection circuit, and the two-stage TVS protection circuit is connected in a π type structure along the edge of the detection electrode.
[0015] Further, in the ESD protection structure of the ECG system, the first metal via surrounds the detection electrode and the two-stage TVS protection circuit together.
[0016] Further, in the ESD protection structure of the ECG system, the two-stage TVS protection circuit comprises a second TVS tube with a low capacitance value, a third TVS tube with a high capacitance value, and a second resistor, the detection electrode is connected to the analog front-end detection chip through the second resistor, one end of the second TVS tube is connected between the detection electrode and the second resistor, and the other end is connected to the analog front-end ground partition, one end of the third TVS tube is connected between the analog front-end detection chip and the second resistor, and the other end is connected to the analog front-end ground partition.
[0017] In the second aspect, an ECG system is constructed, which comprises the ESD protection structure as described above.
[0018] The ECG system and the ESD protection structure thereof have the following beneficial effects: in the utility model, a plurality of first metal via holes penetrating to an analog front end ground layer and a plurality of second metal via holes penetrating to a system ground layer are arranged on a component circuit layer in a thickness direction of a circuit board, the plurality of first metal via holes are arranged around the detection electrode, and the plurality of second metal via holes are arranged around the power supply negative electrode, so that electrostatic of the detection electrode is released to the power supply negative electrode in the shortest path, electrostatic is prevented from running to pins of other chips, and the analog front end chip and the other chips are protected. BRIEF DESCRIPTION OF DRAWINGS
[0019] In order to more clearly illustrate the technical scheme in the embodiments of the utility model or the prior art, the following will briefly introduce the drawings needed to be used in the embodiment or the prior art description, and obviously, the drawings in the following description are only the embodiments of the utility model, and for those skilled in the art, other drawings can also be obtained according to the provided drawings without creative labor:
[0020] Figure 1 It is a circuit board sectional view in the ESD protection structure of the utility model;
[0021] Figure 2 It is a schematic diagram of the layout of the TVS tube protection between the analog front end ground partition and the system ground partition;
[0022] Figure 3 It is a schematic diagram of the layout of the TVS tube protection between the analog front end ground partition and the system ground partition;
[0023] Figure 4 It is a schematic diagram of the layout of the TVS tube protection between the analog front end ground partition and the system ground partition;
[0024] Figure 5 It is a schematic diagram of the layout of the TVS tube protection between the analog front end ground partition and the system ground partition;
[0025] Figure 6 It is a schematic diagram of the layout of the TVS tube protection between the analog front end ground partition and the system ground partition;
[0026] Figure 7 It is a schematic diagram of the layout of the TVS tube protection between the analog front end ground partition and the system ground partition;
[0027] In the drawings, various reference signs represent:
[0028] 100, detection electrode; 200, second resistor; 300, second TVS tube; 400, third TVS tube; 500, first metal via hole; 600, first TVS tube; 700, second metal via hole; 800, power supply negative electrode; 900, analog front end detection chip. DETAILED DESCRIPTION
[0029] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The drawings show typical embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive. It should be understood that the embodiments of the present application and the specific features in the embodiments are detailed descriptions of the technical solutions of the present application, and are not limitations of the technical solutions of the present application. In the case of no conflict, the technical features in the embodiments of the present application and the embodiments can be combined with each other.
[0030] Reference Figure 1 The ESD protection structure of the ECG system includes a circuit board PCB, and the thickness direction of the PCB is defined as the up-down direction. The circuit board includes a multi-layer structure stacked from top to bottom. Each layer of the structure specifically includes a circuit layer and an insulating layer, and the insulating layer is located below the circuit layer. The circuit layer in the top layer of the multi-layer structure is the component circuit layer, and this layer is the outer layer of the PCB, and various circuits (components, circuits, etc.) related to the ECG circuit need to be arranged on it, and the other circuit layers below it belong to the inner layer of the PCB.
[0031] Among them, the component circuit layer is specifically provided with a positive electrode of a power supply, a negative electrode of the power supply, an analog front-end circuit (also referred to as an AFE circuit) and other circuits. The positive electrode of the power supply and the negative electrode of the power supply are used to connect a battery or an external power supply.
[0032] As Figure 2 The AFE circuit includes a detection electrode 100, an analog front-end detection chip (AFE chip) 900, etc. When doing electrostatic test, the probe releasing static electricity directly contacts the detection electrode 100, and then releases. The ECG system contains many chips, and each chip has a power supply and a ground. In this paper, GND represents the ground of the ECG main chip, and this ground is the system ground. The system ground is directly connected to the negative electrode of the power supply, and the ground of other chips is connected to the system ground. The ground of the AFE chip is represented by AGND, and this ground is the analog front-end ground mentioned in this paper. In this embodiment, the detection electrode 100 and the AFE chip 900 are connected through two-stage TVS protection circuit. Continue to refer to Figure 2The two-stage TVS protection circuit comprises a second TVS tube 300 with a low capacitance, a third TVS tube 400 with a high capacitance, and a second resistor 200. The detection electrode 100 is connected to the AFE chip 900 through the second resistor 200. One end of the second TVS tube 300 is connected between the detection electrode 100 and the second resistor 200, and the other end is connected to AGND. One end of the third TVS tube is connected between the AFE chip 900 and the second resistor 200, and the other end is connected to AGND. The parasitic capacitance on the resistor 200 and the subsequent TVS tube 400 forms a low-pass filter. The low-pass filter sets a cutoff frequency, which prevents interference signals greater than the frequency from entering the system. The low capacitance of the front TVS tube 300 is to prevent distortion of the collected signal. The high capacitance of the rear TVS tube 400 is to form a low-pass filter with the resistor 200 to obtain a specific cutoff frequency. Because the resistor 200 cannot be too large, the capacitance value needs to be increased, so when selecting the TVS tube 400, the parasitic capacitance value of the device needs to be considered. In this way, the embodiment can realize the effect of two-stage electrostatic protection and low-pass filtering. In addition, as shown in Figure 5 , the two-stage TVS protection circuit is connected along the edge of the detection electrode to form a π-type structure, and the second resistor 200 is approximately placed along the tangent direction of the detection electrode 100. The second TVS tube 300 and the third TVS tube 400 are approximately placed in the radial direction of the detection electrode 100 and connected to the AGND around the detection electrode 100.
[0033] The analog front-end ground partition (AGND partition) and the system ground partition (GND partition) are included on the component circuit layer. The AGND partition provides AGND for the circuit on the component circuit layer, and the GND partition provides GND for the circuit on the component circuit layer.
[0034] In this embodiment, starting from the top down, the second layer is the system ground layer (GND layer), and the third layer is the analog front-end ground layer (AGND layer). It can be understood that this embodiment is only an example, and in fact the specific levels of the GND layer and the AGND layer are not limited, as long as they are below the component circuit layer. The AGND partition and the GND partition are generally small areas or lines on the outer layers of the PCB. Unlike the AGND partition and the GND partition, the GND layer and the AGND layer are the inner layers of the PCB, which are generally large metal grounds, as shown in Figure 6 According to Ohm's law, the GND layer is a whole layer, and increasing the width of the conductor will greatly reduce the impedance compared to a single GND line on the component circuit layer. As shown in Figure 1As shown, the AGND partition on the component circuit layer needs to be connected to the AGND layer through metal vias, and the GND partition on the component circuit layer needs to be connected to the GND layer through metal vias.
[0035] like Figure 3 As shown, the AFE circuit is arranged inside the AGND partition, and the GND partition is arranged around the outer circle of the AGND partition. Figure 3 This does not represent the actual PCB layout, but only illustrates a concept. The AGND partition on the component circuit layer is connected to the GND partition through multiple first TVS tubes 600, and the multiple first TVS tubes 600 are scattered in different locations. The so-called scattered in different locations can be understood as being placed at a distance rather than side by side. The first TVS tube 600 is also connected in parallel with a first resistor with zero resistance, such as Figure 3 In the example, ESD9 is one of the first TVS diodes 600, and R15 and R25 are two first resistors. It is understood that the resistance value of zero is not limited to being absolutely equal to or identical to zero in mathematical terms, and does not exclude the possibility of using other lower resistance values. The zero resistance value here emphasizes that it can be close in engineering terms or within an acceptable error range when practicing the rights described in this patent.
[0036] refer to Figure 5 In this embodiment, in order to shorten the discharge path and reduce the impedance, on the one hand, a plurality of first metal vias 500 are provided on the component circuit layer, which pass through the AGND layer in the thickness direction of the circuit board. The AGND partition surrounds the detection electrode 100, and the first metal via 500 is specifically opened on the AGND partition on the component circuit layer, and a plurality of the first metal vias 500 are provided around the detection electrode 100. If the two-stage TVS protection circuit is not designed in other embodiments, the plurality of the first metal vias 500 can be arranged in a circle around the detection electrode 100. Because two-stage TVS protection circuits are added in this embodiment and the two-stage TVS protection circuits are connected along the edge of the detection electrode to form a π-shaped structure, the plurality of the first metal vias 500 in this embodiment surround the detection electrode 100 and the two-stage TVS protection circuit together. Figure 5 In the example, the first metal via 500 is arranged along the detection electrode 100 until it encounters two TVS diodes, then it is arranged along the TVS diodes, ultimately enclosing the detection electrode 100 and the two-stage TVS protection circuit as much as possible. This allows static electricity to be quickly discharged to the AGND layer inside the PCB.
[0037] refer to Figure 7In the embodiment, in order to further shorten the discharge path and reduce impedance, a plurality of second metal vias 700 are arranged on the component circuit layer and penetrate the GND layer in the thickness direction of the circuit board. The GND partition surrounds the negative electrode of the power supply, and the second metal vias 700 are arranged on the GND partition of the component circuit layer. The plurality of second metal vias 700 surround the negative electrode 800, so that static electricity is quickly returned to the negative electrode 800 through the GND layer.
[0038] The beneficial effect of the embodiment is that the π-type network circuit composed of the TVS tube and the resistor has two-stage protection measures. The components of the two-stage protection circuit are connected along the edge of the detection electrode to form a π-type structure. The detection electrode 100 is surrounded by the AGND of the AFE, and the AGND is designed with multiple holes (first metal vias 500). The AGND of the AFE is connected to the GND through the multiple-point TVS tube 600. In this way, the static electricity of the detection electrode 100 is discharged to the AGND layer in the optimal (shortest, smallest impedance) path. The AGND layer quickly conducts the static electricity to the GND layer, and the GND layer is connected to the negative end of the battery or the negative end of the power supply with the lowest impedance. The static electricity can be quickly returned to the input negative end, reducing the static electricity running to the pins of other chips, and protecting the AFE chip and other chips.
[0039] It should be noted that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements can also be present. As used herein the terms "vertical", "horizontal", "left", "right", and the like are merely used for the purpose of explanation.
[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0041] The terms "first", "second", and the like, as used in the description of the specification, can be used to describe various constituent elements, but these constituent elements are not limited by these terms. The purpose of using these terms is only to distinguish one constituent element from other constituent elements. For example, a first constituent element can be named as a second constituent element without departing from the scope of the application, and similarly, a second constituent element can be named as a first constituent element. The "connection" or "connection" not only includes directly connecting two entities, but also indirectly connecting through other entities with beneficial improvement effects.
[0042] The embodiments of the present application are described above with reference to the drawings; however, the present application is not limited to the specific embodiments described above, but the specific embodiments described above are merely illustrative rather than restrictive, and a person of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the purpose of the present application and the scope protected by the claims, and these all belong to the protection of the present application.
Claims
1. An ESD protection structure for an ECG system, characterized in that: The circuit board comprises a multi-layer structure stacked from top to bottom, the multi-layer structure comprising a component circuit layer at the top and a system ground layer and an analog front-end ground layer below the component circuit layer, wherein an analog front-end circuit including a detection electrode and a negative power supply electrode are provided on the component circuit layer; The component circuit layer is provided with a plurality of first metal vias penetrating the analog front-end ground layer and a plurality of second metal vias penetrating the system ground layer along the thickness direction of the circuit board; A plurality of first metal vias are arranged around the detection electrode and a plurality of second metal vias are arranged around the negative power supply electrode, so as to release the static electricity of the detection electrode to the negative power supply electrode in an optimal path, thereby reducing the static electricity from running to the pins of other chips.
2. The ESD protection structure of the ECG system according to claim 1, wherein: The component circuit layer includes an analog front-end ground partition and a system ground partition, the analog front-end ground partition is connected to the analog front-end ground layer through a third metal via, and the system ground partition is connected to the system ground layer through a fourth metal via; The analog front-end ground partition is connected to the system ground partition through a plurality of first TVS tubes, and the plurality of first TVS tubes are distributed in different positions.
3. The ESD protection structure of the ECG system according to claim 2, wherein: The analog front-end circuit is arranged inside the analog front-end ground partition, and the system ground partition is arranged around the outer ring of the analog front-end ground partition.
4. The ESD protection structure of the ECG system according to claim 2, wherein: The first TVS tube is further connected in parallel with a first resistor with zero resistance.
5. The ESD protection structure of the ECG system according to claim 2, wherein: The analog front-end ground partition surrounds the detection electrode and the first metal via is opened on the analog front-end ground partition. The system ground partition surrounds the negative power supply electrode and the second metal via is opened on the system ground partition.
6. The ESD protection structure of the ECG system according to claim 2, characterized in that: The analog front-end circuit also includes an analog front-end detection chip. The detection electrode and the analog front-end detection chip are connected via a two-stage TVS protection circuit. The two-stage TVS protection circuit is connected along the edge of the detection electrode to form a π-shaped structure.
7. The ESD protection structure of the ECG system according to claim 6, characterized in that: The plurality of first metal vias surround the detection electrode and the two-stage TVS protection circuit.
8. The ESD protection structure of the ECG system according to claim 6, wherein: The two-stage TVS protection circuit includes a second TVS tube with low capacitance, a third TVS tube with high capacitance, and a second resistor. The detection electrode is connected to the analog front-end detection chip through the second resistor; one end of the second TVS tube is connected between the detection electrode and the second resistor, and the other end is connected to the analog front-end ground partition; one end of the third TVS tube is connected between the analog front-end detection chip and the second resistor, and the other end is connected to the analog front-end ground partition.
9. An ECG system, characterized in that The invention comprises the ESD protection structure according to any one of claims 1 to 8.